experimental validation of a space-vector-modulation algorithm for

1282 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 4, APRIL 2011

Experimental Validation of aSpace-Vector-Modulation Algorithm for Four-Leg

Matrix ConvertersRoberto Cárdenas, Senior Member, IEEE, Rubén Peña, Member, IEEE, Patrick Wheeler, Member, IEEE, and

Jon Clare, Senior Member, IEEE

Abstract—Most variable-speed ac generation systems use back–to-back converters to supply electrical energy, with fixed electricalfrequency and voltage, to a stand-alone load or grid. Matrix con-verters (MCs) are a good alternative to back-to-back convertersbecause they have several advantages in terms of size and weight.Therefore, MCs can be advantageously used in any variable-speedgeneration system where high efficiency, reliability, small size,and low weight are considered important factors. Nevertheless, tointerface an MC-based generation system to an unbalanced 3φstand-alone load, a four-leg MC is required to provide a path forthe zero-sequence load current. Space-vector-modulation (SVM)algorithms for the operation of four-leg MCs have been proposedin the literature. However, these modulation methods have highcomputational burdens, and they are difficult to implement, evenin fast DSP-based control platforms. Therefore, only simulationresults have been reported in these publications. In this paper, anSVM algorithm is optimized and experimentally tested. Moreover,the harmonics produced in the input current when a four-leg MCis feeding an unbalanced or nonlinear load are also mathemati-cally analyzed in this paper, with experimental verification beingprovided.

Index Terms—AC–AC power conversion, modulation, powergeneration.

I. INTRODUCTION

MATRIX CONVERTERS (MCs) have many advantages,which are well documented in the literature [1]–[5]. A

MC provides bidirectional power flow, sinusoidal input/outputcurrents, and controllable input-displacement factor [3], [4].When compared with back-to-back converters, the MC hassome significant advantages. For instance, due to the absence ofelectrolytic capacitors, the MC can be more robust and reliable[6]. The space saved by an MC, compared with a conventionalback-to-back converter, has been estimated to be a factor ofthree [5].

Manuscript received August 10, 2009; revised December 20, 2009 andMay 29, 2010; accepted July 15, 2010. Date of publication August 30, 2010;date of current version March 11, 2011. This work was supported in partby the Fondecyt Chile under Contract 1085289 and in part by the IndustrialElectronics and Mechatronics Millennium Nucleus.

R. Cárdenas is with the Electrical Engineering Department, University ofSantiago de Chile, Santiago 9170124, Chile (e-mail: [email protected]).

R. Peña is with the Electrical Engineering Department, University of Con-cepción, Concepción 4074580, Chile (e-mail: [email protected]).

P. Wheeler and J. Clare are with the Department of Electrical and ElectronicEngineering, University of Nottingham, NG7 2RD Nottingham, U.K. (e-mail:[email protected], [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2010.2068531

Fig. 1. Control system for a variable-speed diesel-generation system.

The advantages of variable-speed generation are also known[7]–[9]. For wind-energy conversion systems, variable-speedoperation of the generator produces a higher aerodynamicefficiency [7], less mechanical stress in some parts of the wind-energy conversion system, e.g., the gearbox and blades, and thepower output is smoother when compared with that producedby fixed-speed wind turbines [9]. Recently, a relatively newtopology, suitable for wind–diesel systems or variable-speeddiesel generation to a stand-alone load, has been reported[10], [11]. In this case, a standard diesel-generation system isoperated (see Fig. 1) following an optimal power–speed char-acteristic. For this topology, the efficiency is improved becausediesel engines have high fuel consumption when operated atlight loads and constant speed [11], [12]. Moreover, a dieselengine operating at high rotational speeds can increase itspower output well beyond that obtained at the synchronousvelocity [11], [12]. Therefore, a mobile generation system canbe implemented using a relatively small variable-speed engine[12]. This allows for considerable weight and size reduction.Moreover, if a four-leg MC is used to feed a stand-aloneunbalanced load, a further reduction in the size of the generationsystem is accomplished because the bulky dc-link capacitorsare eliminated from the topology [1].

Space-vector-modulation (SVM) algorithms for MCs havemany advantages and can be modified to address additionalcontrol objectives, for example, to reduce the MC input cur-rent and total harmonic distortion (THD) [13], to minimize

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CÁRDENAS et al.: EXPERIMENTAL VALIDATION OF SVM ALGORITHM FOR FOUR-LEG MATRIX CONVERTERS 1283

the output-current distortion [14], or to compensate the input-voltage unbalance [15]. However, for the autonomous variable-speed generation system shown in Fig. 1, a four-leg MC isrequired in order to provide an electrical path for the circulationof the zero-sequence current in the load. Therefore, the standardmodulation algorithm used in 3 × 3 MCs [16], [17] is notapplicable to this configuration.

A modulation algorithm for four-leg MCs was presented in[18]. The method presented was based on the fictitious dc-linkapproach [19], and SVM was not discussed in that work. AnSVM algorithm suitable for four-leg MCs is discussed in [20]and [21]. However, the implementation of the SVM proposedin [20] and [21] requires a very large computational effortand could not be implemented even when a very fast C6711DSP board is used in the experimental work. Therefore, onlysimulation results for the SVM algorithm are presented in [20]and [21].

In this paper, an SVM algorithm suitable for the controlof a four-leg MC is discussed and experimentally validated.The method is based on the SVM algorithm presented bythe authors in [21]. However, the modulation algorithm hasbeen modified and mathematically optimized to reduce thecomputational burden required for a digital implementation.Moreover, because of the lack of dc capacitors in the MC,the input current is distorted when the generation system isfeeding an unbalanced or nonlinear load. This is analyzedin Section III-B, and experimental results are discussed inSection IV-A.

The SVM discussed in this paper is implemented using aspace-vector representation in a 3-D α–β–γ space, describingthe output voltage and switching states. The modulation tech-nique discussed in this paper enables the MC to provide the out-put line-to-neutral voltages (balanced or unbalanced) requiredat the load. This 3-D approach for the output is combined withthe control of the phase-angle shift between the fundamentalcomponents of the input-current and input-voltage vectors. Tothe best of our knowledge, this is the first publication whereexperimental validation of an SVM algorithm suitable for four-leg MCs is presented.

Fig. 2 shows the four-leg MC and filters used in the ex-perimental work discussed in Section IV. A second order LCfilter is used at the MC input to improve the quality of theinput currents [22]. The input-filter capacitors also provide theessential decoupling to minimize the commutation inductancebetween phases. Usually, a resistor in parallel with the filterinductance improves the damping of the system [23], [24].

At the MC output, a second-order LC filter is provided to re-duce the effects of the switching harmonic in the load voltages.Fig. 2 also shows the (star-connected) stand-alone load fed fromthe four-leg MC. The parameters of the input/output filters usedin this work are presented in Appendix A.

The rest of this paper is organized as follows. In Section II,the input/output space used to implement the modulation isdiscussed. In Section III, the SVM algorithm is presented. InSection IV, the experimental system and experimental resultsfor open-loop operation of the proposed modulation techniqueare analyzed. Finally, an appraisal of the modulation methoddiscussed in this paper is presented in Section V.

Fig. 2. MC and input/output filters.

II. ANALYSIS OF INPUT/OUTPUT SPACES USED IN

PROPOSED MODULATION

All SVM techniques use a set of vectors that is defined bythe instantaneous space vectors of the voltage and current at theinput and output of the converter. These vectors are a result ofthe set of switching states that the converter topology is ableto produce. For instance, to create the switching state labeled“+1” in Table I, output “a” has to be connected to input “A”,and outputs “b, c, and n” have to be connected to input “B”(see Fig. 2). For the standard 3 × 3 MC, there are 27 (33)switching states [16]. However, the addition of the fourth outputleg increases the total number of switching states to 81 (34).

For the four-leg MC as well as for the conventional 3 ×3 converter [16], not all of the switching states are usefulto implement SVM. Only the switching states that produce avector with a constant direction within the output space arenormally used. These are called “stationary vectors” and arelisted in Table I. The stationary vectors are produced by theconnection of two of the input phases to the output [16], [18]. Inaddition to these states, there are three switching combinationswhich are useful for the implementation of the SVM algorithm.These are obtained when a single input phase is connected to allof the output legs. These states do not produce any differencein the voltage across the output [16], [18]. Therefore, they aredesignated as “zero vectors.” These states are shown at the topof Table I.

A. Output Space

The output space used in SVM algorithms suitable for four-leg MCs is similar to that used for SVM of conventional four-leg voltage-source inverters [25]–[28]. The outputs “a”, ”b”,”c”, and “n” (see Table I) can be transformed into α–β–γcoordinates using the following transformation:

⎡⎣ Vα

Vβ

V γ

⎤⎦ =

23

⎡⎣ 1 −1/2 −1/2

0√

3/2 −√

3/21/(2

√2) 1/(2

√2) 1/(2

√2)

⎤⎦

⎡⎣Van

Vbn

Vcn

⎤⎦ .

(1)


TABLE IZERO AND STATIONARY FOUR-LEG MC SWITCHING STATES


Fig. 3. Three-dimensional representation of the vectors in the α–β–γ space.

Fig. 4. (a) Projection into the α–β plane of Fig. 3. (b) Three-dimensional viewof Prism 6.

Using (1), the α–β–γ components of the 42 active vectorsshown in Table I are obtained. These vectors are placed along14 directions but with different magnitudes. These directionsare shown in Fig. 3 in an α–β–γ 3-D space. Fig. 4(a) showsthe projections of the vectors of Fig. 3 into the α–β plane.As shown in this graphic, there are six triangular prisms withsix vectors in each prism. For instance, in Prism 6, the vectorsare 1, 14, 8, 9, 10, and 11. The vectors in each prism can becombined into four tetrahedrons in an α–β–γ space, each ofthem bounded by three vectors at its vertices [20], [27], [28].The tetrahedrons are aligned with one on top of the other in theγ direction.

The 3-D view of Prism 6, showing the six vectors inthe α–β–γ space, is shown in Fig. 4(b). Fig. 5 is obtainedfrom Fig. 4(b) and shows tetrahedron 4 in Prism 6, which isbounded by the space vectors V1, V9, and V11. Using thesethree vectors and the zero vectors, a demanded output voltage(v0α, v0β , v0β), located inside the tetrahedron, can be synthe-

Fig. 5. Tetrahedron 4 in Prism 6.

sized. Therefore, to generate a given voltage at the MC output,two steps are required. First, the prism where the output voltageis located has to be identified. This is simple to realize by usingthe phase angle θαβ of the output voltage in the α–β plane [see(2) and Fig. 4(a)].

The second step for the modulation of a given output vector isto identify the tetrahedron (inside the prism) where the vectoris located. As reported in [27], this can be achieved by usingthe polarity of the demanded line-to-neutral output voltages.This is shown in Table II, where van, vbn, and vcn are thedemanded line-to-neutral output voltages. The vectors used forthe modulation in a particular tetrahedron are also shown inTable II.

0 ≤ θαβ <π

3Pr . = 1

π

3≤ θαβ <

2π

3Pr . = 2

2π

3≤ θαβ < π Pr . = 3

π ≤ θαβ <4π

3Pr . = 4

4π

3≤ θαβ <

5π

3Pr . = 5

5π

3≤ θαβ < 0 Pr . = 6. (2)

B. Input Side Space

By using SVM to control the four-leg MC, the magnitude andphase of the output voltage as well as the displacement angle ofthe input current can be regulated. Therefore, the output-voltagevector and the phase of the input-current vector are decoupled.This is similar to the SVM algorithm for conventional 3 ×3 MCs presented in [16].

The input side has no neutral connection; hence, the inputvectors can be represented in the α–β coordinates (i.e., theγ components are zero). Therefore, using (1) and the inputcurrents IA, IB , and IC shown in Table I, the vectors of theinput currents in the α–β plane are calculated. These are shownin Fig. 6. An expression similar to (2) is used to calculate theinput-current sector [16].

III. SVM TECHNIQUE

Using the input and output spaces, the switching states tosynthesize the output-voltage vector with a given displacement


TABLE IISELECTION OF TETRAHEDRON FOR GIVEN PRISM

Fig. 6. Input-current vectors in the α–β plane.

TABLE IIISWITCHING STATES FOR GIVEN CURRENT AND OUTPUT VOLTAGE

angle at the input are selected. For instance, if the input-currentvector is in sector 1 (between I1 and I6) and the output-voltagevector is in tetrahedron 2 in Prism 6, the switching states shownin Table III can be used to modify the current and voltagevectors. To regulate both the input-current displacement an-gle and the output-voltage vector simultaneously, the requiredswitching states are ±1, ±3, ±4, ±6, ±16, and ±18. However,if the input current is in sector 1, the current vectors producedby the switching states have to be either I1, I6, or I3, I4.Therefore, the selected states are +1, −3, −4, +6, +16, and−18. Each vector in the tetrahedron, (e.g., v8, v10, and v11) issynthesized by two of the switching states. Finally, the outputvoltage is synthesized using the three vectors mentioned beforeand the three zero vectors.

After the switching states are selected, the next step is tocalculate the duty cycles required for the demanded outputvoltage. The methodology required to calculate the duty cyclesis similar to that reported in [21]. Therefore, only a subset of theequations discussed in [20] and [21] is repeated in this Section.

The output voltage can be obtained using Vout = V ′o + V ′′

o +V ′′′

o , where V ′o, V ′′

o , and V ′′′o are obtained from the vectors of a

particular tetrahedron as

V ′o = α1V

1 V ′′o = α2V

2 V ′′′o = α3V

3 (3)

with |αi| ≤ 1. For instance, for tetrahedron 2 in Prism 6, thethree vectors are V 1 = V8, V 2 = V10, and V 3 = V11.

Each of the vectors V ′o, V ′′

o , and V ′′′o can be obtained from

two switching states. For instance

V ′o = δIV I + δIIV II . (4)

In the same way, the voltages V ′′o and V ′′′

o are obtained asV ′′

o = (δIIIV III + δIV V IV ) and V ′′′o = (δV V V + δV IV V I),

where V I , . . . , V V I are the switching states and δI , . . . , δV I

are the six duty cycles for these states. Using βi as the phaseangle of the input-current vector measured from a line bisectingthe current sectors defined in Fig. 6 (as shown in Fig. 7), theequation required to regulate the phase of one of the inputcurrent is

(iIi δ

I + iIIi δII

)• jejβiej(Ki−1) π

3 = 0 (5)

where the symbol • represents the inner product and Ki isthe input-current sector. As discussed in [20] and [21], similar


Fig. 7. Vector diagram for the calculation of the duty cycles.

equations can be obtained for the currents (iIIIδIII + iIV δIV )and (iV δV + iV IδV I), where iIi , . . . , i

V Ii are the six current

vectors corresponding to the switching states used by the mod-ulation algorithm in a particular sampling time. The addition ofall the duty cycles is restricted by

δI + δII + δIII + δIV + δV + δV I ≤ 1. (6)

For each of the current pairs (ini , in+1i ) [see (5)], the current

magnitude is the same, i.e., |ini | = |in+1i | (see Table I). Using

this, the vector diagram of Fig. 7 and (5) yields

δI

δII=

cos(βi − π/3)cos(βi + π/3)

. (7)

In Fig. 7, the N -axis has a 90◦ phase shift with respect toii. Similar expressions to (7) are derived for δIII/δIV andδV /δV I . Using (3) and (7) in (4) yields

δI =α1|V 1| cos(βi − π/3)

|V I cos(βi − π/3) + V II cos(βi + π/3)| . (8)

After some manipulation, it can be demonstrated that the de-nominator of (8) is

∣∣V I cos(βi − π/3) + V II cos(βi + π/3)∣∣ =

32Vm cos ϕ (9)

where Vm is the amplitude of the line-to-neutral input voltageand ϕ is the displacement angle between the input-current andinput-voltage vectors. For the autonomous system of Fig. 1,unity displacement-factor operation is considered. Using (9),the duty cycle is obtained as

δn =23

αi|V i| cos(βi + (−1)|n|π/3

)Vm cos ϕ

(10)

where n varies between I, . . . , V I . The voltage in the nu-merator V i is equal to V 1 for n = I, II , V 2 for n =III, IV , and V 3 for n = V, V I . In the term (−1)|n|, |n| rep-resents the equivalent Arabic numerals of the Roman numeralsn = I, . . . , V I .

The total duty cycle for the zero vectors is calculated as

δ0 = 1 −V I∑n=I

δn. (11)

The value of α1 required for the calculation of (8) and (10) isobtained as

α1 =

[(V 2 ⊗ V 3

)• Vout

][(V 2 ⊗ V 3) • V 1]

=|Vout| cos ψ1

|V 1| cos ψ2. (12)

The symbol ⊗ denotes cross product. The term V 2 ⊗ V 3 is avector which is orthogonal to both V 2 and V 3. In (12) ψ1 andψ2 are the phase angles between this orthogonal vector and Vout

and V 1, respectively.The numerator of (12) is the projection of Vout into the

orthogonal vector. The denominator is the projection of V 1 intothe same orthogonal vector. Because the α–β–γ componentsof the 14 vectors located in the output space are known, thecalculation of (12) requires one cross-product and two inner-product operations between α–β–γ vector components whichare stored in a lookup table. A similar expression to that of (12)can be used to calculate α2 and α3.

In (12), the use of the orthogonal vector V 2 ⊗ V 3 is requiredto ensure that the calculation of α1 is independent of the vectorsV 2 and V 3. Therefore, α1 reflects only the contribution of V 1

to the output voltage Vout. Using (12) in (10), the duty-cyclecalculation is

δn =23

q cos(ψ1) cos(βi + (−1)|n| π3

)Vm cos(ψ2) cos(ϕ)

(13)

where q is the voltage transfer ratio |Vout/Vm| and the term 2/3is a constant, which is dependent on the α–β–γ transformationused.

The SVM algorithm described in this paper and its proposedimplementation considerably reduce the complexity of calculat-ing the duty cycles. Unlike the work described in previous pub-lications [20], the use of the term (3/2)Vm [see (14)] insteadof the denominator of (8) implies a considerable simplificationfor the calculation of (10). Furthermore, as shown by (13), theduty cycles are not affected by the magnitude of the vectors V 1,V 2, and V 3 in a particular tetrahedron. Therefore, in the exper-imental work, normalized unit vectors are stored in a lookuptable. With this methodology, the computation of (12) is quitestraightforward, requiring only a couple of multiplications, forthe calculation of the cross and inner products and one division.

A lookup table is used to store the switching states cor-responding to each combination of input sector and outputtetrahedron. As shown in Table III, there are 24 tetrahedronswhere the output-voltage vector could be located. For theinput current, there are six input sectors. Therefore, there are144 combinations, and for each one of them, 17 prearrangedswitching states are required (see Fig. 8, for the double-sidedswitching pattern used in this paper). Totally, the number ofprearranged switching states stored in the main lookup table is2448. The switching states are prearranged in order to minimizethe switching commutations.

Additional lookup tables, for example, to store Table IIare used in the SVM implementation. With this methodology,more processor memory is necessary, but a much reducedcomputation time is achieved. For instance, the execution timeof the SVM algorithm implemented in this paper takes about


Fig. 8. Double-sided switching pattern in a cycle period for tetrahedron 2 in Prism 6; Ki = 1.

40 μs with the TI C6713 DSP board used for the control of theexperimental prototype.

A. Modulation

Using the selected switching states and the duty cycles cal-culated from (10), (11), and (12), a switching sequence for thecontrol of the four-leg converter is generated. With reference tothe particular case discussed earlier, where the output voltagelies in tetrahedron 2 in Prism 6 and the input current is insector 1, the switching states selected are OA, OB, OC, +1,−3, −4, +6, +16, and −18. As mentioned before, in the cycleperiod, the switching states are arranged to reduce the switchingcommutations. For instance, for the double pattern shown inFig. 8, only one switch commutates for each switching-statechange, producing 16 switching commutations in each cycleperiod.

B. Input-Current Distortion for Unbalanced Conditions

An MC does not have any bulk energy-storage element.Therefore, if the converter losses are neglected, the instanta-neous input power is equal to the instantaneous output power.Assuming that the MC output has positive-, negative-, and zero-sequence signals, then the instantaneous output power can bewritten as

Po =(v+

a + v−a + v0

a

) (i+a + i−a + i0a

)+

(v+

b + v−b + v0

b

)×

(i+b + i−b + i0b

)+

(v+

c + v−c + v0

c

) (i+c + i−c + i0c

)(14)

where the superscripts “+,” “−,” and “0” denote positive-,negative- and zero-sequence components, respectively.

As is well known, the zero-sequence currents i0a, i0b , and i0care identical and calculated using [34]

i0a = i0b = i0c =13[ia + ib + ic] =

in3

(15)

with in as the neutral current. Therefore, using (15) andreplacing v0

a = v0b = v0

c = v0 cos(ωot) and i0a = i0b = i0c =i0 cos(ωot + θ0) in (14) yields

Po =[(

v+a i+a + v+

b i+b + v+c i+c

)+

(v−

a i−a + v−b i−b + v−

c i−c)

+(v+

a i−a + v+b i−b + v+

c i−c)

+(v−

a i+a + v−b i+b + v−

c i+c)

+3v0i0 cos(ωot) cos(ωot + θ0)] . (16)

If the positive- and negative-sequence components are rep-resented as rotating vectors, i.e., �v+ = v1e

jωot and �v− =v2e

−jωot, then the output power can be written as afunction of the output current and voltage vectors usingPo = (3/2)Re(�vout(�iout)c), where the superscript “c” is thecomplex-conjugate operator. The expression “Re” stands forthe real component of a complex term.

The identity cos(ωot) = (1/2)(ejωot + e−jωot) can be usedin (16) to obtain the output power as a function of negative- andpositive-sequence components only. Considering these modifi-cations, Po is calculated as

Po =(

32

)Re

[(v1e

jωot + v2e−jωot)

×(i1e

j(ωot+θ1) + i2e−j(ωot+θ2)

)c

+ voio(ejωot + e−jωot)

×(ej(ωot+θo) + e−j(ωot+θo)

)/2

]. (17)

As mentioned before, the instantaneous input power isequal to the instantaneous output power. Therefore, Po =(2/3)Re(�vi(�ii)c), where �vi and �ii are the MC voltage- andcurrent-input vectors. Assuming that the input voltage is bal-anced, the input current can be calculated as

Re(�ii)c = Re[{

(v1ejωot + v2e

−jωot)

×(i1e

j(ωot+θ1) + i2e−j(ωot+θ2)

)c

+ voio(ejωot + e−jωot)

×(ej(ωot+θo) + e−j(ωot+θo)

)/2}

e−jωit/|vi|].

(18)

In (18), ωi is the grid frequency. Finally, the input-currentcomponents can be calculated from (18) as

Re(�ii)

=Re[(

v1i1ej(ωit+θ1)+v2i2e

j(ωit−θ2)+voio cos(θo)ejωit)

+(v1i2e

j[(ωi−2ωo)t−θ2]+0.5voi0ej[(ωi−2ωo)t−θo]

)

+(v2i1e

j[(ωi+2ωo)t+θ2]+0.5voi0ej[(ωi+2ωo)t+θo]

)]

/|vi|. (19)


Therefore, when the MC feeds an unbalanced load at theoutput, the input current is distorted (but not unbalanced), andthe following frequency components may be present in theinput current.

1) A fundamental frequency (ωi) signal with a magnitudethat is dependent on the terms v1i1, v2i2, and voio.

2) A component with a frequency of (ωi − 2ωo) rad−1. Themagnitude of this signal is dependent on the terms v1i2and 0.5voio.

3) A component with a frequency of (ωi + 2ωo) rad−1. Themagnitude of this signal is dependent on the terms v2i1and 0.5voio.

Note that in (19), the load zero-sequence current componentaffects the magnitude of the three frequencies present in theinput current. This is due to the fact that a zero-sequence currentor voltage is obtained as a combination of positive and negativesequences.

The input-current THD produced by the unbalanced currentsat the output can also be calculated from (19). Assuming ahigh-power-factor load (i.e., θ0, θ1, and θ2 ≈ 0), the THD isapproximately

THD ≈√

(v1i2 + 0.5v0i0)2 + (v2i1 + 0.5v0i0)2

(v1i1 + v2i2 + v0i0). (20)

In (20), the THD is calculated as the quotient of the total rmscurrent produced by the harmonics over the rms fundamentalcurrent [29].

A further simplification of (20) is obtained when the outputfilter is implemented with a small inductance. In this case, thevoltage drop is small, and the MC output voltage is almost equalto the load voltage. If the load voltages are balanced, the zero-and negative-sequence voltages in the MC output are negligible,and (20) can be reduced to THD ≈ i2/i1, where i1 and i2 arethe magnitudes of the positive- and negative-sequence currents,respectively, at the MC output.

C. Input-Current Distortion by Harmonicsin Output Current

A possible application of a four-leg MC is to feed nonlinearloads. The input current for this situation could be obtained byassuming that the MC output current has a signal componentof frequency “nωo.” For this situation, the output power isobtained as

Po =(

32

)Re

[(v1e

jωot + v2e−jωot)

×(i1e

j(nωot+θ1) + i2e−j(nωot+θ2)

)c ]. (21)

As shown by (19), the output zero-sequence componentsgenerate distortion in the MC input current with harmon-ics of the same frequencies to those created by the out-put negative-sequence signals. Therefore, only positive- andnegative-sequence components are considered in (21).

Using the methodology discussed in the previous section [see(14)–(19)], it is relatively simple to demonstrate that four input-current frequency components are obtained in the input as a

consequence of this harmonic of order “n” in the output. Thesefrequency components are ωi + (n − 1)ωo, ωi − (n − 1)ωo,ωi + (n + 1)ωo, and ωi − (n + 1)ωo.

The extra current distortion due to output unbalance is han-dled by the generator, which is usually capable of operatingwith significant current-waveform distortion [20], [30]. Never-theless, local heating or relatively large torque pulsations mightbe produced if the load negative-sequence current is too large,and in a practical system, there will ultimately be a limit to thedegree of unbalance that can be tolerated. As reported in [30],permanent-magnet generators driven by variable-speed windturbines are usually connected to ac–dc converters which canproduce a high THD, in the range of 20%–25%. Therefore,for linear loads, the simplified equation THD ≈ i2/i1 could beused to calculate a possible limit of the load negative-sequencecurrent, i.e., i2 ≈ 0.20i1 − 0.25i1. However, further research inthe subject is required.

Interaction of the additional distortion components with theinput filter is generally not an issue since, unless the outputfrequency is particularly high, the additional components willbe placed well below the filter resonant frequency. It should benoted that any additional distortion created in the input voltageto the converter is automatically rejected from the output bythe modulation calculations. These calculations are based oninput-voltage measurements which are updated every switchingcycle.

IV. EXPERIMENTAL RESULTS

The SVM algorithm discussed in this paper has been val-idated using the experimental system shown in Fig. 9. Theproposed SVM algorithm is implemented using a DSP-basedcontrol board and a field-programmable gate array, the latterimplementing the four-step commutation method [31]–[33] andgenerating the switching signals for the insulated-gate bipolartransistor (IGBT) gate drivers [32]. The MC is connected toa three-phase variable transformer at the input. At the output,the MC is connected to a three-phase load. A second-orderLC output filter is used to reduce the harmonic content in thevoltages and currents. For this paper, only open-loop operationis considered. Closed-loop control of the output voltage is con-sidered outside the scope of this paper and will be the subjectof a future publication. The parameters of the experimental rigare presented in Appendix A.

For data acquisition, an external board with ten analog-to-digital channels of 14 b 1-μs conversion time each is interfacedto the DSP. This board also has four digital-to-analog channelsavailable. Hall-effect transducers are used to measure the inputcurrents, input voltages, and output currents.

For data acquisition of steady-state waveforms, a 500-MHzfour-channel digital oscilloscope and voltage/current probes arepreferred. The data stored in the scope are processed usingMATLAB-based software.

As discussed in Section III, several lookup tables are requiredfor the implementation of the SVM algorithm. For each tetrahe-dron in the output space, the switching states for all the input-current sectors are obtained offline and stored in a two-inputlookup table. One of the inputs to this lookup table is a function


Fig. 9. Experimental system used in this paper.

Fig. 10. Unbalanced operation of the four-leg MC. (a) Phase currents.(b) Neutral current.

of the prism and tetrahedron number. The other input is thecurrent sector at the MC grid side (see Fig. 6). Finally, anotherlookup table is required to transform the switching states intoswitching pulses for the IGBT gate drivers.

In this section, some experimental tests involving high levelof unbalance, modulation of voltage signals of different fre-quencies at the output, modulation of three output voltages withthe same phase, etc., are realized. Although it is recognized thatmany of these operation modes are not realistic and that theymight produce unacceptable MC input-current distortion, theexperimental tests have been carried out to show the capabilityof the proposed SVM algorithm to modulate independent line-to-neutral output voltages.

The unbalanced operation of the four-leg MC is shown inFig. 10. For this test, the output voltages are Van = 70∠0◦

(70 V rms, producing approximately 100 V peak per phase andan rms phase-to-phase voltage of 120 V), Vbn = 70∠120◦, andVcn ≈ 25∠ − 120◦. Fig. 10(a) shows the phase currents ia, ib,and ic. In Fig. 10(b), the neutral current is shown. Because ofunbalanced operation, the neutral current is relatively high. Thephase currents shown in Fig. 10 are well regulated with lowdistortion.

For the test of Fig. 11, the voltages Van and Vcn aremodulated with the same magnitude and phase, i.e., Van =

Fig. 11. Unbalanced operation of the four-leg MC. (a) Phase currents ia andib. (b) Phase current ic. (c) Neutral current.

Fig. 12. Load voltages with the identical phases at the output.

Vcn ≈ 70∠0◦, and the voltage Vbn is modulated to achieve≈ 70∠120◦ at the MC output. All output voltages are 70-Hzsignals. Fig. 11(a) shows the currents ia and ib. As shown in thisfigure, both currents have little harmonic distortion. Fig. 11(b)shows the current ic, which is in phase of and with the samemagnitude as ia. Finally, Fig. 11(c) shows the neutral current.Because two of the currents are in phase, the neutral currenthas a larger magnitude than that of the phase currents. Fig. 12shows the operation of the SVM algorithm, modulating threeoutput voltages Van, Vbn, and Vcn in phase (i.e., Van = 70∠0◦,Vbn, Vcn ≈ 35∠0◦). For this test, the line-to-neutral voltagesare measured in the load (after the output filter). In this case,the MC is equivalent to a single-phase power supply connectedin parallel with all of the three phases of the load and with arelatively high current returning through the neutral. As shownin Fig. 12, the load voltages are also sinusoidal with littleharmonic contents.

As mentioned before, synthesizing voltages of the samephase in a system feeding a 3φ stand-alone load is ratherunrealistic. However, the experimental test of Figs. 11 and12 demonstrates the performance of the SVM algorithm tosynthesize voltages of any phase at the output.

The load voltages for unbalanced operation are shown inFig. 13, for a test similar to that shown in Fig. 10. The volt-ages modulated are Van ≈ 70∠0◦, Vbn ≈ 70∠120◦, and Vcn ≈50∠ − 120◦. In this case, the voltages are modulated with anoutput frequency of ≈30 Hz. The load voltages and currentshave negative-sequence components which produces distortion


Fig. 13. Unbalanced voltages at the load.

Fig. 14. Performance of the (a) phase currents ia and ib, (b) phase current ic,and (c) neutral current.

in the input current. Nevertheless, for this test, the load-voltagewaveforms have an almost perfect sinusoidal shape.

The performance of the SVM algorithm has also been testedconsidering the demand of MC output voltages of differentfrequencies. Fig. 14 shows the line and neutral currents forthis test. The line-to-neutral voltages Van and Vbn are 50-Hzsignals of 55∠0◦ and 55∠120◦, respectively. A signal of thesame amplitude is modulated in Vcn but with a frequency of100 Hz. The currents ia and ib are shown in Fig. 14(a). Thedouble-frequency signal is shown in Fig. 14(b), and the neutralcurrent is shown in Fig. 14(c). As expected, the neutral currenthas a 50-Hz fundamental signal and a 100-Hz harmonic.

It is rather unrealistic to use different frequencies to feed a 3φstand-alone load. However, the results shown in Fig. 14 showthe performance of the proposed modulation algorithm, whichcan be used even to modulate signals of different frequencies atthe MC output.

The performance of the system when balanced voltages aremodulated at the MC output is shown in Figs. 15 and 16. Forthis test, the MC is feeding an unbalanced resistive load withvalues of Ra = 12 Ω, Rb = 18 Ω, and Rc = 18 Ω. Fig. 15shows the steady-state unbalanced phase currents measuredusing the digital scope and high bandwidth current probes.Fig. 15(b) shows the neutral current. Finally, Fig. 16 shows thephase-to-neutral load voltages which have been measured usingdifferential voltage probes. Even when the control system is inopen loop, the load voltage unbalance is low because at thisoperating point, the filter-inductance voltage drop is relativelysmall.

A. Effects of Unbalanced Loads and Output-CurrentHarmonics in MC Input Current

Fig. 17 shows the input current corresponding to theunbalanced operation shown in Fig. 13. As discussed in

Fig. 15. MC currents. (a) Phase currents. (b) Neutral currents.

Fig. 16. Phase-to-neutral load voltages.

Fig. 17. Input current for unbalanced operation of the MC.

Fig. 18. Power spectrum density for unbalanced operation. (a) Output current.(b) Input current.

Section III-B, the negative- and zero-sequence signals at theMC output produces distortion in the input current. This isclearly seen in Fig. 17, where the input current has a subhar-monic plus a relatively high-frequency component.

The spectral components of the input and output currents areshown in Fig. 18. Fig. 18(a) shows the power spectrum of theoutput-current signal. As expected, the load current has a 30-Hzpeak with almost no distortion due to additional frequency com-ponents. Fig. 18(b) shows the power-spectrum density of theinput current. In this figure, there is a fundamental-frequencycomponent of 50 Hz plus a low side frequency of 10 Hz and ahigh side frequency of 110 Hz. These frequencies correspond tothe values of (ωi ± 2ωo) discussed before [see (23)]. The THDcalculated from (24) for this test is about 40%.


Fig. 19. MC input and output current considering a fundamental and a fifthharmonic in the output. (a) Output current. (b) Input current.

Fig. 20. Power-spectrum density corresponding to the currents of Fig. 19.(a) Input current. (b) Output current.

In order to test the effects of injecting a single harmonicto the output current, simulation studies are realized usinga detailed model of the system where discretization effects,delays, input/output filter dynamics, harmonics produced bythe switching frequency, etc., are considered. Simulation isused to verify (19) because of the experimental complicationsassociated with injecting a single harmonic to the MC output.The results obtained are shown in Figs. 19 and 20.

Fig 19(a) shows the 70-Hz fundamental output current,severely distorted by a fifth harmonic with an amplitude of 55%of the fundamental signal. Fig. 19(b) shows the input currentwhich is also distorted.

Fig. 20 shows the spectrum of the input/output current. Theinput current has a fundamental signal of 50 Hz and six addi-tional frequency components. Two of them are produced by thenegative-sequence components at the fundamental frequency,i.e., |fi − 2fo| = 90 Hz, |fi + 2fo| = 190 Hz. Another fourinput-frequency components are produced by the fifth-ordercurrent harmonic in the output. These are |fi − 4fo| = 230 Hz,|fi + 4fo| = 330 Hz, |fi − 6fo| = 370 Hz, and |fi + 6fo| =470 Hz (see Section III-B). The THD for the input current isapproximately 20%.

V. CONCLUSION

This paper has presented a detailed analysis and the imple-mentation methodology of an SVM algorithm suitable for thecontrol of a four-leg MC. Experimental results have demon-strated that the proposed modulation algorithm can be usedto synthesize line-to-neutral output voltages of different am-plitudes, any phase angle, or even the output of differentfrequencies.

The proposed modulation algorithm can be applied to amobile generation system where a stand-alone load with neutralconnection is required to provide an electrical path for thecirculation of zero-sequence current.

The distortion produced at the MC input current, whenunbalanced or nonlinear load is connected to the output, hasbeen analyzed and corroborated by experiments and simulation.

The proposed SVM has been tested for open-loop operationof the proposed generation system. However, based on theexperimental results obtained in this paper, a good performanceis expected for closed-loop operation.

APPENDIX

PARAMETERS OF EXPERIMENTAL RIG

MC Input filter Lf = 0.625 mH, Cf = 2 μF(delta-connected capacitors), Rf = 100 Ω,four-step commutation methodimplemented with 0.7 μs for each step.MC controlled with a 12.5-kHz switchingfrequency.

MC Output filter Output filter implemented with 4-mH induc-tances and 40-uF capacitors.

Output Load The filter capacitors are connected in paral-lel with a resistive load. In the experimentaltest, the load is implemented using switch-able resistor banks of 140 Ω per phase.

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Roberto Cárdenas (S’95–M’97–SM’07) was bornin Punta Arenas, Chile. He received the B.S. degreefrom the University of Magallanes, Punta Arenas,Chile, in 1988 and the M.Sc. and Ph.D. degrees fromthe University of Nottingham, Nottingham, U.K., in1992 and 1996, respectively.

From 1989 to 1991 and 1996 to 2008, he was aLecturer with the University of Magallanes. From1991 to 1996, he was with the Power ElectronicsMachines and Control Group, University of Notting-ham. He is currently with the Electrical Engineering

Department, University of Santiago de Chile, Santiago, Chile. His main inter-ests are in control of electrical machines, variable-speed drives, and renewable-energy systems.

Rubén Peña (S’95–M’97) was born in Coronel,Chile. He received the B.S. degree in electrical en-gineering from the University of Concepcion, Con-cepcion, Chile, in 1984, and the M.Sc. and Ph.D.degrees from the University of Nottingham, Notting-ham, U.K., in 1992 and 1996, respectively.

From 1985 to 2008, he was a Lecturer with theUniversity of Magallanes, Punta Arenas, Chile. Heis currently with the Electrical Engineering Depart-ment, University of Concepción. His main interestsare in control of power electronics converters, ac

drives, and renewable-energy systems.

Patrick Wheeler (M’00) received the degree inelectrical engineering and the Ph.D. degree for workon matrix converters from the University of Bristol,Bristol, U.K., in 1990 and 1994, respectively.

In 1993, he was with the University of Notting-ham and worked as a Research Assistant in the De-partment of Electrical and Electronic Engineering.In 1996, he was appointed Lecturer (subsequentlySenior Lecturer in 2002 and Professor in PowerElectronic Systems in 2007) with the Power Elec-tronics, Machines and Control Group, University of

Nottingham, U.K. His research interests are in variable-speed ac motor drives,particularly, different circuit topologies; power converters for power systemsand semiconductor switch use.

Prof. Wheeler is a member of the Institution of Engineering Technology.

Jon Clare (M’90–SM’04) was born in Bristol,England. He received the B.Sc. and Ph.D. degreesin electrical engineering from The University ofBristol, Bristol, U.K.

From 1984 to 1990, he was a Research Assistantand Lecturer with The University of Bristol, involvedin teaching and research in power electronic systems.Since 1990, he has been with the Power Electronics,Machines and Control Group, University of Notting-ham, Nottingham, U.K. and is currently a Professorin power electronics. His research interests are power

electronic converters and modulation strategies, variable-speed drive systems,and electromagnetic compatibility.

Prof. Clare is a member of the Institution of Engineering Technology.

experimental validation of a space-vector-modulation algorithm for

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