expedition brochure

8/2/2019 Expedition Brochure

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The technology leader for todays most complex PCB systems designs

EXPEDITION ENTERPRISE


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Tightly Integrated Flow

It's Expedition Enterprises tightly

integrated design environment,

industry unique technologies and its

ability to meet the needs of mid-sized

to large electronics companies that

really sets it apart from the competi-

tion. It features a common database

and user interface, with rules that elim-

inate the burden of managing multiple

tools to complete a design. Its electrical

and manufacturing constraint manage-

ment system, and design data and

library management provides support

for local or globally dispersed design

teams to leverage their resources and

reduce design cycle times. Data

integrity is constantly maintained

from concept to manufacturing.

Expedition Enterprise is integrated

with DMS (Data Management

System) and CES (Constraint Editing

System), providing a central infrastruc-

ture for component libraries, design

data versioning and management,

design reuse, where used, entry and

management of high speed and manu-

facturing rules, and

integration withcorporate PLM

systems. Once the

design is complete,

integration with

manufacturing output

tools ensures that the

integrity of the design

is maintained.

Industry-Unique

Technologies

While tight inte-

gration provides a

seamless environment

to support the PCB

systems design team,

Expedition Enterprise

has extended beyond the classical defi-

nition of a PCB design solution and

contains many industry-unique tech-

nologies. These technologies address

the most advanced business needs of an

electronics company enabling the devel-

opment team to deliver a more competi-

tive product to market faster and at re-

duced cost. These unique technologies

fall into three categories: concurrent

(parallel vs. serial) product development

processes; use and analysis of the most

advanced IC and PCB fabrication tech-

nologies; and, collaboration between the

PCB designer and other disciplines in

the product development process.

System Definition

Design EntryDxDesigner provides a complete

solution for design creation, definition

and reuse. It provides everything need-

ed for circuit design and simulation,

component selection and library man-

agement, signal integrity planning,

project management and team-based

design. With DxDesigner, multiple engi-

neers can work on the same design

concurrently without a classical split

and re-join process. Changes made by

one engineer are immediately reflected

in the master database being viewed bythe team so interfaces between the sche-

matic sheets are kept in sync. In addi-

tion to classical schematic symbols,

DxDesigner supports spreadsheet input

of component and interconnect data.

This is especially important to accom-

modate very-high-pin-count packages,

where a schematic symbol would

occupy several pages.Expedition Enterprise delivers industry-unique technologies to product development

DxDesigner provides a complete solutionfor design creation, definition, and reuse

For demonstrations of Expedition Enterprises advanced technology go to:

http://www.mentor.com/products/pcb-system-design/multimedia/


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DxDesigner is also integrated with

product lifecycle management systems,

making design data, PDF schematics,

and BOMs available throughout the

company. It also has a centralized,

Internet-based library so only one

version of the corporate library needs

to be maintained.

ASIC-FPGA-PCB Design

Collaboration

To help with the growing demands

of FPGA, ASIC, and PCB design, I/O

Designer is a fast and efficient solu-

tion for assigning FPGA and ASIC I/O

to device pins in the PCB layout. I/O

Designer integrates the IC and PCB

design flows to provide top-downconcurrent design of the FPGA/IC

packages and the PCB, reducing the

design cycle time and optimizing

system-level performance.

By maintaining a library of parts

from major FPGA vendors, I/O

Designer supplies all of the important

information about each pin of the

selected device. Users then choose to

assign all of the signals to pins on the

device or only those signals deemed

critical to the PCB design. They can

also assign I/O standards for critical

signals. This way, the pinout of single or

multiple FPGAs can be optimized prior

to PCB layout to insure the best system

performance, reducing PCB routing

congestion and design cycle time. Need

to swap pins on the PCB to further

improve the layout? I/O De-signer

knows which pins are swappable and

which are not. I/O Designer also main-

tains the consistency between the FPGA

and PCB flows by acting as a data

management tool, monitoring each flow

and managing any changes that occur.

Pin swaps carried out on the PCB are

picked up by I/O Designer and the

necessary FPGA files updated. It then

generates FPGA place and route

constraints, based on the HDL design

and pin I/O assignment process, and

creates the necessary symbols, sche-

matics and hierarchical associations

based on the "post route" pin data.

Expedition Enterprise is simply the most productive solution available for thecreation of dense, difficult, high technology PCB designs

For ASIC (SoC) packages and sys-

tem-in-package (SiP) designs, I/O De-signer lets package designers balance

IC placements, orientations, and pin

assignments to optimize the design of

the package and the target PCB.

Constraint Definition

Expedition Enterprise understands

and follows an extensive set of high

speed and manufacturing constraints

(rules). These constraints are set either

by engineer direct entry or by inter-

facing from pre-layout high speed

analysis and are obeyed throughout the

layout and verification steps to insure

correct by design results.

The Constraint Editor System

(CES) provides a fully integrated,

constraint-driven design methodology

that reduces design costs and time-to-

market by automating design rules

communication and eliminating unnec-

essary PCB prototypes and re-spins.

And, like DxDesigner, multiple engi-

neers can input and edit constraints

concurrently without a divide and re-

join methodology that can be error

prone and time consuming. Edits are

viewed by the team as they are made, in

real time. CES provides common con-

straint entry for manufacturing and

electrical and physical high-speed

rules. CES has an easy-to-use spread-

sheet-like GUI guided by the design

database with cross probing to the

schematic and layout.

Rules are preserved on net re-

names, connectivity additions/

removals, pin and/or gate swaps,

and stackup changes.

The GUI offers easy differential

pair creation, parallelism rules

entry and pin-pair creation.

Hierarchical constraint entry

enables simple assignment of

complex topologies with filtering

and sorting.




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PCB Layout

Expedition Enterprise is the most

powerful physical-layout solution in

the industry. By combining ease-of-use

with advanced functionality, Expedi-

tion offers designers the leading tech-

nology to create today's most complex

designs. It includes interactive and

customizable multi-pass auto-routing

controls for design challenges, such as

differential pair routing, net tuning,

manufacturing optimization and

HDI/microvia and buildup technology.

The Physical LayoutTechnology Leader in PCB

Design

Expeditions placement and routing

technology represents a revolutionary

step forward for PCB design. The pow-

er of industry-leading auto-routing

technology is combined with interac-

tive editing capabilities to produce asingle, powerful and easy-to-use de-

sign environment. This environment

eliminates the burdens of jumping be-

tween tools to get the job done and

managing differences between the con-

straints on the auto-router and on inter-

active editing. Expedition provides

greater control than ever before, easily

switching between automatic and

manual editing as needed. From simple

tasks, such as defining board areas, to

complex procedures that involve main-

taining high-speed signal conditions,all objectives are accomplished with

the system and the designer working

together in real time. The net result of

Expeditions technology is reduced

design times, increased productivity

and unmatched design quality.

Auto and Interactive Routing

A single, integrated, place-and-route editing environment that

reduces total design time and

increases productivity.

All physical rules and high speed

rules are maintained.

Correct-by-construction design

that produces high-quality results

with clean-up time eliminated.

Shape-based, true 45 routing.

The most advanced auto-routing

technology ever. Stop and start the

auto-router at any time: all results

will be correct-by-construction.

Dynamic clean-up of traces

through the reduction of segments,

prevention of acute angles, and

application of pad entry rules.

Dynamic Area Fills

Expedition Enterprise automatically

clears area fills around traces, vias and

pads as the board is edited. Dynamic

area fills are so fast, it allows users to

keep their area fills turned on while

they are doing all necessary edits.

Moving a via pushes and shoves other

vias, traces and area fills and connec-tivity is automatically maintained.

Rules By Area

The rules-by-area function greatly

improves routing around BGAs and

other fine-pitched parts. Rule areas

represent complete rule sets that are

obeyed by online and batch DRC and

in interactive and automatic routing.

Rule areas may be defined by layer and

can be assigned to any polygon, rect-

angle or circle. Trace widths and clear-

ances automatically change when with-

in the rule area. Designers may also

change via sizes and spans in a rule

area to maximize route completion.

Multi-plow with Variable ViaPatterns

Expedition Enterprise's multi-plow

functionality allows designers to

simultaneously route multiple nets,

Routing and editing differential pairs with Expedition PCB is accomplishedwith speed and ease that will change your view of high-speed design




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including differential pairs, with true

45 routing. It can even handle routingthrough areas of staggered pins. Traces

being routed push and shove the other

vias and traces and automatically clear

area fills as needed. Changes can be

easily made to a variety of selectable

via patterns at the touch of a button,

allowing enhanced flexibility for

routing into dense areas of a design.

High-Speed Layout

Designers are increasingly required

to manage signal quality to achieve

system performance and reduce proto-

type iterations. High-speed design with

Expedition Enterprise is an integrated

part of the design environment.

Net Tuning

While routing interactively, graphic

tuning aids are displayed for guidance.

Nets modified out-of-tune during edits

are automatically re-tuned. The hazards

dialog box dynamically updates as

users edit nets, providing instant feed-

back to their constraints.

Nets can also be tuned automati-

cally within an auto-route pass.Tuned

nets are automatically maintained asthe designs are completed.

Differential Pair Routing

Routing and editing differential pairs

with Expedition is accomplished with speed

and ease that changes the view of high-

speed design. Pair spacing rules can be

established by both layer and net class. If

one trace is edited, the other trace in the pair

automatically moves with it. Adjacent layer

differential pair routing capabilities add

another valuable option for routing critical

signals on a dense PCB.

Dynamic Hazard Review

Design hazards are dynamically

displayed and may be individually selected

and colored for easy identification. When a

hazard is fixed, it is dynamically removed

from the hazard list.

Simultaneous Design

XtremePCB is a revolutionary,

patented, and exciting new technology

that enables multiple PCB designers,

locally or globally dispersed, to simul-

taneously work on a single design

database over a LAN or WAN. Unlike

traditional team design methodologiesthat employ a split-and-join approach to

design collaboration, XtremePCB

requires no physical partitioning and

every designer sees all other client edits

in real time. Because no further training

or complex setup is required, designers

can be brought in at any time and from

anywhere to collaborate on time-critical

projects, dramatically shortening design

cycles. It is ideal for large, complex

designs or when specialists work on

their specialty within a mixed-signal

environment.

Xtreme-Powered Auto-routing

The same Xtreme technology that

enables simultaneous design on the

same database by multiple designers

enables multi-processor auto-routing.

By executing the auto-routing on up to

15 processor clients on a LAN or WAN

network, users can obtain up to a 10x

improvement in elapsed times. For

very large, highly constrained boards,

this can reduce the times from days to

Expedition PCB offers the leading technology for the creation of advanced interconnect designs




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hours. The result is not only a decrease

in design times but the opportunity to

run multiple scenarios of placements

and constraints and pick the the most

cost-effective one.

Bus Routing

Auto-routing is rarely used on

dense, highly bus-structured PCBs, as

manual routing can produce denser,

more manufacturable and aestheticresults. However, manual routing can

be very time consuming and tedious.

Skillful designers or engineers deter-

mine the topology of the buses and

their assigned planes to meet high-

speed constraints. Expedition

Enterprise has unique technology that

combines the skill of the designer and

engineer with the speed of auto-

routing, eliminating the

tedium, instead

focusing on producing

a better design.

Topology Planner

provides an interactive

method of defining the

topologies of buses,

assigning them to

planes and specifying

many specialized rules.

This plan is saved with

the design data and can

be modified. Topology

Router can then be

executed to auto-route

the interconnects

following the plan,

eliminating tedious

trace digitizing. The results mimic

those of a skilled designer, yet signifi-cantly reduce design cycle times and

improve productivity.

Embedded Passive Design

As ICs and FPGAs increase in

speed and density, they require more

passive components (resistors and

capacitors) some may need several

hundred. Implementing these as

embedded components versus discrete

SMDs can significantly reduce board

sizes and improve performance.

Expedition Enterprise provides a

complete solution: trade-off tools

decide which components to imple-

ment in embedded versus discrete

based on board size and cost, passive

material choices, automatic synthesis

driven by material suppliers libraries,

and full manufacturing data generation.

The result is automation of a task that

could take weeks of manual effort.

Advanced Interconnect

Routing

The challenges and solutions of

advanced interconnect are prevalenttoday with BGA, CSP, COB and DCA

packages increasing board density.

With Expedition Enterprise, timing and signal integrity issues can be addressed andcorrected throughout the design process rather than just at the end

Expedition can automatically generate a complexfanout pattern in seconds




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Build-up and microvia structures used

in these board designs further compli-

cate routing. Expedition PCB offers the

leading technology for advanced inter-

connect designs, supporting the defini-

tion of complex via structure rules and

the routing of microvia geometries,including routing under pads. Via

spans between any two layers are

possible. By moving beyond traditional

laminate layer pairing, Expedition

facilitates the design of build-up struc-

tures on laminate to enable escape

patterns from dense, high pin count

devices. Build-up areas typically have

a smaller clearance than the laminate

beneath them. Expedition can establish

delay values and clearances per via

span to address these issues.

High-density BGA FanoutConnecting to todays advanced

packages can be a time consuming task

for the designer. Industry unique tech-

nology in Expedition enables auto-

matic fanout of high pin-count and

density BGAs. Following Mentor

published design guidelines, the user

can define the fanout pattern using

HDI/microvia layers and develop the

pattern in seconds. Then, in the

context of the other PCB components,

define and automatically produce abreakout that connects to the rest of the

PCB. Reducing to minutes what used

to take days of designer time.

RF Circuit Design

With the increase of wireless tech-

nology, more PCB designs mix RF

circuitry with their analog and digital

interconnect. Typically, designing

these boards required two completely

different tools and libraries. Mentors

leading technology enables RF circuit

design in the Expedition Enterprise

environment including schematic entry,synthesis of RF parts using the same

libraries as the RF simulation provid-

ers, manipulation and editing RF cir-

cuitry, and direct interface to RF simu-

lators from suppliers like Agilent and

AWR. The result is a highly productive

process that integrates the design and

design team, eliminates duplication and

HyperLynx enables powerful, easy to use signal integrity, crosstalk, and EMC analysis prior to layout,after component placement, and after a board has been fully routed.

Expedition Enterprise enables the design and verification of digital,analog and RF on the same PCB




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synchronization of libraries, and capi-

talizes on the strengths of Mentors

PCB design and the RF simulator

suppliers technology.

Analysis and Verification

Signal Integrity, Timing

Analysis and EMI

With the Expedition Enterprise flow,

signal integrity and electro-magnetic

interference (EMI) issues can be ad-

dressed and corrected throughout the

design process rather than just at the

end. Driven by constraints in CES this

ensures that designs are correct the first

time, effectively reducing design itera-

tions and facilitating optimum system

performance.HyperLynx provides pre- and

post-layout signal integrity, crosstalk

and EMC analysis for traditional high-

speed interconnects, as well as the

emerging SERDES and DDR2/3 tech-

nologies. HyperLynx's easy-to-learn

analysis environment makes it an ev-

ery-desktop standard for Expedition

Enterprise. Higher-frequency designs

and government regulations place

increasing importance on EMI control.

This normally required a prototype

board, testing in a shielded chamber

and re-design. Now with QuietExpert, the causes of EMI can be

highlighted and eliminated during the

design layout, thus significantly re-

ducing design iterations and saving

valuable time-to-market.

Power Integrity

With todays lower and multiple

voltage ICs, power and ground is no

longer easy to design and analyze.

PCBs can contain as many as 30 power

distribution networks jig-sawed into

the PCB layers. These networks must

be analyzed for DC voltage drop (suffi-

cient power to all IC pins), current

density (too much current through a

narrow part of the network), and AC (is

the power clean). HyperLynx PI

(Power Integrity) provides the engineer

and designer with pre- and post-layout

analysis of complex power distribution

networks to insure proper operation

and high reliability of the PCB.

Thermal Analysis

As products get faster and smaller,

thermal management issues increase.

HyperLynx Thermal, FloTHERM,

and FloEFD provide thermal

analysis capabilities for the PCB as

well as the PCB(s) in the full product

(enclosure, fans, heat sinks, etc.).

Using these capabilities, the PCB

designer can perform analysis on the

PCB to determine good placement of

the components. The mechanical

designer of the enclosure can insert the

PCB(s) into the complete product and

analyze it to see if the heat will be

dissipated properly. The result is a

design that has higher reliability and

can be manufactured without multiple

prototypes or re-spins.

Mixed Signal Verification

HyperLynx Analog verifies

analog and mixed analog/digital

designs at the system or board level. It

is tightly integrated into DxDesigner

and combines ease-of-use with

powerful simulation, stimuli prepara-

tion, and complex circuit analysis and

The Expedition Enterprise flow addresses the needs of the mid-sized to large enterprise electronics company




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verification. ModelSim is

the world's most popular and

widely used VHDL and

mixed-VHDL/Verilog simu-

lator and the fastest-growing

Verilog simulator.

ModelSim products are

unique, using technology

such as Optimized Direct

Compile for faster compile

times and simulation

performance, Single Kernel

Simulation (SKS) and

Tcl/Tk for greater openness

and faster debugging. These

exclusive ModelSim, inno-vations result in leading

compi-ler/simulator

performance, complete

freedom to mix VHDL and

Verilog and the unmatched

customization.

Multi-disciplinedCollaboration

Developing an electronic product

requires more than the design of the

PCB. The mechanical enclosure must

be designed. Procurement, test and

manufacturing must be involved

throughout the design process to insure

that the product can reach volume

production in time to hit the market

window. Expedition Enterprise

provides the ability for these disci-

plines to collaborate during the product

development process.

ECAD-MCAD Collaboration

In the past, communication between

the electrical designer and the mechan-

ical designer was performed via paper

or through mass data transfers.Expedition Enterprise provides3D

viewing capability for the PCB

designer to insert the PCB into the

enclosure and identify gross errors

such as interference of components

with the enclosure. But true collabora-

tion goes beyond 3D viewing.

Expedition also provides the ability for

bi-directional, electronic communica-

tion of incremental change proposals.

Using this ECAD-MCAD collabora-

tion, either discipline can propose a

change in their domain and communi-

cate that proposal to the other. The

proposal can then be analyzed,

rejected, accepted, or counter-

proposed. This digital processcontinues until both disciplines are

satisfied at which point the change is

reflected in both databases.

PCB Designer Supply Chain

Collaboration

Late changes in the PCB design can

negatively affect the ability for

procurement, manufacturing and test to

deliver volume production targets.

Expedition Enterprise enables the PCB

designer to propose a change and elec-

tronically communicate that proposal

to the rest of the supply chain organi-

zations. visECAD enables these

organizations to view the proposed

change and communicate back to the

designer through mark-ups and

redlines whether this change is accept-

able. This negotiation process

continues until an acceptable solution

is reached.

vSure DFM Verification

Concurrent DFM verification with

the vSure product is the most efficient

way to incorporate manufacturability

into your PCB design process. Identify

the opportunity for fabrication, assem-

bly and test improvement during de-

sign, and avoid manufacturing-initiated

Engineering Changes. You can even

automate the intervals for DFM verifi-

cation and review results in a timely

manner so the design flow is stream-

lined and efficient. If an error is identi-

fied, a single click takes you to the

location on your PCB design so that

you can remedy the issue.

Comprehensive Analysis

Your DFM process is only as good

as the verification tools you use. To-

days miniaturized, high-layer count

designs cannot be reliably reviewed by

manual means. Mentors vSure DFM

verification software analyzes your

PCB design with more than:

275 Fabrication checks

250 Assembly checks

100 Advanced Substrate checks

40 Microvia checks

30 Panel checks

visECAD enables the PCB designer to electronically communicate proposed schematic and layoutchanges to the rest of the supply chain for their viewing and comment


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In addition, vSure also

provides the ability to check

your Netlist against the

design data to assure there

are no fatal errors within this

critical step. vSure validates

that your BOM matches the

design, and that all compo-

nents in your Approved

Vendors List (AVL) are an

acceptable physical match.

Design Center

Customization

Every design center andevery technology type have

their own unique require-

ments with respect to manu-

facturability.

From data attribution to

manufacturing rules values,

you need to be able to run

DFM at the highest level of

automation. vSure uses a

Design Center concept to

allow customization of the

DFM process flow, attribute

mapping, component classification,and, the set-up and management of

manufacturing rules files. Using a

hierarchical approach, you create a

master rules model using constants

and variables that drive derivative

rules models. This greatly reduces the

support requirements for your DFM

environment.

vSure even provides a default

master set compliant with the IPC-

7351 standard.

Understand the

Manufacturing RiskvSure not only identifies where

your PCB design is in hard violation

of your suppliers manufacturing

capbilities, it also shows where yield

or field failure issues may occur by

using color severity indicators of red,

yellow, and green. vSure further cate-

gorizes and prioritizes the issues so

that you may easily resolve the most

critical first. The weight assigned toeach check is user-definable, enabling

you to apply criteria to how the

results are prioritized. After all, your

technology and suppliers processes

are likely different than another

companys processes.

FabLink XE for Fabrication

Manufacturing and fabrication

have always been an integral part of

PCB design. Previously, designers

used multiple applications to create

schematics, layouts and prepare for

manufacturing. To make the processeasier, Expedition Enterprise integrates

the FabLink XE environment

for manufacturing data creation,

generation and verification. FabLink

XE enables designers to control their

fabrication data at either the board

or panel level, ensuring design and

manufacturing data integrity.

FabLink XE provides a standalone

panel creation and editing environmentfor creating manufacturing data at

the panel level, using a panel design

database. It also provides additional

board level functionality, including

detailed data views, searchable

PDF output, copper balancing, data

outputs and Gerber In/Drill In

capabilities.

Automation

Automation provides customization

and extensibility within the design and

layout products, allowing the addition

of custom functionality, the automationof repetitive tasks, and the ability to

tailor the flow to customer-specific

use-cases and optimize the flow for

specialized processes. The use of a

wide range of industry-standard

languages (VBscript, Jscript, TCL,

Java, VB6, C++, C#, VB.NET...) mini-

mizes the start-up time for company



DFM issues are summarized and ranked by severity based on userweighting


11/12

programmers and facilitates script

reuse. The result of automation is toreduce errors, increase productivity,

increase the performance, quality, and

reliability of the design, decrease the

cost of the design, and decrease time to

market (and time to profit).

Intellectual PropertyManagmenent

DMS brings the electronic design

process to the supply chain, and brings

the supply chain to the designer's

desktop. It ensures complete data

consistency, accuracy and availability

throughout the design enterprise. Plus,

DMS consolidates multiple data

systems, enabling collaboration and life

cycle management across multiple team

members, disciplines and sites.

It does this by integrating design data

management with component in-

formation so that corporate component

procurement policies (approved parts,

preferred vendors) are easily available

on the desktop. This helps designers

make optimum component choices and

manage parts lists during the design

process so they can be released as accu-

rate BOM's meeting corporate policies

for cost, reliability and regulatory

compliance. At the end of the project,

DMS manages the process so that

accurate product documentation canbe released to enterprise manufac-

turing, PLM and ERP systems, and

supply chain management systems.

Design Reuse

The Design Reuse module creates

and stores reusable blocks of circuitry,

including schematic, as well as PCB

placement and routing data, in a

central library. These blocks can then

be placed and modified in the same

design or multiple designs now and

in the future. Design reuse automates

this process and manages the design

data to ensure error-free databases

and reduce the overall PCB design

cycle time by not having to re-design

the same circuit. Layout data can

also be easily cut/pasted within a

design and into other designs,

enabling informal reuse of sections

of a design.

Variant Management

Variant Manager manages the

creation of multiple product configura-

tions from a single design database.

Variant Manager's single-point ECO

management minimizes errors,

reduces costs, improves design quality

and enhances production efficiency.

Support, Education and

ConsultingMentor Graphics offers a full range

of services to drive your productivity

and success with the Expedition

Enterprise flow tools. Customer

Support offers award-winning tech-

nical assistance, innovative electronic

support and high-quality product

enhancements. Education Services

offers classroom and online training to

help you assimilate new tools and tech-

nologies into your design environment.

Finally, Mentor Consulting is always

ready to provide focused expertise in

tough design areas.

Hardware Requirements

Dual core, 2 GHz or faster

Memory: 2 GB RAM

OS Requirements

Windows XP Professional

Windows 7

HPUX

Sun OS

RedHat Linux




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Systems Design Division

Mentor Graphics Corporation

1811 Pike RoadLongmont, CO 80501720.494.1000 Main

800.547.3000 Saleswww.mentor.com/pcb

Corporate Headquarters

Mentor Graphics Corporation

8005 SW Boeckman RoadWilsonville, OR 97070-7777

503.685.7000 Main800.547.3000 Saleswww.mentor.com

Copyright 2010 Mentor Graphics Corporation. The marks for the Mentor products and processes mentioned in thisdocument are trademarks or registered trademarks of Mentor Graphics Corporation. All other trademarks mentioned inthis document are trademarks or registered trademarks of their respective owners.

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