exception and interrupt handling -...
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Exception and Interrupt HandlingException and Interrupt Handling
Hsiao-Lung Chan, Ph.D.Dept Electrical Engineering
Chang Gung University, [email protected]
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• 31 general-purpose 32-bit register• 6 status register
r0r1r2r3r4r5r6r7r8r9
r10r11r12r13r14
r15(PC)
CPSR
System & User
Programstatus registers
General registers& Program counter
r0r1r2r3r4r5r6r7
R8_fiqR9_fiqR10_fiqR11_fiqR12_fiqR13_fiqR14_fiqr15(PC)
CPSR
FIQ
SPSR_fiq
Supervisorr0r1r2r3r4r5r6r7r8r9
r10r11r12
R13_svcR14_svcr15(PC)
CPSRSPSR_svc
Abortr0r1r2r3r4r5r6r7r8r9
r10r11r12
R13_abtR14_abtr15(PC)
CPSRSPSR_abt
IRQr0r1r2r3r4r5r6r7r8r9
r10r11r12
R13_irqR14_irqr15(PC)
CPSRSPSR_irq
Undefinedr0r1r2r3r4r5r6r7r8r9
r10r11r12
R13_undR14_undr15(PC)
CPSRSPSR_und
Banked registers :available only processor is in a particular mode
ARM registers and operation modes
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HL Chan, EE, CGUException 3
User (usr) mode Program execution state
Fast interrupt (fiq) mode Data transfer or channel process
Interrupt (irq) mode General-purpose interrupt handling
Supervised (svc) mode Protected mode for operating system
Abort (abt) mode Entered after a data or instruction prefetch Abort
System (sys) mode Privileged user mode of operating system
Undefined (und) mode Entered when a undefined instruction is executed
Operation modes of ARM
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HL Chan, EE, CGUException 4
N Z C V ․․․ I F T M4 M3 M2 M1 M0
OverflowCarry or borrow or extendZeroNegative or less than
Mode bitsState bit (1:Thumb, 0:ARM)FIQ disableIRQ disable
Control bitsCondition code flag Reserved
827 031
Note: N, V : Relate to 2’s complement arithmetic
Program status register
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HL Chan, EE, CGUException 5
Undefined instruction or software interruptLowest
Prefetch Abort
IRQ
FIQ
Data Abort
ResetHighest
ExceptionPriority
• Exception arise whenever the normal flow of a program has to be halted temporally.
ARM exception priority order
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HL Chan, EE, CGUException 6
Exception handling
Exception Any condition that needs to halt normal sequential execution
of instructions ARM core is reset Instruction fetch or memory access fails Undefined instruction is encountered Software interrupt instruction is executed External interrupt has been raised
Exception handling The method of processing these exceptions Exception handler
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HL Chan, EE, CGUException 7
ARM processor exceptions and modes
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HL Chan, EE, CGUException 8
ARM processor exceptions and modes (cont.)
When an exception causes a mode change, the core automatically Save CPSR to SPSR of the exception mode Save PC to LR of the exception mode Sets CPSR to the execution mode Sets PC to the address of the exception handler
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HL Chan, EE, CGUException 9
Vector tables
A table of addresses that the ARM core branches to when an exception is raised
These addressed contain branch instructions B <address> LDR pc, [pc, #offset]
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HL Chan, EE, CGUException 10
Vector tables (cont.)
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HL Chan, EE, CGUException 11
Interrupts
Assigning interrupts IRQ and FIQ exceptions Interrupt latency Interrupt stack design
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HL Chan, EE, CGUException 12
Assigning interrupts
Interrupt controller Multiple external interrupts to one if the two ARM interrupt
requests Standard design practice
SWI are reserved to call privileged operating system routines IRQ are assigned for general-purpose interrupts
A periodic timer
FIQ are reserved for a single interrupt source that require a fast response time Direct memory access to move blocks of memory FIQ has a higher priority and shorter interrupt latency than IRQ
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HL Chan, EE, CGUException 13
IRQ and FIQ exceptions
nzcvqjift_usr
nzcvqjIft_irqspsr_irq=cpsr
r14_irq=pcpc=0x18
Softwarehandler
IRQ
Return to user mode code
nzcvqjift_usr
nzcvqjIFt_irqspsr_fiq=cpsr
r14_fiq=pcpc=0x1c
Softwarehandler
FIQ
Return to user mode code
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HL Chan, EE, CGUException 14
Enabling and disabling IRQ and FIQ exceptions
Enabling an interrupt
Disabling an interrupt
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HL Chan, EE, CGUException 15
Interrupt latency
Interval of time from an external interrupt request signal being raised to the first fetch of an instruction of interrupt service routine (ISR)
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HL Chan, EE, CGUException 16
Program status register instructions
MRS{<Cond>} Rd, <CPSR|SPSR> Copy program status register to general-purpose register
MSR{<Cond>} <CPSR|SPSR>_<fields>, Rm Copy general-purpose register to program status register
MRS{<Cond>} <CPSR|SPSR>_<fields>, #immediateCopy program status register to general-purpose register
<Pre-condition> CPSR = nzcvqIFt_SVC
MRS r1, cpsrBIC r1, r1, #0x80MSR cpsr_c, r1
<Post-condition> CPSR=nzcvqiFt_SVC
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HL Chan, EE, CGUException 17
Examples: program state register transfer
MRS r0, cpsr ; read CPSRBIC r0, r0, #f0000000 ; clear N,Z,C,V flagsMSR cpsr, r0 ; update the flag in CPSR
MRS r0,cpsr ; read CPSRBIC r0, r0, #0x1F ; clear mode bitsORR r0, r0, #0x13 ; set the mode bits to supervised modeMSR cpsr, r0 ; update the control bits in CPSR
MRS r0,cpsr ; read CPSRORR r0, r0, #0x80 ; set interrupt disable bitMSR cpsr, r0 ; update the control bits in CPSR
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HL Chan, EE, CGUException 18
Software interrupt (SWI) instruction
Use SWI instruction to enter supervisor mode for calling operating system routines
SWI{<Cond>} SWI_number lr_svc = address of next instruction following SWI SPSR_svc = CPSR pc = 0x08 CPSR mode = SVC CPSR I = 1 (mask IRQ interrupts)
After SWI routine, return to the calling program byMOV pc, lr_svc
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HL Chan, EE, CGUException 19
SWI example
SWI call with SWI number 0x123456, used by ARM toolkits as a debugging SWI
<Pre-condition> CPSR = nzcVqift_USERpc = 0x00008000lr = 0x003fffffr0 = 0x12 ; used for parameter passing
0x00008000 SWI 0x123456
<Post-condition>CPSR = nzcVqIft_SVCSPSR_svc = nzcVqift_USERpc = 0x00000008lr = 0x00008004r0 = 0x12
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HL Chan, EE, CGUException 20
Interrupt stack design
Each operation system has its own requirement for stack design
Stack pointers are initialized after reset
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HL Chan, EE, CGUException 21
Reset handler
Initialize system Setting up memory and caches Setting up stack pointers for all processor modes
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HL Chan, EE, CGUException 22
Example to set up stacks
USR_Stack EQU 0x20000IRQ_Stack EQU 0x8000SVC_Stack EQU IRQ_Stack-128…Usr32md EQU 0x10FIQ32md EQU 0x11IRQ32md EQU 0x12SVC32md EQU 0x13Abt32md EQU 0x17Und32md EQU 0x1bSys32md EQU 0x1fNoInt EQU 0xc0 ; Disable interrupts
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HL Chan, EE, CGUException 23
Example to set up stacks (cont.)
; Set up supervisor mode stackLDR r13, SVC_NewStack ; set r13_svc
; Set up IRQ stack LDR r2, #NoInt | IRQ32mdMSR cpsr_c, r2 ; make r13_irq visibleLDR r13, IRQ_NewStack ; set r13_irq
; Set user mode stack LDR r2, #Sys32mdMSR cpsr_c, r2 ; make r13_sys visibleLDR r13, USR_NewStack ; set r13_usr…
SVC_NewStack DCD SVC_StackIRQ_NewStack DCD IRQ_StackUSR_NewStack DCD USR_Stack
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HL Chan, EE, CGUException 25
Exercise
Write a ARM program to set stacks for all exception modes
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HL Chan, EE, CGUException 26
Non-nested interrupt handler
Disable interruptspc = vector table entryspsr_{mode} = cpsr
Restorecontext
Save nonbank registers
Return to task
Interrupt
Savecontext
Interrupthandler
ServiceInterruptroutine
Enable interruptspc = lr-4cpsr = spsr_{mode}
Identify interrupt source and execute appropriate ISR
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HL Chan, EE, CGUException 27
Non-nested interrupt handler (cont.)
interrupt_handlerSUB r14, r14, #4 ; adjust lrSTMFD sp!,{r0-r3,r12,r14} ; save contextLDR r0,=IRQStatus ; interrupt status addressLDR r0,[r0] ; get interrupt statusTST r0,#0x0080BNE timer_isr ; branch timer ISRTST r0,#0x0001BNE button_isr ; call button ISRLDMFD sp!,{r0-r3,r12,pc}^ ; restore context and return
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HL Chan, EE, CGUException 28
Load-Store Instructions (Multiple-Register Transfer)
{!} : Store the modified address to Rn (W=1){^} : S=1, determine whether R15 can be in <registers> list
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R1
R5
0x1000
R6
R8
LDMIA r8!, {r1, r5, r6}
R8
R1
0x1000
R6
R5
R8
LDMIB r8!, {r1, r5, r6}
R8
R6
R5
R1
0x1000R8
LDMDA r8!, {r1, r5, r6}
R8
R6
R5
R1
0x1000R8
LDMDB r8!, {r1, r5, r6}
R8
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HL Chan, EE, CGUException 30
Load-Store Multiple Pairs when base update used
STMIA <- - -> LDMDB STMIB <- - -> LDMDA STMDA <- - -> LDMIB STMDB <- - -> LDMIA
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HL Chan, EE, CGUException 31
Load-Store Multiple Instructions Example
<Pre-condition> r0 = 0x00009000r1 = 0x00000009r2 = 0x00000008r3 = 0x00000007
STMIB r0! , {r1-r3}
MOV r1, #1MOV r2, #2MOV r3, #3
<2nd_Condition> r0 = 0x0000900cr1 = 0x00000001r2 = 0x00000002r3 = 0x00000003
<Post-condition> r0 = 0x00009000r1 = 0x00000009r2 = 0x00000008r3 = 0x00000007
LDMA r0! , {r1-r3}
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HL Chan, EE, CGUException 32
Load-Store Multiple Instruction for Block Memory Copy
; r9 points to start of source data; r10 points to start of destination data; r11 points to end of the source
loop; load 32 bytes from source and update r9 pointerLDMIA r9!, {r0-r7}; store 32 bytes to destination and update r10 pointerSTMIA r10!, {r0-r7}; have reached the end?CMP r9, r11BNE loop
Destination
Sourece
Copyr9
r11
r10
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HL Chan, EE, CGUException 33
Pipeline Stalls: Data Stall(ARM multi-cycle LDMIA instruction)
fetchLDMIA r0, {r2, r3}
SUB r2, r3, r6
CMP r2,#3
decode
fetch
time
ex ld r3
decode
fetch
ex sub
decodeex cmp
ex ld r2
stall
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HL Chan, EE, CGUException 34
Nested interrupt
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SAMSUNGS3C2410X
ARM920TProcessor Core
LCDCONT.
LCD DMA
USB Host CONT.
ExtMaster
BUS CONT.
Interrupt Cont.
PowerManagement
Memory CONT.
Bridge DMA
Clock Generator(MPLL) UART 0,1
USB Device
MMC
WatchdogTimer
BUS CONT.
SPI
I2C
I2S
GPIO
RTC
ADC
Timer/PWM
AHB
APB
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HL Chan, EE, CGUException 36
Interrupt controller in S3C2410
Receives request from 56 interrupt sources When receiving multiple interrupt requests, interrupt
controller requests FIQ or IRQ interrupt of ARM920T core after arbitration procedure
Arbitration procedure Depends on hardware priority logic Result is written to the interrupt pending register, which
helps users notify which interrupt is generated
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HL Chan, EE, CGUException 37
Interrupt sources in S3C2410
Internal peripherals DMA controller UART IIC others
External interrupts
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Interrupt operation in S3C2410
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Interrupt priority logic
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Interrupt mode
F-bit and I-bit of program status register (PSR) If F-bit is set to 1, CPU does not accept fast interrupt request
(FIQ) from interrupt controller If I-bit is set to 1, CPU does not accept interrupt request
(IRQ) from interrupt controller Interrupt mode set by interrupt mode register (INTMOD)
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Interrupt mask register (INTMSK)
An interrupt is disabled if corresponding mask bit of INTMSK is set to 1. Otherwise, the interrupt will be serviced normally.
If corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set
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Interrupt pending registers
S3C2410 has two interrupt pending resisters Source pending register (SRCPND) Interrupt pending register (INTPND)
When interrupt sources request interrupt service Corresponding bits of SRCPND are set to 1 Only one bit of INTPND is set to 1 after arbitration procedure.
If interrupts are masked, corresponding bits of SRCPND are set to 1. This does not cause the bit of INTPND changed.
Service routine must clear pending condition by writing a 1 to corresponding bit in SRCPND first and then clear pending condition in INTPND
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Interrupt pending registers
Source pending register
Interrupt pending register
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Reference
A.N. Sloss, D. Symes, C. Wright, “ARM System Developer’s Guide”, Elsevier Inc., 2004.
D.Seal, ARM Architecture Reference Manual, 2nd Edition, Addison-Wesley, 2001.
S3C2410 User Mannual, Samsung Semiconductor