example on circuits

8/7/2019 example on circuits

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Computer Science 141

omput ng Har wareFall 2008

Harvard University

Instructor: Prof. David Brooks

Computer Science 141David Brooks


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Counters

sequential logic circuits that proceed through: a well-defined sequence of states

types up-counter vs. down-counter . . . .

simplest possible finite-state machines (FSMs)

single input (typically clock saying count!) outputs simply the current state



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design example: 3-bit binary up-counter

Step 1: describe operation (graphically and in tabular form)



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3-bit binary up-counter example (continued)

Step 2: choose a flip-flop type



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Step 3: remap next state into required FF inputs

Q Q + T0 0 0

Excitation Table

0 1 11 0 11 1 0



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Step 4: use K-maps to derive simplified logic eqns for FF inputs

S2 S1 S2 S1

0 0 0 0

0 1 1 0

S0 00 01 11 10

0

1

0 0 0 0

1 1 1 1

S0 00 01 11 10

0

1

Ts2 = S1 S0 Ts1 = S0

S2 S1

1 1 1 1

1 1 1 1

S0 00 01 11 10

0

1

Ts0 = 1



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Step 5: wire it up!

clrclrclr

reset

QQQcnt

S0 S1 S2

use async ronous reset or n t a zat on



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another example: 3-bit Johnson counter

Step 1: describe operation



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Step 2: choose a flip-flop type



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Step 3: remap next state into required J-K FF inputs



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another example: 3-bit Johnson counter Step 4: use K-maps to derive simplified logic eqns for FF inputs

Step 5: Wire it up!



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another example: 3-bit Johnson counter Step 5: wire it up



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Asynchronous-ity in counters

state transitions only through synchronous inputs as nchronous in uts for ower-on reset/ reset onl !

example no-no: ripple counter

T QT QT QT Q

S0 S1 S2 S3



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Cascaded Counters Say you have a pre-designed 4-bit counter

How do ou build a 8-bit or bi er counter?

Solution: 4-bit counters have RCO ( ripple carry out ) pinwhereRCO = S3 S2 S1 S0Feed this to enable pin of next significant 4-bit counter.



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General Finite State Machine (FSM) design

FSM = sequential logic circuit which can be implemented in afixed number of states

basically extend design technique learned for counters



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Mapping Input History Parity Checkers: Simplest example of general class of

error detecting codes

How to build a odd/even parity checker? Odd parity: asserts output when a serial input stream contains an

odd number of 1s

Even parity: asserts output when its seen an even number of 1s Clearly, output depends on entire input history!



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Building the FSM

0 PresentState

Input NextState

Output

11

Even (0) 0 Even (0) 0

Even (0) 1 Odd (1) 0

Odd 1 0 Odd 1 1

Odd Odd (1) 1 Even (0) 1

State Diagram

Next State = Present State XOR InputOutput = Present State

D Q

Q

clr



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Basic design approach1. understand the problem

make assumptions to complete design specification Identif inputs and outputs draw a block diagram of FSM enumerate possible inputs sequences and system states

2. obtain abstract representation of FSM raw s a e rans on agram or alternative state machine representation

3. perform state minimization (new step)

encode states build state transition table

5. choose FF type

remap next state into required FF inputs6. implement

simplify next state and output logic equations



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Design example: simple vending machine

block diagram:

N

Vending

MachineFSMSensor Gum

ReleaseD

reset

dispense

clk

N, N, N N, N, D

, D, N D, D


output: asserted on y after reaching 15 or greater


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Step 2: obtain abstract representation of FSM state dia ram based on tree of in ut o tions



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Step 2: obtain abstract representation of FSM state dia ram based on tree of in ut o tions

S0[ ]

S1 S2

N D

[ ] [ ]

S3[ ]

S4[open]

S5[open]

S6[open]

N DD N

N D

S7[open]

S8[open]

open = dispense



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minimized state diagram (intuitive approach to Step 3)0

reset

[ ]

5

N

D

D10

[ ]

N

15[open]

,

algorithm state machines like flowcharts w/ rigorous timing hardware description languages (Verilog, etc)



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Step 4: perform state assignment

4 states requires 2 bits

5 0110 10



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Design example: simple vending machineStep 5: choose FF type

Choose J-K FF remap next state into FF inputs



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Step 6: implement simplify logic equations for FF inputs and circuit output



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Gate Implementation


example on circuits

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