EVE: A CAD Tool ProvidingPlacement and Pipelining Assistance for

High-Speed FPGA Circuit Designs

William Chow

Supervisor : Prof. Jonathan Rose

M.A.Sc. Thesis

Edward S. Rogers Sr. Department of

Electrical and Computer Engineering,

University of Toronto

September 28, 2001

2

Motivation

• Context: High-speed circuit designs, how?

• Push-button design flow– Automatic: design -> circuit– 0.18 m, struggling to achieve 150MHz+

• Von Herzen’s paper [VonH97]– 250MHz FPGA, 0.6m in 1997!

• Useful “Event Horizon” concept (later)

• EVE: EVent horizon Editor

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Event Horizon

src CLB

250MHz budget = 4ns

0.8

0.80.4

1.2 1.2

0.8 1.20.4

Max clock skew = 0.1ns, clock-to-output delay = 1.3ns,LUT delay+FF setup time = 1.5ns

• Choose placement of target CLB

• Set target speed

• Know chip spec

• Calculate Event Horizon

Max routing delay = 4.0-0.1-1.3-1.5 = 1.1ns

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Context

• Von Herzen’s approach– Set speed goal

– Build by construction using Event Horizon concept

• EVE– Start with placed and routed design– Increase speed by manual editing small

designs

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Goals1. Construct a manual editor focussing

on packing/placement/pipelining level of the Event Horizon design methodology to allow a designer to increase speed easier

2. Gain insights to better placement and routing techniques through extensive manual circuit editing experience

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Design Objectives of EVE

1. Target real FPGA architecture : Xilinx Virtex-E

2. Give full low-level control3. Give instant performance feedback4. Assist pipelining

(3&4) not supported by Xilinx Tools

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EVE: two operating modes

1. Timing Exact Microscopic Placement (TEMP) Mode

– Change placement and packing of circuit components

– Instant timing feedback

– Invoke horizon : suggest good placement positions

2. Pipelining Mode– Maintain correct functionality during flip-flop insertion

and flip-flop motion

– Instant feedback of new circuit speed estimation

– Flip-flop placement optimizations

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Horizon

• From “Event Horizon”• Gradient of colours• Horizon Radius

– Where to evaluate– Limit computation

• Display timing– -ve : speed improves– +ve : speed degrades

+0.2

+0.2

-0.2

-0.2

src LUT

+0.0

+0.4

+0.4

+0.2

+0.2

Radius = 1

Definition: Display effect of critical path delay should a circuit element moved to indicated positions

(mode 1)

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Timing Exact Microscopic Placement(TEMP) Mode

Radius = 3 • Placement• Packing• Timing

Feedback• Horizon• More info• Better

answer

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Implementation of TEMP mode

• Instant feedback– Internal Timing Analysis

• Accurate timing– Database of real delays

– Compression by 100x (100MB->1MB)

• High Interactivity– Integrate tightly with Xilinx backend (FPGA

Editor) for quick incremental P&R,timing

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Partial Incremental Timing Analysis

• Full Timing Analysis (TA)

• O(n) Forward &Backward Sweep as in [HSC83]

• Faster: Only rebuild modified portion of circuit

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Delay Database

• Delay Extraction

– RC Models: Elmore, Penfield Rubinstein

– Not possible in EVE

• Extracting Logic Delays

• Extracting Routing Delays

• Delay Database Compression

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Routing Delay Compression

Intersect

Dr(r)

Dc(c)

Column of source pin

Row of source pin

Pin-to-pin delay (ns) Symmetric!Symmetric!“BRAMs”

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Backend Integration

• Existing tools are insufficient– Lack ease for incremental flow

– Full CAD flow is slow

• Solution: Interface with Xilinx manual editor - FPGA Editor– Full set of commands for circuit editing

– Use named pipes on WIN NT platform

floorplan

P&R

TA

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src CLB

Event Horizon: Pipelining

• Pipeline to extend Event Horizon

src CLB

Original Event Horizon

dstCLB

dstCLB

Pipelining flip-flop

Extended Event Horizon

(Mode 2)

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Pipelining Mode

(Leave for

demo)

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Baseline Circuits Generation

(Push-button flow baseline)• Input is VHDL or Verilog• Synthesize using Synplify Pro 6.2, freq = s• Place and route using Xilinx backend tools• Obtain frequency from reports• repeat step (2) to (4), increasing s 10% until

done• Using frequency in (5), do Multi-Pass

Place&Route (MPPR) for 10 runs, pick the best design [+10%]

(skip!)

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Vision 142 241 4.92 203.3 224.8 10.6%Batcher 252 455 3.06 326.8 380.1 16.3%Banyan 165 311 2.94 340.7 395.3 16.0%Trap 187 470 2.45 408.3 460.4 12.8%Miim 122 112 6.16 162.4 168.5 3.8%Div 87 255 4.65 215.1 229.6 6.7%Dotproduct 243 178 6.74 148.4 173.3 16.8%Crossproduct 129 126 4.54 220.1 261.4 18.8%Average 166 269 4.43 238.7 268.8 12.7%

New Freq (MHz)

% Change

Circuit # LUTs

# FFs Period (ns)

Freq (MHz)

Results: Using TEMP mode only

+12.7%!+12.7%!(Note: Area is unchanged!)

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Example : Vision

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Vision: Before

203.3MHz

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Vision: After

224.8MHz

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Results: Using both TEMP and pipelining modes

(Note: FF inserted once only)

Circuit # LUTs # FFs # FFs added

Freq (MHz)

New Freq (MHz)

% Change

Vision 142 241 224.8 N/A : critical path in loopBatcher 252 455 380.1 N/A : already well pipelinedBanyan 165 311 395.3 N/A : already well pipelinedTrap 187 470 460.4 N/A : already well pipelinedMiim 122 112 168.5 N/A : critical path in loopDiv 87 255 66 229.6 237.7 3.5%Dotproduct 243 178 173.3 N/A : due to tool instabilityCrossproduct 129 126 261.4 N/A : due to tool instabilityMult 39 23 38 123.1 175.1 42.2%

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Observations (1)

Pack and unpack slices during Pack and unpack slices during placement and routing is goodplacement and routing is good

Slice Slice

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Observations (2)

Focusing on improving k-most Focusing on improving k-most critical path is effectivecritical path is effective

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Observations (3)Partial re-routing of timing-critical Partial re-routing of timing-critical

regions is effectiveregions is effective

Reroute!

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Observations (4)

CAD Tool should show high speed CAD Tool should show high speed routing resources on the chip, help routing resources on the chip, help

user make better decisionsuser make better decisions

Fast Routing!

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Live DemoLive Demo

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Conclusion• Proposed a high-speed manual circuit design

methodology • Created a manual editor

– Targets real designs: Xilinx Virtex-E– Focus on pipelining, placement, packing– Full low-level control– Instant exact timing feedback

• Results: speed increased up to +19%, avg +12.7% for 8 ccts

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Future Work

1. Synthesis in Event Horizon framework

2. Extend EVE to support Virtex-II, etc.

3. Automate manual optimizations in EVE

4. Make pipelining mode more useful