evb-lan9500a-mii user's guide

2014 Microchip Technology Inc. DS50002242A

EVB-LAN9500A-MIIEvaluation Board

User’s Guide

DS50002242A-page 2 2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may besuperseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NOREPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use ofMicrochip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic-itly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

A more complete list of registered trademarks and common law trademarks owned by Standard Microsystems Corporation (“SMSC”) is available at: www.smsc.com. The absence of a trademark (name, logo, etc.) from the list does not constitute a waiver of any intellectual property rights that SMSC has established in any of its trademarks.

All other trademarks mentioned herein are property of their respective companies.

© 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 9781620778364

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

EVB-LAN9500A-MII Evaluation Board User’s Guide

Object of Declaration: EVB-LAN9500A-MII Evaluation Board

2014 Microchip Technology Inc. DS50002242A-page 3


NOTES:


EVB-LAN9500A-MIIEVALUATION BOARD

USER’S GUIDE

Table of Contents

Preface ........................................................................................................................... 7Introduction............................................................................................................ 7

Document Layout .................................................................................................. 7

Conventions Used in this Guide ............................................................................ 8

The Microchip Web Site ........................................................................................ 9

Development Systems Customer Change Notification Service ............................ 9

Customer Support ................................................................................................. 9

Document Revision History ................................................................................. 10

Chapter 1. Overview1.1 Introduction ................................................................................................... 11

Chapter 2. Getting Started2.1 Board Details ................................................................................................ 13

2.1.1 Configuration ............................................................................................. 132.1.2 Mechanicals .............................................................................................. 18

Appendix A. EVB-LAN9500A-MII Evaluation BoardA.1 Introduction .................................................................................................. 19

Appendix B. EVB-LAN9500A-MII Evaluation Board SchematicsB.1 Introduction .................................................................................................. 21

Appendix C. Bill of Materials (BOM)C.1 Introduction .................................................................................................. 25

Appendix D. ReferencesD.1 Introduction .................................................................................................. 29

Worldwide Sales and Service .................................................................................... 31



NOTES:



USER’S GUIDE

Preface

INTRODUCTION

This chapter contains general information that will be useful to know before using the EVB-LAN9500A-MII Evaluation Board. Items discussed in this chapter include:

• Document Layout

• Conventions Used in this Guide

• The Microchip Web Site

• Development Systems Customer Change Notification Service

• Customer Support

• Document Revision History

DOCUMENT LAYOUT

This document describes how to use the EVB-LAN9500A-MII Evaluation Board as a high-performance and low-cost USB/Ethernet connectivity solution.

The manual layout is as follows:

• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9500A-MII Evaluation Board.

• Chapter 2. “Getting Started” – Includes information about the EVB-LAN9500A-MII Evaluation Board.

• Appendix A. “EVB-LAN9500A-MII Evaluation Board” – This appendix shows the EVB-LAN9500A-MII Evaluation Board.

• Appendix B. “EVB-LAN9500A-MII Evaluation Board Schematics” – This appendix shows the EVB-LAN9500A-MII Evaluation Board schematics.

• Appendix C. “Bill of Materials (BOM)” – This appendix includes the EVB-LAN9500A-MII Evaluation Board Bill of Materials.

• Appendix D. “References” – This appendix shows the reference documents related to the EVB-LAN9500A-MII Evaluation Board.

NOTICE TO CUSTOMERS

All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available.

Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is “DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document.

For the most up-to-date information on development tools, see the MPLAB® IDE online help. Select the Help menu, and then Topics to open a list of available online help files.



CONVENTIONS USED IN THIS GUIDE

This manual uses the following documentation conventions:

DOCUMENTATION CONVENTIONS

Description Represents Examples

Arial font:

Italic characters Referenced books MPLAB® IDE User’s Guide

Emphasized text ...is the only compiler...

Initial caps A window the Output window

A dialog the Settings dialog

A menu selection select Enable Programmer

Quotes A field name in a window or dialog

“Save project before build”

Underlined, italic text with right angle bracket

A menu path File>Save

Bold characters A dialog button Click OK

A tab Click the Power tab

N‘Rnnnn A number in verilog format, where N is the total number of digits, R is the radix and n is a digit.

4‘b0010, 2‘hF1

Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>

Courier New font:

Plain Courier New Sample source code #define START

Filenames autoexec.bat

File paths c:\mcc18\h

Keywords _asm, _endasm, static

Command-line options -Opa+, -Opa-

Bit values 0, 1

Constants 0xFF, ‘A’

Italic Courier New A variable argument file.o, where file can be any valid filename

Square brackets [ ] Optional arguments mcc18 [options] file [options]

Curly brackets and pipe character: { | }

Choice of mutually exclusive arguments; an OR selection

errorlevel {0|1}

Ellipses... Replaces repeated text var_name [, var_name...]

Represents code supplied by user

void main (void){ ...}


Preface

THE MICROCHIP WEB SITE

Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.

To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.

The Development Systems product group categories are:• Compilers – The latest information on Microchip C compilers, assemblers, linkers

and other language tools. These include all MPLAB C compilers; all MPLAB assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK object linker); and all MPLAB librarians (including MPLIB object librarian).

• Emulators – The latest information on Microchip in-circuit emulators.This includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.

• In-Circuit Debuggers – The latest information on the Microchip in-circuit debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug express.

• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows Integrated Development Environment for development systems tools. This list is focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and MPLAB SIM simulator, as well as general editing and debugging features.

• Programmers – The latest information on Microchip programmers. These include production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included are nonproduction development programmers such as PICSTART Plus and PIC-kit 2 and 3.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support


www.microchip.com

http://www.microchip.com


Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

DOCUMENT REVISION HISTORY

Revision A (January 2014)

• Initial release of this document.


http://www.microchip.com/support

http://www.microchip.com/support


USER’S GUIDE

Chapter 1. Overview

1.1 INTRODUCTION

The LAN9500A is a high-performance, small form factor solution for USB to 10/100 Ethernet port bridging. With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators, USB to Ethernet adapters, PC docking stations, and test instrumentation, the LAN9500A is targeted as a high-performance and low-cost USB/Ethernet connectivity solution.

The LAN9500A contains an integrated 10/100 Ethernet PHY, USB PHY, Hi-Speed USB 2.0 device controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with a total of 30 KB of internal packet buffering. The LAN9500A complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol and USB 2.0 specification, enabling compatibility with industry standard Fast Ethernet and USB 2.0 applications.

The EVB-LAN9500A-MII is an evaluation board that utilizes the LAN9500A to provide a fully-functional, USB to Ethernet interface. The EVB-LAN9500A-MII provides fully-integrated Ethernet and USB ports via the on-board RJ45 and USB Type B connectors. The EVB-LAN9500A-MII can be configured for bus- or self-powered operation and supports internal and external PHY modes. An external PHY may be connected via the on-board 40-pin female MII connector. The on-board 256x8 EEPROM is used to load the EVB-LAN9500A-MII’s USB configuration parameters and MAC address.

LAN9500A software drivers are available for Windows XP, Windows Vista, Mac OS X, Linux, and Windows CE. Additional manufacturing and diagnostic tools are available for debugging and external EEPROM configuration. For complete details, refer to the “LAN9500A Software User Manual”.

A simplified block diagram of the EVB-LAN9500A-MII can be seen in Figure 1-1.



FIGURE 1-1: EVB-LAN9500A-MII BLOCK DIAGRAM

MicrochipLAN9500A

EVB-LAN9500A-MII

256 x 8µWire

EEPROMEthernet

10/100 Ethernet

Magnetics & RJ45USB Type B

ConnectorUSB

GPIO Header

1 x 10

2 x 20

JTAG Header40-Pin MII Connector

(Female)

External PHY



USER’S GUIDE

Chapter 2. Getting Started

2.1 BOARD DETAILS

This section includes the following EVB-LAN9500A-MII board details:

• Configuration

• Mechanicals

2.1.1 Configuration

The following sub-sections describe the various board features including jumpers, LEDs, test points, and system connections. A top view of the EVB-LAN9500A-MII is shown in Figure 2-1.

FIGURE 2-1: EVB-LAN9500A-MII TOP VIEW

+5V Power Input

MII Testpoints

Ethernet Port(integrated LEDs)

USB Type B Connector

JTAG Header

JP7GPIO/Strap

Header

JP1JP3 – JP6

Female MII Connector

Reset Switch

JP2JP8

LAN9500A

Note: The EVB-LAN9500A-MII includes a 2A fuse (F1) to protect from overcurrent conditions. If this fuse becomes damaged, it can be replaced with a 2A Littlefuse-154002.



2.1.1.1 JUMPERS

The following table details the jumper definitions and default settings for the EVB-LAN9500A-MII.

Jumper settings may be changed as needed. However, any deviation from the default settings should be approached with care and knowledge of the schematics and data sheet. An incorrect jumper setting may disable the board.

1: JP5 and JP7 must be identically populated.

2: This jumper should only be removed if the customer supplies +3.3V from an external source.

3: JP4 must be populated when using a bus-powered external PHY that is powered through the MII connector. To avoid contention, JP4 must be unpopulated when using a self-powered external PHY through the MII con-nector.

Note: A dashed line in the Settings column indicates an installed jumper. All jumper settings are shown in their default state (self-powered, internal Ethernet PHY operation).

TABLE 2-1: JUMPERS

JUMPER DESCRIPTION SETTINGS

JP2 JTAG Header Connect 1 2 IN: Connects shared JTAG signals to JTAG header J2OUT: Disconnects shared JTAG signals from JTAG header J2

JP3 Ethernet PHY Select1 2 Selects external Ethernet PHY

2---3 Selects internal LAN9500A Ethernet PHY

JP4 MII Connector +5V SelectNote 3

1 2 IN: On-board +5V supplied to MII connector pins 1, 20, 21, and 40OUT: On-board +5V not supplied to MII connector pins 1, 20, 21, and 40

JP5+5V Power Supply SelectNote 1

1 2 Populate when bus-powered. Connects VSS_USB from the upstream host USB connector to the on-board +3.3V voltage regulator input.

2---3 Populate when self-powered. Connects +5V from the external power supply to the on-board +3.3V voltage regulator input.

JP6 On-board +3.3V Regulator Output ConnectNote 2

1---2 IN: Connects output of on-board +3.3V regulator to the +3.3V power planeOUT: Disconnects output of on-board +3.3V regulator from the +3.3V power plane

JP7VBUS_DET Input SelectNote 1

1 2 Populate when bus-powered. Connects +3.3V voltage regulator output to VBUS_DET.

2---3 Populate when self-powered. Connects VCC_USB from the upstream host USB connector to VBUS_DET through a voltage divider and transient filter.

JP8 EEPROM Disable1---2 IN: EEPROM Enabled

OUT: EEPROM Disabled


2.1.1.2 LEDS

Table 2-2 describes the EVB-LAN9500A-MII LEDs.

2.1.1.3 TEST POINTS

Table 2-3 describes the EVB-LAN9500A-MII test points.

Note 1: Pin 1 of this test point can be used by the customer to provide an external +3.3V supply. This option may be useful in cases where the customer desires operation in self-powered permanently attached mode. If used in this fashion, JP6 must be removed.

2.1.1.4 SYSTEM CONNECTIONS

Table 2-4 describes the EVB-LAN9500A-MII system connections.

TABLE 2-2: LEDs

REFERENCE COLOR INDICATION

LED1 Green Ethernet Full Duplex

LED2 Green +5V External Power Active

Note: This LED will not illuminate when in bus-powered mode.

T1 Green Ethernet Link/ActivitySolid: Link establishedBlinking: Link activityOFF: No link

T1 Yellow Ethernet SpeedON: 100BASE-TXOFF: 10BASE-T

TABLE 2-3: TEST POINTS

TEST POINT DESCRIPTION CONNECTION

TP2 TDO/nPHY_RST Pin of LAN9500A (Unpopulated)

TDO/nPHY_RST

TP3 nRESET Pin of LAN9500A (Unpopulated) nRESET

TP4 +3.3V Test Point (Unpopulated)Note 1 PIN 1: +3.3VPIN 2: GND

TP5 GND Black Test Point (Populated) GND

TP6 GND Black Test Point (Populated) GND

TABLE 2-4: SYSTEM CONNECTIONS

PLUG/HEADER DESCRIPTION PART

P1 USB Type B Right Angle Connector AMP 292304-1

P2 +5V Power Supply Barrel Connector CUI PJ-102AH

T1 RJ45 Ethernet Port with Integrated Magnetics and LEDs

Pulse J0011D01B

JP1 1x2 nPHY_INT Header

PIN 1: nPHY_INTPIN 2: Ground

Note: In internal PHY mode, nPHY_INT is a configurable output. In external PHY mode, nPHY_INT is an input.

Adam Tech PH1-2-U-A



Table 2-5 describes the EVB-LAN9500A-MII JTAG header pinouts.

Table 2-6 describes the EVB-LAN9500A-MII GPIO/STRAP header pinouts.

J2 2x10 JTAG Header for IEEE 1149.1 Compliant TAP Controller

Note: Refer to Table 2-5 for a full pin list.

Adam Tech PH2-20-U-A

J3 1x10 GPIO/Strap Header

Note: Refer to Table 2-6 to for a full pin list.


J4 40-pin Female MII Connector

Note: This connector follows the standardized MII pinout. Refer to the EVB-LAN9500A-MII schematic for additional information.

AMP 5787170-4

J5 1x2 External Reset Header

PIN 1: GNDPIN 2: Reset Generator Input

Adam Tech PH1-2-U-A

J6 2x11 MII Test Point Header

Note: Refer to Table 2-7 to for a full pin list.


TABLE 2-5: 2x10 JTAG HEADER PINOUT

HEADER PIN DESCRIPTION HEADER PIN DESCRIPTION

1 nTRST 11 No Connect

2 Ground 12 Ground

3 TDO 13 No Connect

4 Ground 14 Ground

5 TDI 15 No Connect

6 Ground 16 Ground

7 TMS 17 No Connect

8 Ground 18 Ground

9 TCK 19 No Connect

10 Ground 20 +3.3V

TABLE 2-6: 1x10 GPIO/STRAP HEADER PINOUT


1 +3.3V 6 TXD0/GPIO4/EEP_DISABLE

2 COL/GPIO0 7 TXD1/GPIO5/RMT_WKP

3 MDIO/GPIO1 8 TXD2/GPIO6/PORT_SWAP

4 MDC/GPIO2 9 TXD3/GPIO7/EEP_SIZE

5 CRS/GPIO3 10 Ground

TABLE 2-4: SYSTEM CONNECTIONS (CONTINUED)

PLUG/HEADER DESCRIPTION PART


Table 2-7 describes the EVB-LAN9500A-MII MII header pinouts.

2.1.1.5 SWITCHES

Table 2-8 describes the EVB-LAN9500A-MII switch.

TABLE 2-7: 2x11 MII HEADER PINOUT


1 Ground 12 TXER (Ground)

2 Ground 13 TXCLK

3 MDIO/GPIO1 14 TXEN

4 MDC/GPIO2 15 TXD0/GPIO4/EEP_DISABLE

5 TDI/RXD3 16 TXD1/GPIO5/RMT_WKP

6 TMS/RXD2 17 TXD2/GPIO6/PORT_SWAP

7 TCK/RXD1 18 TXD3/GPIO7/EEP_SIZE

8 nTRST/RXD0 19 COL/GPIO0

9 RXDV 20 CRS/GPIO3

10 RXCLK 21 Ground

11 RXER 22 Ground

TABLE 2-8: SWITCHES

SWITCH DESCRIPTION FUNCTION

S1 Reset Switch When pressed, triggers a board reset



2.1.2 Mechanicals

Figure 2-2 details the EVB-LAN9500A-MII mechanical dimensions.

FIGURE 2-2: EVB-LAN9500A-MII MECHANICALS

2.07

5

3.100

Ø0.125 Ø0.125

Ø0.125 Ø0.125

TOP VIEW

0.225

0.2

0.225

0.675

0.225 0.675 0.2 0.225



USER’S GUIDE

Appendix A. EVB-LAN9500A-MII Evaluation Board

A.1 INTRODUCTION

This appendix shows the EVB-LAN9500A-MII Evaluation Board.

FIGURE A-1: EVB-LAN9500A-MII EVALUATION BOARD



NOTES:



USER’S GUIDE

Appendix B. EVB-LAN9500A-MII Evaluation Board Schematics

B.1 INTRODUCTION

This appendix shows the EVB-LAN9500A-MII Evaluation Board schematics.


EV

B-L

AN

9500A-M

II Evalu

ation

Bo

ard U

ser’s G

uid

e

DS

50002242A

-page 22

2014 M

icrochip Technolo

gy Inc.

1

1

D

C

B

A

Ethernet

USB Connector

LINK/ACT

SPD

FDX

ion

tors near. resistor

R7hm 1%

hm

ing external JTAG.

nLNKA_LED/GPIO9

nFDX_LED/GPIO8

USBDPUSBDM

nSPD_LED/GPIO10

GND_USB

VCC_USB

+3.3V

+3.3V

+3.3V

+3.3V

Title

Size Assembly No. Schematic Rev

Date: Sheet of

Engineer PCB Rev

6516 1.0

LAN9500 / LAN9500A, USB / Ethernet / JTAG

C2 3Tuesday, January 28, 2014

JM E

Title


Date: Sheet of

Engineer PCB Rev

6516 1.0



JM E

Title


Date: Sheet of

Engineer PCB Rev

6516 1.0



JM E

C24 4700pF50V 10%

R61 332

1%1 2

C221.0uF16V10%

12

FB30.5amp 120 Ohm 100MHz

1 2P1

USB Type-B Right AngleAMP_292304-1

SHLD15

SHLD26

VCC1

D+3

GND4

D-2

R20332

1/10W1%

12

R271.00K1/10W1%DNP

12

XMIT

RCV

75

75 75

1000 pF 2 kV

RJ45

1

4 & 5

2

3

7 & 8

6

75

GRN

YEL

T1

Pulse - J0011D01BNL

RD+3

RXCT5

RD-6

TD+1

TXCT4

TD-2

CHS GND8

GN

D13

GN

D14

MTG

15

MTG

16

NC7

C10

A9

C11

A12

R28 10M1/10W5%

C230.1uF

16V10%

12

R2510.0K1/10W1%DNP

12

R29 0

LED1

LED_0805

21

KW

R44 332

1/10W 1%

1 2

FIGURE B-1: EVB-LAN9500A-MII EVALUATION BOARD SCHEMATIC 15

5

4

4

3

3

2

2

D

C

B

A

JTAG HEADER

NOTE:In an EMI constrained environment, populate these capacitors. These components must be placed close to the transformer.

LAN9500 / LAN9500A

JTAGBypass and Filtering

12.4K Ohm 1%LAN9500A *

R14LAN9500

12.0K Ohm 1%

Device

* Default Configuration

Device R22

LAN9500A ** Default Configuration

DNPLAN9500 1M Ohm 1%

* Default Configurat

NOTE:Place 49.9 Ohm resisLAN9500 / LAN9500APlace 0 Ohm / 10 Ohmnear transformers.

GPIO Header + Straps Straps

Notes:JP3(1-2)=External Ehternet PHY.JP3(2-3)=Internal Ehternet PHY.

DeviceLAN9500 10 OLAN9500A * 0 O

NOTE:Populate JP2 and R27 when us

TXD2/GPIO6/PORT_SWAP

EEDO/AUTOMDIX_ENTXD3/GPIO7/EEP_SIZE

TMS

nTRST/RXD0

TXD0/GPIO4/EEP_DISABLE

TCK

TXD3/GPIO7/EEP_SIZE

nTRSTnTRST

TXD1/GPIO5/RMT_WKPCRS/GPIO3

MDIO/GPIO1

TCK

PHY_SEL

TMS

TXD1/GPIO5/RMT_WKP

EECLK/PWR_SEL

TDO/nPHY_RST

TDI


COL/GPIO0

TMS/RXD2

TCK/RXD1TDI

MDC/GPIO2

TDI/RXD3


EEDI

VBUS_DET

nRESET

TDO/nPHY_RST

RXCLK

TXP

nPHY_INT

EEDO/AUTOMDIX_EN

USBDP

RXN

RXER

TCK/RXD1 nFDX_LED/GPIO8

TXD3/GPIO7/EEP_SIZE

TXD1/GPIO5/RMT_WKP

PHY_SEL

nSPD_LED/GPIO10

COL/GPIO0

MDIO/GPIO1

nLNKA_LED/GPIO9

RXP

EECS

nTRST/RXD0

TMS/RXD2

EECLK/PWR_SEL

TXENRXDV


TXCLK

MDC/GPIO2

USBDM

CRS/GPIO3

TXN


TDI/RXD3

+3.3V

+3.3V

+3.3V

+3.3V

VDDCORE

+3.3V

VDDCORE

+3.3V

VDDUSBPLL+3.3V

+3.3V

VDDCORE

+3.3V

+3.3V

VDD33A

VDDUSBPLL

+3.3V

VDDPLL

+3.3V

VDD33A

+3.3V

VDD33A

VDDPLL

MDIO/GPIO1

VBUS_DET

MDC/GPIO2

TDI/RXD3

TXD3/GPIO7/EEP_SIZE

EECLK/PWR_SEL

RXDV


RXER

TXD1/GPIO5/RMT_WKP

EECS

TXEN

CRS/GPIO3


EEDO/AUTOMDIX_EN

nTRST/RXD0

EEDI

nRESET

TCK/RXD1

TXCLKCOL/GPIO0

TMS/RXD2

RXCLK

R36 10.0KDNP1 2

C160.1uF16V10%

12

J3

1x10

1

32

45678910

R22 1.00M

DNP

12

C315pF50V5%DNP

12

C170.1uF16V10%

12

R649.91/10W1%

12

C280.1uF16V10%

12

FB40.5amp 120 Ohm 100MHz

1 2

FB2

0.5amp 120 Ohm 100MHz

1 2

C150.1uF16V10%

12

C6 4700pF

50V 10%

1 2

R70

R46

10.0K

DNP1 2

JP3

1x3

12

3

C210.1uF16V10%

12

R21 10M

1/10W5%

1 2

U1

LAN9500/LAN9500A

EECS30

EEDO/AUTOMDIX_EN31

EECLK/PWR_SEL29

TXN2TXP3

RXN5RXP6

VD

D33

IO51

EXRES8

nPHY_INT1

TXEN43

RXER44

RXCLK41

RXDV42

MDIO/GPIO123 MDC/GPIO222

CRS/GPIO345

COL/GPIO046

TXD3/GPIO7/EEP_SIZE53

TXD2/GPIO6/PORT_SWAP54

TXD1/GPIO5/RMT_WKP55

TXD0/GPIO4/EEP_DISABLE56

TXCLK47

TEST213

PHY_SEL34

VBUS_DET20

VD

D33

A4

VD

D33

A/N

C7

nRESET24

TCK/RXD138

TMS/RXD239

nTRST/RXD036

TDO/nPHY_RST37

TDI/RXD340

VD

DP

LL10

VD

D33

A9

VD

D33

IO25

VD

DC

OR

E50

VD

D33

IO48

VD

D33

IO52

VD

DC

OR

E21

EEDI32

EP

57XO

19

XI18

VD

DU

SB

PLL

17

USBRBIAS16

VD

D33

A15

USBDP12

USBDM11

nSPD_LED/GPIO1028nLNKA_LED/GPIO927nFDX_LED/GPIO826

NC14

TEST333

VD

D33

IO35

TEST149

C1030pF50V5%

12

R349.91/10W1%

12

C140.1uF16V10%

12

J2

2x10

13 4

2

5 67 89

111012

13 141615

17 1819 20

R14 12.0K

1%1 2

U2SN74CBTLV3125PW

VC

C14

GN

D7

1B31OE

1

1A2

2OE4

2A5

3OE10

3A9

4OE13

4A12

2B6

3B8

4B11

R40 10.0KDNP1 2

C270.1uF16V10%

12

JP21x2

21

R35

10.0K

DNP1 2

R233.32K1/10W1%

12

R34 10.0KDNP1 2R32 10.0KDNP1 2

C110.1uF16V10%

12

C415pF50V5%DNP

12

C200.1uF16V10%

12

R449.91/10W1%

12

R33

10.0K

DNP1 2

C190.1uF16V10%

12

C930pF50V5%

12

R39 10.0KDNP1 2

R260DNP

C120.1uF16V10%

12

R42

10.0K

DNP1 2

TP21

R15 12.0K

1%1 2

FB1

0.5amp 120 Ohm 100MHz

1 2

R38 10.0KDNP1 2

C180.1uF16V10%

12

R30 10.0KDNP1 2

C260.1uF16V10%

12

R549.91/10W1%

12

R2410.01/101%

12

Y125.000MHz

HC49US12

3

C10.022uF50V10%0805

12

C515pF50V5%DNP

12

R45

10.0K

DNP1 2

JP1

1x2

21

C250.1uF16V10%

12

C215pF50V5%DNP

12

R41

10.0K

DNP1 2

R37 10.0KDNP1 2

C130.1uF16V10%

12

EV

B-L

AN

9500A-M

II Evalu

ation

Bo

ard U

ser’s Gu

ide

2014

Microchip T

echnology Inc.D

S5

0002242A-p

age 23

FIG1

1

D

C

B

A

OM

WER

TE:6 BYTE EEPROM.

Ground Test Points

nRESET

K

+3.3V

EEDI

nRESET

Title


Date: Sheet of

Engineer PCB Rev

6516 1.0

Power / MII / uWire EEPROM / Misc.


JM E

Title


Date: Sheet of

Engineer PCB Rev

6516 1.0



JM E

Title


Date: Sheet of

Engineer PCB Rev

6516 1.0



JM E

2

TP6Test Point - BlackGND

1

MTG4

Plated Hole .250 Dia.

NC1

ED2ED_0805

MTG2

Plated Hole .250 Dia.

NC1

R6210.0K1/10W1%

12

C290.1uF16V10%

12

TP5Test Point - BlackGND

1

TP31

URE B-2: EVB-LAN9500A-MII EVALUATION BOARD SCHEMATIC 25

5

4

4

3

3

2

2

D

C

B

A

Microwire Serial EEPR

MII Test Points

PO

Reset

Mounting Holes

PowerVBUS_DET

NOTE:JP5 and JP7 should be populated identically.

NO25

MII

TMS/RXD2

MDIO/GPIO1MDC/GPIO2

TCK/RXD1

CRS/GPIO3

TXEN


COL/GPIO0

TXER

TXEN

RXDV

TDI/RXD3

RXER

TXD3/GPIO7/EEP_SIZE

TXD0/GPIO4/EEP_DISABLETXD1/GPIO5/RMT_WKP

nTRST/RXD0

RXCLK

TXCLK

MDIO/GPIO1

RXCLK

COL/GPIO0

nTRST/RXD0

MDIO/GPIO1

TXD1/GPIO5/RMT_WKP

TDI/RXD3

RXERTXCLK

RXDV

TXEN


MDC/GPIO2

CRS/GPIO3


TXER

TXD3/GPIO7/EEP_SIZE

TCK/RXD1TMS/RXD2

+5V

+3.3V

+3.3V

+3.3V

+3.3V

+5V_BRICK

VCC_USB +3.3V

+5V +5V_BRIC

VCC_USB+3.3V

nTRST/RXD0TCK/RXD1TMS/RXD2TDI/RXD3

TXEN

RXDV

CRS/GPIO3COL/GPIO0

MDIO/GPIO1MDC/GPIO2

TXD3/GPIO7/EEP_SIZETXD2/GPIO6/PORT_SWAPTXD1/GPIO5/RMT_WKPTXD0/GPIO4/EEP_DISABLE

RXER

EEDO/AUTOMDIX_EN

EECLK/PWR_SEL

VBUS_DET

RXCLK

TXCLK

EECS

R54

0

C310.1uF16V10%

12

JP7

1x31

32

TP4DNP2

1R6041.2K1/10W1%

12

C350.1uF16V10%

12

R55

0

MTG1

NUM3 Plated Hole .250 Dia.

NC1

C360.1uF16V10%

12

R56

0

R5110.0K1/10W1%

12

+

-

C3222uF16V10%

12

S1

R58 0

J4

MII

Con

nect

or R

A Fe

mal

e

12345678910111213141516171819202122232425262728293031323334353637383940

Cha

ssis

141

Cha

ssis

242

JP8

21

U4MIC6315SOT-143_BIG1VTH = 2.93 VTreset = 20 mS

GN

D1

VCC4

RESET

MR3

Pin 5 is TABVR1

LP38693MP-3.3SOT223_5500mA

VIN4

VOUT3

NC2 VEN1

GN

D5

JP5

1x3

1

32

C341.0uF16V10%

12

C331.0uF16V10%

12

R52

1001/10W1%

1 2

NUM3

MTG3

NUM3 Plated Hole .250 Dia.

NC1

C300.1uF16V10%

12

J6

HEADER_2x11

13 4

2

5 67 89 10

121113 1415 1617 1819 2021 22

LL

21

JP4

1x2

21

R576041/10W1%

12

NUM3

JP621F1

2A/125V

1 2

J5DNP

21

P2

POWER SUPPLY

+V1

GND2

GND INT3

R53

0

R5049.9K1/10W1%

12

R4910.0K1/10W1%DNP

12

R6310.0K1/10W1%

12

R4810.0K1/10W1%

12

U3

93AA56A-OTSOT23-6

DI3

DO1

GND2

VC

C6

CS5

CLK4

R59

20.5K1/10W1%

1 2


NOTES:



USER’S GUIDE

Appendix C. Bill of Materials (BOM)

C.1 INTRODUCTION

This appendix includes the EVB-LAN9500A-MII Evaluation Board Bill of Materials.



FIGURE C-1: EVB-LAN9500A-MII EVALUATION BOARD BILL OF MATERIALS (1 OF 2)

LAN9500A Customer Evaluation Board REVISED: Nov. 11, 2013 ASSY 6516 PCB Revision E

Schematic Revision: 1.0

Bill Of Materials Page 1 of 2 Item Qty Reference Part PCB Footprint Manufacturer Part # .

1 1 C1 0.022uF 50V 0805 Kemet C0805C223K5RACTU 2 DNP 4 C2,C3,C4,C5 15pF 50V 0603 Kemet C0603C150J5GAC 3 2 C6,C24 4700pF 50V 0603 Kemet C0603C472K5RACTU 4 2 C9,C10 30pF 50V 0603 Murata GRM1885C1H300JA01D 5 21 C11,C12,C13,C14,C15,C16, 0.1uF 16V 0603 Kemet C0603C104K4RACTU C17,C18,C19,C20,C21,C23, C25,C26,C27,C28,C29,C30, C31,C35,C36 6 3 C22,C33,C34 1.0uF 16V 0603 Kemet C0603C105K4PACTU 7 1 C32 22uF 16V SMD_B AVX TAJB226K016RNJ 8 4 FB1,FB2,FB3,FB4 0.5A/120 Ohm/100MHz 0603 TDK MMZ1608S121A 9 1 F1 2A/125V FUSE_SMF Littelfuse 0154002.DR 10 5 JP1,JP2,JP4,JP6,JP8 1x2 HEADER_1x2_0.100 Adam Tech PH1-2-U-A 11 3 JP3,JP5,JP7 1x3 HEADER_1x3_0.100 Adam Tech PH1-03-U-A 12 1 J2 2x10 HEADER_2x10_0.100 Adam Tech PH2-20-U-A 13 1 J3 1x10 HEADER_1x10_0.100 Adam Tech PH1-10-U-A 14 1 J4 MII Connector RA Female AMP_787170_4 AMP - 5787170-4 15 DNP 2 TP4,J5 1x2 HEADER_1x2_0.100 Adam Tech PH1-2-U-A 16 1 J6 2x11 HEADER_1x11_0.100 Adam Tech PH2-22-U-A 17 2 LED1,LED2 LED - Green LED_0805 Lite-On LTST-C170GKT 18 4 MTG1,MTG2,MTG3,MTG4 NUM3 Plated Hole .250 Dia. MTG_NUM3_GND_P250 19 1 P1 USB Type-B Right Angle THRU-HOLE CUSTOM AMP 292304-1 20 1 P2 POWER SUPPLY PJ_102AH CUI PJ-102AH 21 4 R3,R4,R5,R6 49.9 0603 Rohm MCR03EZPFX49R9 22 7 R7,R29,R53,R54,R55,R56, 0 0603 Rohm MCR03EZPJ000 R58 23 2 R14,R15 12.0K 0603 Yageo RC0603JR-0712KL 24 3 R20,R44,R61 332 0603 Rohm MCR03EZPFX3320 25 2 R21,R28 10M 0603 Rohm MCR03EZPJ106 26 DNP 1 R22 1.00M 0603 Rohm MCR03EZPFX1004 27 1 R23 3.32K 0603 Rohm MCR03EZPFX3321 28 5 R24,R48,R51,R62,R63 10.0K 0603 Rohm MCR03EZPFX1002 29 DNP 16 R25,R30,R32,R33,R34,R35, 10.0K 0603 Rohm MCR03EZPFX1002 R36,R37,R38,R39,R40,R41, R42,R45,R46,R49 30 DNP 1 R26 0 0603 Rohm MCR03EZPJ000 31 DNP 1 R27 1.00K 0603 Rohm MCR03EZPFX1001 32 1 R50 49.9K 0603 Rohm MCR03EZPFX4992 33 1 R52 100 0603 Rohm MCR03EZPFX1000 34 1 R57 604 0603 Rohm MCR03EZPFX6040 35 1 R59 20.5K 0603 Rohm MCR03EZPFX2052 36 1 R60 41.2K 0603 Rohm MCR03EZPFX4122 37 1 S1 MOM_PB SW_MOM_PB Digi-Key P8052SCT-ND



FIGURE C-2: EVB-LAN9500A-MII EVALUATION BOARD BILL OF MATERIALS (2 OF 2)

LAN9500A Customer Evaluation Board REVISED: Nov. 11, 2013 ASSY 6516 PCB Revision E

Schematic Revision: 1.0

Bill Of Materials Page 2 of 2 Item Qty Reference Part PCB Footprint Manufacturer Part # .

38 DNP 2 TP2,TP3 Test Point -1x1 HEADER_1X1 Adam Tech PH1-01-U-A 39 2 TP5,TP6 Test Point - Black GND TP_THRU_93x63P Keystone 5006 40 1 T1 J0011D01BNL PULSE_RJ45_J0026 Pulse J0011D01BNL 41 1 U1 LAN9500A QFN56 Microchip LAN9500A-ABZJ 42 1 U2 SN74CBTLV3125PW TSSOP14 SN74CBTLV3125PW 43 1 U3 93AA56A-OT SOT23-6 Microchip 93AA56AT-I/OT 44 1 U4 MIC6315 SOT-143_BIG1 Micrel MIC6315-26D2UY TR 45 1 VR1 LP38693MP-3.3 SOT223_5 National LP38693MP-3.3/NOPB 46 1 Y1 25.000MHz HC49US Suntsu Freq. SCS20D-25.000MHZ



NOTES:



USER’S GUIDE

Appendix D. References

D.1 INTRODUCTION

Concepts and material available in the following documents may be helpful when using EVB-LAN9500A-MII.

• LAN9500A Data Sheet

• AN 8.13 Suggested Magnetics

• EVB-LAN9500A-MII Evaluation Board Schematic

• LAN9500A Software User Manual



NOTES:



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