etin55 – lab seminar - lth · 2017-11-09 · etin55 – lab seminar ... • assignment 1 – fft,...

Lund University - Department for Electrical and Information Technology

ETIN55 – Lab Seminar

Pietro Andreani

Department for Electrical and Information TechnologyLund University


Presentation Objectives

• Administrative issues – organization and requirements

• Lab report requirements

• Schedule

• Introduction to A/D and D/A conversion

• Introduction to the assignments

• Assignment 1 – FFT, sampling and quantization

• Assignment 2 – analog modeling and simulation with Verilog-A

• Assignment 3 – mixed-signal design and simulation with AMS


Organisation and Requirements

• MATLAB and Cadence files are available for download atwww.eit.lth.se/course/etin55

• The course homepage contains Errata and FAQ page

• The assignments are well suited for self studies, but 3 supervisedlab sessions are scheduled, where you can get help

• The total workload is about 60 hours, so it is inevitable that youwork outside the scheduled lab hours. Start working now!

• Undergraduate students work in groups of 2 students

• Ph.D. students work alone

• One clearly written report per group is required

• Cheaters will be prosecuted by the law

• Lab report hard deadline: Friday 15/12 ⇒⇒⇒⇒⇒⇒⇒⇒⇒


Lab Report Requirements

• Include answers to homework exercises

• Include simulation results and calculations

• Include circuit schematics if you think you have done somethingwrong (it is easier for us to help you)

• Include the code you have written yourself

• Answer all questions asked in the lab manual

• Write concisely

• No handwritten reports

• Reports shall be handed in (paper copy, no email attachments) toPietro Andreani


Lab Session Schedule

• Lab Seminar – Monday Nov. 14th 18-20

• Lab Session 1a – Wednesday Nov. 15th, 8-12 (Blåtunga)

• Lab Session 1b – Wednesday Nov. 15th, 13-17 (Blåtunga)

• Lab Session 2a – Wednesday Nov. 22nd, 8-12 (Blåtunga)

• Lab Session 2b – Wednesday Nov. 22nd, 13-17 (Blåtunga)

• Lab Session 3a – Wednesday Nov. 29th, 8-12 (Blåtunga)

• Lab Session 3b – Wednesday Nov. 29th, 13-17 (Blåtunga)


Labs – Overview

1. Studies of the FFT, sampling and quantization using MATLAB –illustrates mathematical modeling of mixed-signal systems usingMATLAB.

2. Circuit-level modeling and simulation of mixed-signal circuits usingVerilog-A modules

3. Circuit-level modeling and simulation of a flash ADC and apipelined ADC using the AMS simulator


Lab 1


Lab 1 – Learning Objectives

• Mathematical models and simulation using MATLAB• Efficient MATLAB code• How to perform a good FFT• Fundamental accuracy limitations in ADCs• Sampling• Quantization• System simulations• Performance metrics for ADCs (and DACs) – SNR, SNDR, INL, DNL,

ENOB, ERBW, SFDR ...


Lab 1 – Taking a Good FFT

• Coherent sampling! Make the FFT window an integer number ofsignal periods, with no repetition of the samples ⇓ make sure thatfin = m∙fs /N, where m is an odd integer prime and N (number ofsamples) is a power of 2

• The required simulation time will be proportional to N∙log(N), so donot choose N unnecessarily large

• If windowing is used, compensate for the amplitude loss introducedby the window function. In assignment #1 this is accomplishedautomatically (for the hann window) with the code in adcperf.m

• The noise floor is also affected by windowing. For a hann window,the noise bandwidth is NBW = 1.5/N, while for a rectangularwindow it is NBW =1/N


Lab 1 – Sampling

• Signal folding (aliasing)

• Sampling noise (kT/C)

• Sampling instant uncertainty (clock jitter)

• Non-linearity


Lab 1 – Quantization

• White noise equivalent of the quantization error

• Quantization error power and SNR

• Statistical properties of quantization errors (random signal??)

• Additive circuit noise and non-linearity


Lab 2



• Circuit design and simulation with Cadence

• Verilog-A syntax

• Circuit models with Verilog-A

• Simulation of Verilog-A modules

• Use of Hierarchy Editor (config views)


Lab 2 – Getting help

• Seminar slides + FAQ on the course homepage

• Online documentation- Open through forms and windows in Cadence- Type cdnshelp & to launch online documentation

• Cadence Verilog-A language manual, available at/usr/local-eit/cad2/cadence/ic616/doc/verilogamsref/verilogamsref.pdf

• Reference material- Fitzpatrick and Miller, ”Analog Behavioral Modeling with the Verilog-A Language”,Kluwer Academic Publishers, 1998.- Kundert and Zinke, ”The Designers Guide to Verilog-AMS”, Kluwer AcademicPublishers, 2004.


Lab 2 – Verilog-A Overview

• Verilog-A is an extension of Verilog, used to describe analog andmixed-signal circuits. It is an Open Verilog International (OVI)standard

• Multidisciplinary: it can model electrical, mechanical, fluid andthermodynamic systems

• Used with spectre circuit simulator in the Virtuoso Analog DesignEnvironment, in the Analog Workbench (AWB) or in Virtuoso AMSDesigner

• Supports top-down design and greatly speeds up system simulationtimes


Lab 2 – Creating Verilog-A ModulesCreate a veriloga view Enter the behavioral description

A symbol can be createdautomatically when the

veriloga view is saved (simpler,however, than this one)


• A veriloga view requires a symbol view in order to be instantiatedin a higher-level schematic. If a schematic view of the same cellalso exists, all three views (veriloga, schematic, symbol) musthave the same pin names.

Lab 2 – Verilog-A View

schematic view

symbol view

veriloga view


Lab 2 – Simulate Verilog-A in ADEFor spectre to simulate your modules,the veriloga view must be in theSwitch View List and Stop View List

Setup simulator:spectre for

veriloga, AMSfor mixed mode

Netlist andrun simulation

Generatewaveforms


Lab 2 – More on Simulation

• When creating cell views with names other than the default names(e.g., veriloga_2), adjust the Switch View List and Stop View Listsaccordingly

• In mixed-signal mode, or with large analog configurations, use theHierarchy Editor to choose the specific views that should be usedin simulation (more about this later)

• The Hierarchy Editor is strictly required only in the mixed-signalmode, where the simulator is AMS (which is selected as templatewhen creating the config view of the design)


Lab 2 – Verilog-A in ADE

Start CIW withinittde adda17

Open the LibraryManager

Create a new CellView... Select

VerilogA Editor

Text editor openswith header and

footer for Verilog-A Module

Add or edit textwithin the text

file

Save text file &close text editor

Syntaxcorrect

?

Generate or editsymbol view

Place symbol viewin test-bench

schematic

Run simulation onyour test bench

Verify modulebehavior andperformance

Module (symbol)can be used in

other schematics

No

Yes


Lab 2 – Verilog-A in ADE

’include ”constants.vams”’include ”disciplines.vams”

module MyRes(p,n);

inout p,n;electrical p,n;parameter real R = 1 from (0:inf);parameter real tc = 1.5m from [0:3m);

real Reff;

analog begin@(initial_step) beginReff = R*(1+tc*$temperature);

endI(p,n) <+ V(p,n) / Reff;

end

endmodule

’include files needed in thebehavioral model

Interface declarations:- Module name

- Port directions anddisciplines

- Parameter declarations withdefault values

- Internal variables

Behavioral models useanalog behavioral statements


Lab 2 – Standard Include Files

• ’include ”disciplines.vams”- A set of disciplines and natures that define the signal types- Cadence provides a working sample of a disciplines.vams file at:<install_dir>/tools/spectre/etc/ahdl

• ’include ”constants.vams”- Defines a set of mathematical and physical constants.- Cadence provides a working sample of a constants.vams file at:<install_dir>/tools/spectre/etc/ahdl- Mathematical constants have ’M_ prefix, ex: ’M_PI- Physical constants have ’P_ prefix, ex: ’P_K (Boltzmann’s constant)


Lab 2 – Port Declaration• Input signals

- Cannot be set, but can be used in expressions• Output signals

- Can be set, but cannot be used in expressions• Inout signals (default)

- Are bidirectional. Can be both set and used in expressions

module gainer (out,in); // Declares two portsoutput out; // Declares port as outputinput in; // Declares port as inputelectrical in, out; // Declares port discipline

parameter real gain = 2.0;analog

V(out) <+ gain * V(in);endmodule


Lab 2 – Declaring Parameters• Use parameters to customize module – each module instance may have

different parameter values- Specify default value for each parameter- Specify an optional type and an optional valid range

module sdiode(np,nn);inout np,nn;electrical np,nn;parameter real area = 1;parameter real is = 1e-14;parameter real n = 2;parameter real cjo = 0;parameter real m = 0.5;parameter real phi = 0.7, tt = 1p;real vd,id,gd;

analog beginvd = V(np,nn);id = area*is*(exp(vd/(n*$vt))-1);gd = tt*id + area*vd*cjo/pow((1-vd/phi),m);I(np,nn) <+ id + ddt(gd);

endendmodule

• $vt is the thermal voltage, kT/q, with temperature T set as in the simulator


Lab 2 – Parameter Ranges• Use the optional range specification to express valid parameter ranges for

the behavioral model formulation• If the range specification is violated during instantiation, the simulation

will be terminated• Range boundaries can be included or excluded, as shown in the example:

parameter real resistance = 1;parameter real vol_high = 5, vol_low = 0;parameter real gain = 1 from [0:1K);parameter real pole = 1 exclude [0];parameter real frequency = 1 from (0:inf);

”[” or ”]” implies the boundary is included”(” or ”)” implies the boundary is NOT included


Lab 2 – Contribution Operator <+• The contribution operator <+ is only applied to signal access functions,

i.e. V (for potential) or I (for flow) signals• IMPORTANT: the contribution operator accumulates V or I on successive

contribution statements

V(a) <+ 0; // sets ’a’ to 0VI(p,n) <+ V(p,n)/r; // models resistance between p and nV(p,n) <+ I(p,n)*r; // models resistance between p and nI(p,n) <+ ddt(c*V(p,n)); // models a capacitance between p and nV(p,n) <+ ddt(L*I(p,n)); // models inductance between p and nV(out) <+ 1.0; // out is 1 volt relative to groundV(out) <+ gain*V(in); // out is gain times more than inV(out) <+ idt(V(in), 0); // integrates the output voltage with

// respect to time, setting initial// condition to 0V


Lab 2 – Contribution vs Assignment• Contribution statements (<+) allow input signals to be mapped to output

signals, and implicitly define circuital branch relations according to KVL orKCL. The branch is directed from the first node of the access function tothe second node, or to the reference node if the second node is omitted

• Assignment operators (=) can only be applied to variables, whereascontribution operators can only be applied to access functions (V or I)

• Assigning a number to a variable (e.g., x=4) overrides the numberpreviously contained in that variable, whereas a contribution to an accessfunction (e.g., V(x) <+ 4) is added to any previous contributions

• Contributions to a current can be viewed as adding current sources inparallel, while contributions to a voltage can be viewed as adding voltagesources in series


Lab 2 – Example: Parallel Resonant Tank

• Behavioral descriptions are defined in the analog block (and only there)• The behavioral description is a relationship between the input signals and

the output signals

module rlc(a,b);inout a,b;electrical a,b;parameter real R = 1k exclude 0;parameter real C = 1p;parameter real L = 1n exclude 0;

analog beginI(a,b) <+ V(a,b)/R;I(a,b) <+ ddt(V(a,b)*C);I(a,b) <+ idt(V(a,b)/L);

endendmodule


Lab 2 – Implicit Equations• The contribution operator supports implicit equations, where the same

quantity x is used on both sides of the equation: solves for x when used inx <+ f(x), as illustrated below in the diode model

• The equation below describes a diode current, and has I(a,c) on bothsides of the contribution operator

module diode(a,c);inout a,c;electrical a,c;parameter real r = 1f from (0:inf);parameter real rs = 0 from [0:inf);

analog beginI(a,c) <+ is * ($limexp((V(a,c) – rs * I(a,c))/$vt) – 1);

endendmodule

• limexp is the exponential function with special limiting algorithms toimprove convergence


Lab 2 – Internal Nodes• When necessary, modules can have local internal nodes to define:

- Internal branch relationships- Higher-order or nonlinear differential equations

module dline(p1,p2);inout p1,p2;electrical p1,p2,n1;parameter real delay = 50p, zo=75;real L,C;

analog begin@(initial_step) begin

L = zo*delay/2;C = delay/zo;

endV(p1,n1) <+ ddt(L*I(p1,n1));V(p2,n1) <+ ddt(L*I(p2,n1));I(n1) <+ ddt(C*V(n1));

endendmodule


Lab 2 – Declaring Buses• A net discipline declaration associates a net to a previously defined

description- Nets declared without a range are called scalar nets- A net declared with a range is called a vector or bus net:

electrical [1:10] n1;electrical [3:0] n2;

• The module below uses an input bus, where only the name is appearing inthe list of ports – the range is defined inside the module (i.e., [4:0])module five_inputs(portbus);

input [4:0] portbus;electrical [4:0] portbus;

analog begingenerate i (4, 0)

V(portbus[i]) <+ 0.0;end

endmodule


Lab 2 – Event-Driven Modeling

The simulator generates analog events that can be used by Verilog-A tocontrol the behavior of the veriloga model

Event-driven modeling uses the @event command to execute a block of codewhen event occursTypes of events supported by Verilog-A modeling are:

initial_step At the beginning of the simulationfinal_step At the end of the simulationcross() At analog signal crossingslast_crossing() At last analog signal crossingstimer() Periodically at a specific time


Lab 2 – The Timer Operator• The timer event operator can be used to generate events at a specified

time or at specified time intervals during simulation- Example: the squarewave module below produces a square-wave voltagewaveform with a period of 1s:

module squarewave(out);output out;electrical out;parameter period = 1.0;integer x;

analog begin@(initial_step) x = 1;@(timer(0, period/2)) x = -x;V(out) <+ transition(x, 0.0, period/100.0);

endendmodule


Lab 2 – Simulator Settings• Verilog-A provides an environment parameter function that can be used to

obtain the current internal simulation time in seconds: $abstime- Example: $strobe(”Simulation time = %e”, $abstime)

• The ambient temperature of a circuit in Kelvin degrees can be obtainedusing: $temperature- Example: temp := $temperature

• The thermal voltage (VT=kT/q) can be obtained using $vt- Example: vt_function := $vt(temp)- When not specifying temp, the thermal voltage is calculated at the temperaturereturned by the $temperature function


Lab 2 – Verilog-A Table Models• A Table Model models the component behavior through a look-up table

(LUT, which can be derived from spectre simulations or actualmeasurements)- LUTs instead of complex netlists for shorter simulation times- IP protection- Can be used to import any table of values- Can be extracted using skill scripts- Interpolation between tabulated values

• Example of Verilog-A syntax for a MOSFET table model:module mynmos(g,s,d)electrical g,s,d;inout g,s,d;

analog beginI(d,s) <+ $table_model(V(g,s), V(d,s), ”nmos.tbl”,”3CL,3CL”);

endendmodule


Lab 2 – More Modeling Details• Random number support

• Noise modeling

• Functions and operators (mod, shift ...)

• Conditional statements (if-else, case, while, for ...)

• Analog operators (sin, tan ...)

• Slew-rate and transitions

• File handling (open, close, read and write)

• Laplace transform and z-transform

• Displaying results ($display, $strobe ...)• …


Lab 3



• Principles of modeling mixed-signal designs using Cadence

• Design partitioning to enable mixed-mode simulations with theAMS simulator

• Use of Cadence Hierarchy Editor (config views)

• Design of flash A/D converter

• Design of pipeline A/D converter

• Evaluating static and dynamic circuit performance using Cadenceand MATLAB


Lab 3 – Why Mixed-Signal Simulation

• Mixed-signal systems are both analog and digital ⇓ bothsensitive/simple (analog part) and robust/complex (digital part)

• Much higher complexity than ”analog-only” circuitry

• However, same accuracy requirements as purely analog circuits, atleast for some of the analog blocks

• Analog circuit simulators are accurate but slow

• Analog circuit simulators are dedicated to typical analog design issuessuch as gain, bandwidth, noise and distortion

• Digital circuit simulators are much faster, but not as accurate

• Simulating digital circuits using analog simulators is extremely slow!


Lab 3 – Analog vs. Digital

spectre

spectreveriloga

cmos_sch

verilog

functional

incisive

incisive

Most accurateSlowest

Less accurateSlower

Rather accurateFaster

Least accurateFastest


Lab 3 – AMS simulation

• Simulation with the AMS simulator (incisive + spectre)

• Build test bench (schematic view)

• Create, edit and save the config view of the test bench

• Open the schematic view from the config view

• Open the Analog Design Environment from schematic window

• Setup design files and environment where needed

• Run simulations


Lab 3 – The Mixed-Signal Circuit


Lab 3 – Libraries, views, simulators

• analogLib – Ideal analog passive components, signal sources,groundsViews to use: “spectre”; Simulator: AMS (spectre)

• CORE65GPSTV – Digital standard cells from the foundrySTMicroelectronics (for technical reasons, copied to a local library)Views to use: verilog / cmos_schSimulator: AMS (Incisive) / AMS (spectre)

• cmos065 – Analog circuit elements (such as transistors) fromSTMicroelectronisViews to use: “spectre”; Simulator: AMS (spectre)

• Your design librariesViews to use: veriloga, functional, schematic, layout ...Simulator: AMS


Lab 3 – The Hierarchy EditorFor each cell, select which view should be used in simulations

Openschematic

fromconfig


Lab 3 – The Hierarchy EditorIn the Tree View of the config, it is possible to specify what view to use notonly for each cell, but also for each instance of each cell (however, thereseems to be a kind of bug …)


Lab 3 – The Associated Schematic

Any change in schematic opened from config will be reflected in config


SCANDINAVIAN EXCELLENCEDEF INED IN LUND

etin55 – lab seminar - lth · 2017-11-09 · etin55 – lab seminar ... • assignment 1 – fft,...

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