ethernet controller for isasingle-chip ethernet controller for the industry standard architecture...

PRELIMINARY

This document contains information on a product under dis intended to help you evaluate this product. AMD reserveproduct without notice.

Am79C961APCnet™-ISA II Jumperless, Full Duplex Single-ChipEthernet Controller for ISA

DISTINCTIVE CHARACTERISTICS Single-chip Ethernet controller for the Industry

Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) buses

Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards

Supports full duplex operation on the 10BASE-T, AUI, and GPSI ports

Direct interface to the ISA or EISA bus

Pin compatible to Am79C961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller

Software compatible with AMD’s Am7990 LANCE register and descriptor architecture

Low power, CMOS design with sleep mode allows reduced power consumption for critical battery powered applications

Individual 136-byte transmit and 128-byte receive FIFOs provide packet buffering for increased system latency, and support the following features:

— Automatic retransmission with no FIFOreload

— Automatic receive stripping and transmitpadding (individually programmable)

— Automatic runt packet rejection

— Automatic deletion of received collisionframes

Dynamic transmit FCS generation programmable on a frame-by-frame basis

Single +5 V power supply

Internal/external loopback capabilities

Supports 8K, 16K, 32K, and 64K Boot PROMs or Flash for diskless node applications

Supports Microsoft’s Plug and Play System configuration for jumperless designs

Supports staggered AT bus drive for reduced noise and ground bounce

Supports 8 interrupts on chip

Look Ahead Packet Processing (LAPP) allows protocol analysis to begin before end of receive frame

Supports 4 DMA channels on chip

Supports 16 I/O locations

Supports 16 boot PROM locations

Provides integrated Attachment Unit Interface (AUI) and 10BASE-T transceiver with 2 modes of port selection:

— Automatic selection of AUI or 10BASE-T

— Software selection of AUI or 10BASE-T

Automatic Twisted Pair receive polarity detection and automatic correction of the receive polarity

Supports bus-master, programmed I/O, and shared-memory architectures to fit in any PC application

Supports edge and level-sensitive interrupts

DMA Buffer Management Unit for reduced CPU intervention which allows higher throughput by by-passing the platform DMA

JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test

Integrated Manchester Encoder/Decoder

Supports the following types of network interfaces:

— AUI to external 10BASE2, 10BASE5,10BASE-T or 10BASE-F MAU

— Internal 10BASE-T transceiver with SmartSquelch to Twisted Pair medium

Supports LANCE General Purpose Serial Interface (GPSI)

132-pin PQFP package

evelopment at Advanced Micro Devices. The informations the right to change or discontinue work on this proposed

Publication# 19364 Rev: A Amendment/+3Issue Date: September 1996

P R E L I M I N A R Y

GENERAL DESCRIPTION The PCnet-ISA II controller, a single-chip Ethernet con-troller, is a highly integrated system solution for thePC-AT Industry Standard Architecture (ISA) architec-ture. It is designed to provide flexibility and compatibil-ity with any existing PC application. This highlyintegrated 132-pin VLSI device is specifically designedto reduce parts count and cost, and addresses applica-tions where higher system throughput is desired. ThePCnet-ISA II controller is fabricated with AMD’sadvanced low-power CMOS process to provide lowstandby current for power sensitive applications.

The PCnet-ISA II controller can be configured into oneof three different architecture modes to suit a particularPC application. In the Bus Master mode, all transfersare performed using the integrated DMA controller.This configuration enhances system performance byallowing the PCnet-ISA II controller to bypass the plat-form DMA controller and directly address the full 24-bitmemory space. The implementation of Bus Mastermode allows minimum parts count for the majority ofPC applications. The PCnet-ISA II can also be config-ured as a Bus Slave with either a Shared Memory orProgrammed I/O architecture for compatibility withlow-end machines, such as PC/XTs that do not supportBus Masters, and high-end machines that require localpacket buffering for increased system latency.

The PCnet-ISA II controller is designed to directly inter-face with the ISA or EISA system bus. It contains anISA Plug and Play bus interface unit, DMA Buffer Man-agement Unit, 802.3 Media Access Control function,individual 136-byte transmit and 128-byte receive

FIFOs, IEEE 802.3 defined Attachment Unit Interface(AUI), and a Twisted Pair Transceiver Media Attach-ment Unit. Full duplex network operation can beenabled on any of the device’s network ports. ThePCnet-ISA II controller is also register compatible withthe LANCE (Am7990) Ethernet control ler andPCnet-ISA. The DMA Buffer Management Unit sup-ports the LANCE descriptor software model. Externalremote boot and Ethernet physical address PROMsand Electrically Erasable Proms are also supported.

This advanced Ethernet controller has the built-incapability of automatically selecting either the AUI portor the Twisted Pair transceiver. Only one interface isactive at any one time. The individual 136-byte transmitand 128-byte receive FIFOs optimize system over-head, providing sufficient latency during packet trans-mission and reception, and minimizing interventionduring normal network error recovery. The integratedManchester encoder/decoder eliminates the need foran external Serial Interface Adapter (SIA) in the nodesystem. If support for an external encoding/decodingscheme is desired, the embedded General PurposeSerial Interface (GPSI) allows direct access to/from theMAC. In addition, the device provides programmableon-chip LED drivers for transmit, receive, collision,receive polarity, link integrity and activity, or jabberstatus. The PCnet-ISA II controller also provides anExternal Address Detection InterfaceTM (EADITM) toallow external hardware address filtering in internet-working applications.

RELATED PRODUCTS

Part No. Description

Am79C98 Twisted Pair Ethernet Transceiver (TPEX)

Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver

Am79C981 Integrated Multiport Repeater Plus (IMR+ )

Am79C987 Hardware Implemented Management Information Base (HIMIB )

Am79C940 Media Access Controller for Ethernet (MACE )

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)

Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)

Am79C961 PCnet-ISA Jumperless Single-Chip Ethernet Controller (for ISA bus)

Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller (for 386, 486, VL local buses)

Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)

Am79C974 PCnet-SCSI Combination Single-Chip Ethernet and SCSI Controller (for PCI bus)

2 Am79C961A


ORDERING INFORMATION

Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formedby a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations andto check on newly released combinations.

AM79C961A K C \W

ALTERNATE PACKAGING OPTION\W=Trimmed and Formed (PQB132)

OPTIONAL PROCESSINGBlank=Standard Processing

TEMPERATURE RANGEC=Commercial (0°C to +70°C)

PACKAGE TYPE (per Prod. Nomenclature/16-038)K=Molded Carrier Ring Plastic Quad Flat Pack(PQB132)

SPEEDNot Applicable

DEVICE NUMBER/DESCRIPTIONAm79C961APCnet-ISA II Jumperless Single-Chip Ethernet Controller for ISA

Valid Combinations

AM79C961A KC, KC\W

Am79C961A 3


TABLE OF CONTENTSDISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 RELATED PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 STANDARD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3BLOCK DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10CONNECTION DIAGRAM: BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11PIN DESIGNATIONS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12LISTED BY PIN GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

PIN DESCRIPTIONS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16IEEE P996 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16BOARD INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

PLUG AND PLAY ISA CARD STATE TRANSITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20BLOCK DIAGRAM: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21CONNECTION DIAGRAMS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22PIN DESIGNATIONS: BUS SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

PIN DESCRIPTIONS: BUS SLAVE MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

PIN DESCRIPTIONS: NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30TWISTED PAIR INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

PIN DESCRIPTIONS: POWER SUPPLIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30CONNECTION DIAGRAM (TQFP 144). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31PIN DESCRIPTIONS: BUS MASTER MODE (TQFP 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

PIN DESCRIPTIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144) . . . . . . . . . . . .34LISTED BY PIN NUMBER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36IMPORTANT NOTE ABOUT THE EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

PLUG AND PLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40AUTO-CONFIGURATION PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40INITIATION KEY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40ISOLATION PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41HARDWARE PROTOCOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41SOFTWARE PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42PLUG AND PLAY CARD CONTROL REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

PLUG AND PLAY LOGICAL DEVICE CONFIGURATION REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . .45DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46AMD DEVICE DRIVER COMPATIBLE EEPROM BYTE MAP . . . . . . . . . . . . . . . . . . . . . . . . . . .48PLUG AND PLAY REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49PCNET-ISA II’S LEGACY BIT FEATURE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

PLUG & PLAY REGISTER LOCATIONS DETAILED DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51VENDOR DEFINED BYTE (PNP 0XF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52CHECKSUM FAILURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53USE WITHOUT EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53EXTERNAL SCAN CHAIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

4 Am79C961A


FLASH PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53OPTIONAL IEEE ADDRESS PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54EISA CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54BUS INTERFACE UNIT (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54DMA TRANSFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

1. INITIALIZATION BLOCK DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542. DESCRIPTOR DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .543. FIFO DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

BUFFER MANAGEMENT UNIT (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56REINITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56BUFFER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56DESCRIPTOR RINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56DESCRIPTOR RINGS ACCESS MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57POLLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58TRANSMIT DESCRIPTOR TABLE ENTRY (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59RECEIVE DESCRIPTOR TABLE ENTRY (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61TRANSMIT AND RECEIVE MESSAGE DATA ENCAPSULATION. . . . . . . . . . . . . . . . . . . . . . . .61MANCHESTER ENCODER/DECODER (MENDEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64EXTERNAL CRYSTAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64EXTERNAL CLOCK DRIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65MENDEC TRANSMIT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65TRANSMITTER TIMING AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65INPUT SIGNAL CONDITIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65CLOCK ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65PLL TRACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66CARRIER TRACKING AND END OF MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66DATA DECODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66DIFFERENTIAL INPUT TERMINATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66COLLISION DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66JITTER TOLERANCE DEFINITION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67ATTACHMENT UNIT INTERFACE (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67TWISTED PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67TWISTED PAIR TRANSMIT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67TWISTED PAIR RECEIVE FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67POLARITY DETECTION AND REVERSAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68TWISTED PAIR INTERFACE STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68COLLISION DETECT FUNCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION . . . . . . . . . . . . . . . . . . . . .69JABBER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69FULL DUPLEX OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69EADI (EXTERNAL ADDRESS DETECTION INTERFACE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70GPSI (GENERAL PURPOSE SERIAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72BOUNDARY SCAN CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72SUPPORTED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72INSTRUCTION REGISTER AND DECODING LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72OTHER DATA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72POWER SAVING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72ACCESS OPERATIONS (SOFTWARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Am79C961A 5


I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73I/O REGISTER ACCESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73IEEE ADDRESS ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73BOOT PROM ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73STATIC RAM ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73BUS CYCLES (HARDWARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73BUS MASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74ADDRESS PROM CYCLES EXTERNAL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74ADDRESS PROM CYCLES USING EEPROM DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75ETHERNET CONTROLLER REGISTER CYCLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75TRANSMIT OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80TRANSMIT FUNCTION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80AUTOMATIC PAD GENERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80TRANSMIT FCS GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81TRANSMIT EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81RECEIVE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

RECEIVE FUNCTION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82AUTOMATIC PAD STRIPPING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82RECEIVE FCS CHECKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83RECEIVE EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

MAGIC PACKET OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84MAGIC PACKET MODE ACTIVATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84MAGIC PACKET RECEIVE INDICATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

LOOPBACK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

PCNET-ISA II CONTROLLER REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86REGISTER ACCESS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

RAP: REGISTER ADDRESS PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86CONTROL AND STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

CSR0: PCnet-ISA II Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86CSR1: IADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88CSR2: IADR[23:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90CSR5: Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91CSR6: RCV/XMT Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92CSR8: Logical Address Filter, LADRF[15:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92CSR9: Logical Address Filter, LADRF[31:16]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92CSR10: Logical Address Filter, LADRF[47:32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92CSR11: Logical Address Filter, LADRF[63:48]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92CSR12: Physical Address Register, PADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93CSR13: Physical Address Register, PADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93CSR14: Physical Address Register, PADR[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93CSR15: Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93CSR16: Initialization Block Address Lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95CSR18-19: Current Receive Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95CSR20-21: Current Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95CSR22-23: Next Receive Buffer Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR24-25: Base Address of Receive Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR26-27: Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR28-29: Current Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR30-31: Base Address of Transmit Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR32-33: Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR34-35: Current Transmit Descriptor Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR36-37: Next Next Receive Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR38-39: Next Next Transmit Descriptor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96CSR40-41: Current Receive Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

6 Am79C961A


CSR42-43: Current Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97CSR44-45: Next Receive Status and Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97CSR46: Poll Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97CSR47: Polling Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97CSR48-49: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97CSR50-51: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97CSR52-53: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR54-55: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR56-57: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR58-59: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR60-61: Previous Transmit Descriptor Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR62-63: Previous Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR64-65: Next Transmit Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR66-67: Next Transmit Status and Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98CSR70-71: Temporary Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99CSR72: Receive Ring Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99CSR74: Transmit Ring Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99CSR76: Receive Ring Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99CSR78: Transmit Ring Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99CSR80: Burst and FIFO Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99CSR82: Bus Activity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100CSR84-85: DMA Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101CSR88-89: Chip ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101CSR92: Ring Length Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101CSR94: Transmit Time Domain Reflectometry Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101CSR96-97: Bus Interface Scratch Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102CSR98-99: Bus Interface Scratch Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102CSR104-105: SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102CSR108-109: Buffer Management Scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102CSR112: Missed Frame Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102CSR124: Buffer Management Unit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

ISA BUS CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104ISACSR0: Master Mode Read Active/SRAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . .104ISACSR1: Master Mode Write Active/SRAM Address Pointer . . . . . . . . . . . . . . . . . . . . . . .104ISACSR2: Miscellaneous Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105ISACSR3: EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106ISACSR4: LED0 Status (Link Integrity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107ISACSR5: LED1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107ISACSR6: LED2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108ISACSR7: LED3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109ISACSR8: Software Configuration Register (Read-Only Register) . . . . . . . . . . . . . . . . . . . .110ISACSR9: Miscellaneous Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Initialization Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110RLEN and TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110RDRA and TDRA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111LADRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111PADR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Receive Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112RMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112RMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112RMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112RMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Transmit Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113TMD0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113TMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Am79C961A 7


TMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114TMD3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116Ethernet Controller Registers (Accessed via RDP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port). . . . . . . . . . . . . . . . . .118

SYSTEM APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Compatibility Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119Shared Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Optional Address PROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122Boot PROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122Static RAM Interface (for Shared Memory Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12310BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . .124SWITCHING CHARACTERISTICS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE . . . . . . . . . . . . . . . . .130SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH WRITE CYCLE . . . . . . . . . . . . . . . .130SWITCHING CHARACTERISTICS: SHARED MEMORY MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE. . . . . . . . . . . . .134SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH WRITE CYCLE. . . . . . . . . . . .134SWITCHING CHARACTERISTICS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . .135SWITCHING CHARACTERISTICS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136SWITCHING CHARACTERISTICS: AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139SWITCHING WAVEFORMS: BUS MASTER MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142SWITCHING WAVEFORMS: SHARED MEMORY MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152SWITCHING WAVEFORMS: GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162SWITCHING WAVEFORMS: EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163SWITCHING WAVEFORMS: AUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164SWITCHING WAVEFORMS: 10BASE-T INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

PQB132 Plastic Quad Flat Pack Trimmed and Formed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170PQB132 Molded Carrier Ring Plastic Quad Flat Pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

APPENDIX A: PCNET-II COMPATIBLE MEDIA INTERFACE MODULES. . . . . . . . . . . . . . . . . . . . . . . .172PCnet-ISA II COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS . . . . . . . . . . . . . . . . . . . . . . . .172PCnet-ISA II Compatible AUI Isolation Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 PCnet-ISA II Compatible DC/DC Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 MANUFACTURER CONTACT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 APPENDIX B: LAYOUT RECOMMENDATIONS FOR REDUCING NOISE. . . . . . . . . . . . . . . . . . . . . . . .174DECOUPLING LOW-PASS R/C FILTER DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Digital Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Analog Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 AVSS1 and AVDD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 AVSS2 and AVDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 AVSS2 and AVDD2/AVDD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 APPENDIX C: SAMPLE PLUG AND PLAY CONFIGURATION RECORD . . . . . . . . . . . . . . . . . . . . . . . .176SAMPLE CONFIGURATION FILE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 APPENDIX D: ALTERNATIVE METHOD FOR INITIALIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

8 Am79C961A


APPENDIX E: INTRODUCTION OF THE LOOK AHEAD PACKET PROCESSING(LAPP) CONCEPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179Outline of the LAPP Flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 SETUP: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 FLOW: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 LAPP Enable Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 LAPP Enable Rules for Parsing of Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184APPENDIX F: SOME CHARACTERISTICS OF THE XXC56 SERIAL EEPROM . . . . . . . . . . . . . . . . . . .188SWITCHING CHARACTERISTICS of a TYPICAL XXC56 SERIAL EEPROM INTERFACE . . . . . . . . . . .188 INSTRUCTION SET FOR THE XXC56 SERIES OF EEPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Am79C961A 9


BLOCK DIAGRAM: BUS MASTER MODE

19364A-1

ISA BusInterface

Unit

RCVFIFO

XMTFIFO

FIFOControl

BufferManagement

Unit

EEPROMInterface

Unit

802.3MACCore

Encoder/Decoder(PLS) &AUI Port

10BASE-TMAU

PrivateBus

Control

JTAGPort

Control

AEN

DACK[3, 5–7]

DRQ[3, 5–7]

IOCHRDY

IOCS16

IOR

IOWIRQ[3, 4, 5, 9,

10, 11, 12]MASTER

MEMR

MEMW

REF

RESET

SBHE

BALE

SD[0-15]

LA[17-23]

SA[0-19]

SLEEPSHFBUSY

EEDOEEDI

EESKEECS

DVDD[1-7]

DVSS[1-13]

AVDD[1-4]

AVSS[1-2]

DXCVR/EAR

CI+/–

DI+/–

XTAL1

XTAL2

DO+/–

RXD+/–

TXD+/–

TXPD+/–

IRQ15/APCS

BPCSLED[0–3]

PRDB[0–7]

TDO

TMS

TDI

TCK

10 Am79C961A


CONNECTION DIAGRAMS: BUS MASTER MODE

132

1

DV

DD

2T

CK

131

TM

S13

0T

DO

129

TD

I12

8E

EC

S12

7B

PC

S12

6S

HF

BU

SY

125

PR

DB

0/E

ES

K12

4P

RD

B1/

EE

DI

123

PR

DB

2/E

ED

O12

2P

RD

B3

121

DV

SS

212

0P

RD

B4

119

PR

DB

511

8P

RD

B6

117

PR

DB

711

6D

VD

D1

115

LED

011

4LE

D1

113

DV

SS

111

2LE

D2

111

LED

311

0D

XC

VR

/EA

R10

9A

VD

D2

108

CI+

107

CI–

106

DI+

105

DI–

104

AV

DD

110

3D

O+

102

DO

–10

1A

VS

S1

100

XTAL299AVSS298XTAL197AVDD396TXD+95TXPD+94TXD–93TXPD–92AVDD491RXD+90RXD–89DVSS1388SD1587SD786SD1485SD684DVSS983SD1382SD581SD1280SD479DVDD778SD1177SD376SD1075SD274DVSS873SD972SD171SD870SD069SLEEP68DVDD667

34D

VD

D4

35S

A12

36S

A13

37S

A14

38S

A15

39S

A16

40S

A17

41S

A18

42S

A19

43A

EN

44IO

CH

RD

Y45

ME

MW

46M

EM

R47

DV

SS

1148

IRQ

15/A

PC

S49

IRQ

12/F

LAS

HW

E50

IRQ

1151

DV

DD

552

IRQ

1053

IOC

S16

54B

ALE

55IR

Q3

56IR

Q4

57IR

Q5

58 59D

VS

S12

60D

RQ

361

DA

CK

362

IOR

63IO

W64

IRQ

965

RE

SE

T66

DVSS32MASTER3DRQ74DRQ65DRQ56DVSS107DACK78DACK69DACK510LA1711LA1812LA1913LA2014DVSS415LA2116LA22 17LA2318SBHE19DVDD320SA021SA122SA223DVSS524SA325SA426SA527SA628SA729SA830SA931DVSS632SA1033SA11

Top Side View

RE

F

DV

SS

7

19364A-2

Am79C961A 11


PIN DESIGNATIONS: BUS MASTER MODE

Listed by Pin Number

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

1 DVSS3 34 DVDD4 67 DVDD6 100 AVSS1

2 MASTER 35 SA12 68 SLEEP 101 DO–

3 DRQ7 36 SA13 69 SD0 102 DO+

4 DRQ6 37 SA14 70 SD8 103 AVDD1

5 DRQ5 38 SA15 71 SD1 104 DI–

6 DVSS10 39 DVSS7 72 SD9 105 DI+

7 DACK7 40 SA16 73 DVSS8 106 CI–

8 DACK6 41 SA17 74 SD2 107 CI+

9 DACK5 42 SA18 75 SD10 108 AVDD2

10 LA17 43 SA19 76 SD3 109 DXCVR/EAR

11 LA18 44 AEN 77 SD11 110 LED3

12 LA19 45 IOCHRDY 78 DVDD7 111 LED2

13 LA20 46 MEMW 79 SD4 112 DVSS1

14 DVSS4 47 MEMR 80 SD12 113 LED1

15 LA21 48 DVSS11 81 SD5 114 LED0

16 LA22 49 IRQ15/APCS 82 SD13 115 DVDD1

17 LA23 50 IRQ12/FlashWE 83 DVSS9 116 PRDB7

18 SBHE 51 IRQ11 84 SD6 117 PRDB6

19 DVDD3 52 DVDD5 85 SD14 118 PRDB5

20 SA0 53 IRQ10 86 SD7 119 PRDB4

21 SA1 54 IOCS16 87 SD15 120 DVSS2

22 SA2 55 BALE 88 DVSS13 121 PRDB3

23 DVSS5 56 IRQ3 89 RXD– 122 PRDB2/EEDO

24 SA3 57 IRQ4 90 RXD+ 123 PRDB1/EEDI

25 SA4 58 IRQ5 91 AVDD4 124 PRDB0/EESK

26 SA5 59 REF 92 TXPD– 125 SHFBUSY

27 SA6 60 DVSS12 93 TXD– 126 BPCS

28 SA7 61 DRQ3 94 TXPD+ 127 EECS

29 SA8 62 DACK3 95 TXD+ 128 TDI

30 SA9 63 IOR 96 AVDD3 129 TDO

31 DVSS6 64 IOW 97 XTAL1 130 TMS

32 SA10 65 IRQ9 98 AVSS2 131 TCK

33 SA11 66 RESET 99 XTAL2 132 DVDD2

12 Am79C961A




Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

AEN 44 DVSS12 60 LED2 111 SA6 27

AVDD1 103 DVSS13 88 LED3 110 SA7 28

AVDD2 108 DVSS2 120 MASTER 2 SA8 29

AVDD3 96 DVSS3 1 MEMR 47 SA9 30

AVDD4 91 DVSS4 14 MEMW 46 SBHE 18

AVSS1 100 DVSS5 23 PRDB0/EESK 124 SD0 69

AVSS2 98 DVSS6 31 PRDB1/EEDI 123 SD1 71

BALE 55 DVSS7 39 PRDB2/EEDO 122 SD10 75

BPCS 126 DVSS8 73 PRDB3 121 SD11 77

CI– 106 DVSS9 83 PRDB4 119 SD12 80

CI+ 107 DXCVR/EAR 109 PRDB5 118 SD13 82

DACK3 62 EECS 127 PRDB6 117 SD14 85

DACK5 9 IOCHRDY 45 PRDB7 116 SD15 87

DACK6 8 IOCS16 54 REF 59 SD2 74

DACK7 7 IOR 63 RESET 66 SD3 76

DI– 104 IOW 64 RXD– 89 SD4 79

DI+ 105 IRQ10 53 RXD+ 90 SD5 81

DO– 101 IRQ11 51 SA0 20 SD6 84

DO+ 102 IRQ12/FlashWE 50 SA1 21 SD7 86

DRQ3 61 IRQ15/APCS 49 SA10 32 SD8 70

DRQ5 5 IRQ3 56 SA11 33 SD9 72

DRQ6 4 IRQ4 57 SA12 35 SHFBUSY 125

DRQ7 3 IRQ5 58 SA13 36 SLEEP 68

DVDD1 115 IRQ9 65 SA14 37 TCK 131

DVDD2 132 LA17 10 SA15 38 TDI 128

DVDD3 19 LA18 11 SA16 40 TDO 129

DVDD4 34 LA19 12 SA17 41 TMS 130

DVDD5 52 LA20 13 SA18 42 TXD– 93

DVDD6 67 LA21 15 SA19 43 TXD+ 95

DVDD7 78 LA22 16 SA2 22 TXPD– 92

DVSS1 112 LA23 17 SA3 24 TXPD+ 94

DVSS10 6 LED0 114 SA4 25 XTAL1 97

DVSS11 48 LED1 113 SA5 26 XTAL2 99

Am79C961A 13



Listed by Group

Pin Name Pin Function I/O Driver

ISA Bus Interface

AEN

BALE

DACK[3, 5–7]

DRQ[3, 5–7]

IOCHRDY

IOCS16

IOR

IOW

IRQ[3, 4, 5, 9, 10, 11, 12, 15]

LA[17-23]

MASTER

MEMR

MEMW

REF

RESET

SA[0 –19]

SBHE

SD[0 –15]

Address Enable

Bus Address Latch Enable

DMA Acknowledge

DMA Request

I/O Channel Ready

I/O Chip Select 16

I/O Read Select

I/O Write Select

Interrupt Request

Unlatched Address Bus

Master Transfer in Progress

Memory Read Select

Memory Write Select

Memory Refresh Active

System Reset

System Address Bus

System Byte High Enable

System Data Bus

I

I

I

I/O

I/O

O

I

I

O

I/O

O

O

O

I

I

I/O

I/O

I/O

TS3

OD3

OD3

TS3/OD3

TS3

OD3

TS3

TS3

TS3

TS3

TS3

Board Interfaces

IRQ15/APCS

BPCS

DXCVR/EAR

LED0

LED1

LED2

LED3

PRDB[3–7]

SLEEP

XTAL1

XTAL2

SHFBUSY

PRDB(0)/EESK

PRDB(1)/EEDI

PRDB(2)/EEDO

EECS

IRQ15 or Address PROM Chip Select

Boot PROM Chip Select

Disable Transceiver

LED0/LNKST

LED1/SFBD/RCVACT

LED2/SRD/RXDATPOL

LED3/SRDCLK/XMTACT

PROM Data Bus

Sleep Mode

Crystal Input

Crystal Output

Read access from EEPROM in process

Serial Shift Clock

Serial Shift Data In

Serial Shift Data Out

EEPROM Chip Select

O

O

I/O

O

O

O

O

I/O

I

I

O

I/O

I/O

I/O

O

TS1

TS1

TS1

TS2

TS2

TS2

TS2

TS1

14 Am79C961A


PIN DESIGNATIONS: BUS MASTER MODE (continued)

Listed by Group

Output Driver Types


Attachment Unit Interface (AUI)

CI±DI±DO±

Collision Inputs

Receive Data

Transmit Data

I

I

O

Twisted Pair Transceiver Interface (10BASE-T)

RXD±TXD±TXPD±

10BASE-T Receive Data

10BASE-T Transmit Data

10BASE-T Predistortion Control

I

O

O

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK

TDI

TDO

TMS

Test Clock

Test Data Input

Test Data Output

Test Mode Select

I

I

O

I

TS2

Power Supplies

AVDD

AVSS

DVDD

DVSS

Analog Power [1-4]

Analog Ground [1-2]

Digital Power [1-7]

Digital Ground [1-13]

Name Type IOL (mA) IOH (mA) pF

TS1 Tri-State 4 –1 50



OD3 Open Drain 24 –3 120

Am79C961A 15


PIN DESCRIPTION: BUS MASTER MODEThese pins are part of the bus master mode. In order tounderstand the pin descriptions, definition of someterms from a draft of IEEE P996 are included.

IEEE P996 TerminologyAlternate Master: Any device that can take control ofthe bus through assertion of the MASTER signal. It hasthe ability to generate addresses and bus control sig-nals in order to perform bus operations. All AlternateMasters must be 16 bit devices and drive SBHE.

Bus Ownership: The Current Master possesses busownership and can assert any bus control, address anddata lines.

Current Master: The Permanent Master, TemporaryMaster or Alternate Master which currently has owner-ship of the bus.

Permanent Master: Each P996 bus will have a deviceknown as the Permanent Master that provides certainsignals and bus control functions as described in Sec-tion 3.5 (of the IEEE P996 spec.), “Permanent Master”.The Permanent Master function can reside on a BusAdapter or on the backplane itself.

Temporary Master: A device that is capable of gener-ating a DMA request to obtain control of the bus anddirectly asserting only the memory and I/O strobesduring bus transfer. Addresses are generated by theDMA device on the Permanent Master.

ISA InterfaceAEN

Address Enable Input

This signal must be driven LOW when the bus performsan I/O access to the device.

BALEUsed to latch the LA20–23 address lines.

DACK 3, 5-7DMA Acknowledge Input

Asserted LOW when the Permanent Master acknowl-edges a DMA request. When DACK is asserted thePCnet-ISA II controller becomes the Current Master byasserting the MASTER signal.

DRQ 3, 5-7DMA Request Input/Output

When the PCnet-ISA II controller needs to perform aDMA transfer, it asserts DRQ. The Permanent Masteracknowledges DRQ with the assertion of DACK. Whenthe PCnet-ISA II does not need the bus it dessertsDRQ. The PCnet-ISA II provides for fair bus bandwidthsharing between two bus mastering devices on the ISAbus through an adaptive delay which is inserted

between back-to-back DMA requests. See theBack-to-Back DMA Requests section for details.

Because of the operation of the Plug and Play regis-ters, the DMA Channels on the PCnet-ISA II must beattached to the specific DRQ and DACK signals on thePC/AT bus as indicated by the pin names.

IOCHRDYI/O Channel Ready Input/Output

When the PCnet-ISA II controller is being accessed,IOCHRDY HIGH indicates that valid data exists on thedata bus for reads and that data has been latched forwrites. When the PCnet-ISA II controller is the CurrentMaster on the ISA bus, it extends the bus cycle as longas IOCHRDY is LOW.

IOCS16I/O Chip Select 16 Output

When an I/O read or write operation is performed, thePCnet-ISA II controller will drive the IOCS16 pin LOWto indicate that the chip supports a 16-bit operation atthis address. (If the motherboard does not receive thissignal, then the motherboard will convert a 16-bitaccess to two 8-bit accesses).

The PCnet-ISA II controller follows the IEEE P996 spec-ification that recommends this function be implementedas a pure decode of SA0-9 and AEN, with no depen-dency on IOR, or IOW; however, some PC/AT clone sys-tems are not compatible with this approach. For thisreason, the PCnet-ISA II controller is recommended tobe configured to run 8-bit I/O on all machines. Sincedata is moved by memory cycles there is virtually no per-formance loss incurred by running 8-bit I/O and compat-ibility problems are virtually eliminated. The PCnet-ISA IIcontroller can be configured to run 8-bit-only I/O byclearing Bit 0 in Plug and Play register F0.

IORI/O Read Input

IOR is driven LOW by the host to indicate that an Input/Output Read operation is taking place. IOR is only validif the AEN signal is LOW and the external addressmatches the PCnet-ISA II controller’s predefined I/Oaddress location. If valid, IOR indicates that a slaveread operation is to be performed.

IOWI/O Write Input

IOW is driven LOW by the host to indicate that an Input/Output Write operation is taking place. IOW is only validif AEN signal is LOW and the external address matchesthe PCnet-ISA II controller’s predefined I/O addresslocation. If valid, IOW indicates that a slave write oper-ation is to be performed.

16 Am79C961A


IRQ 3, 4, 5, 9, 10, 11, 12, 15Interrupt Request Output

An attention signal which indicates that one or more ofthe following status flags is set: BABL, MISS, MERR,RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT.All status flags have a mask bit which allows for sup-pression of IRQ assertion. These flags have thefollowing meaning:

Because of the operation of the Plug and Play regis-ters, the interrupts on the PCnet-ISA II must beattached to specific IRQ signals on the PC/AT bus.

LA17-23Unlatched Address Bus Input/Output

The unlatched address bus is driven by the PCnet-ISAII controller during bus master cycle.

The functions of these unlatched address pins willchange when GPSI mode is invoked. The followingtable shows the pin configuration in GPSI mode. Pleaserefer to the section on General Purpose Serial Interfacefor detailed information on accessing this mode.

MASTERMaster Mode Input/OutputThis signal indicates that the PCnet-ISA II controllerhas become the Current Master of the ISA bus. Afterthe PCnet-ISA II controller has received a DMAAcknowledge (DACK) in response to a DMA Request

(DRQ), the Ethernet controller asserts the MASTERsignal to indicate to the Permanent Master that thePCnet-ISA II controller is becoming the Current Master.

MEMRMemory Read Input/OutputMEMR goes LOW to perform a memory read operation.

MEMWMemory Write Input/OutputMEMW goes LOW to perform a memory wr iteoperation.

REFMemory Refresh InputWhen REF is asserted, a memory refresh is active. ThePCnet-ISA II controller uses this signal to mask inad-vertent DMA Acknowledge assertion during memoryrefresh periods. If DACK is asserted when REF isactive, DACK assertion is ignored. REF is monitored toeliminate a bus arbitration problem observed on someISA platforms.

RESETReset InputWhen RESET is asserted HIGH the PCnet-ISA II con-troller performs an internal system reset. RESET mustbe held for a minimum of 10 XTAL1 periods beforebeing deasserted. While in a reset state, the PCnet-ISAII controller will tristate or deassert all outputs to pre-defined reset levels. The PCnet-ISA II controller resetsitself upon power-up.

SA0-19System Address Bus Input/OutputThis bus contains address information, which is stableduring a bus operation, regardless of the source.SA17-19 contain the same values as the unlatchedaddress LA17-19. When the PCnet-ISA II controller isthe Current Master, SA0-19 will be driven actively.When the PCnet-ISA II controller is not the CurrentMaster, the SA0-19 lines are continuously monitored todetermine if an address match exists for I/O slavetransfers or Boot PROM accesses.

SBHESystem Byte High Enable Input/OutputThis signal indicates the high byte of the system databus is to be used. SBHE is driven by the PCnet-ISA IIcontroller when performing bus mastering operations.

SD0-15 System Data Bus Input/OutputThese pins are used to transfer data to and from thePCnet-ISA II controller to system resources via the ISAdata bus. SD0-15 is driven by the PCnet-ISA II control-

BABL Babble

RCVCCO Receive Collision Count Overflow

JAB Jabber

MISS Missed Frame

MERR Memory Error

MPCO Missed Packet Count Overflow

RINT Receive Interrupt

IDON Initialization Done

TXDATSTRT Transmit Start

Pin Number

Pin Function in Bus Master Mode

Pin Function in GPSI Mode

10 LA17 RXDAT

11 LA18 SRDCLK

12 LA19 RXCRS

13 LA20 CLSN

15 LA21 STDCLK

16 LA22 TXEN

17 LA23 TXDAT

Am79C961A 17


ler when performing bus master writes and slave readoperations. Likewise, the data on SD0-15 is latched bythe PCnet-ISA II controller when performing busmaster reads and slave write operations.

Board InterfaceIRQ12/FlashWE

Flash Write Enable OutputOptional interface to the Flash memory boot PROMWrite Enable.

IRQ15/APCSAddress PROM Chip Select OutputWhen programmed as APCS in Plug and Play RegisterF0, this signal is asserted when the external AddressPROM is read. When an I/O read operation isperformed on the first 16 bytes in the PCnet-ISA II con-troller’s I/O space, APCS is asserted. The outputs ofthe external Address PROM drive the PROM Data Bus.The PCnet-ISA II controller buffers the contents of thePROM data bus and drives them on the lower eight bitsof the System Data Bus.

When programmed to IRQ15 (default), this pin has thesame function as IRQ 3, 4, 5, 9, 10, 11, or 12.

BPCSBoot PROM Chip Select OutputThis signal is asserted when the Boot PROM is read. IfSA0-19 lines match a predefined address block andMEMR is active and REF inactive, the BPCS signal willbe asserted. The outputs of the external Boot PROMdrive the PROM Data Bus. The PCnet-ISA II controllerbuffers the contents of the PROM data bus and drivesthem on the lower eight bits of the System Data Bus.

DXCVR/EARDisable Transceiver/External Address Reject Input/Output

This pin can be used to disable external transceivercircuitry attached to the AUI interface when the internal10BASE-T port is active. The polarity of this pin is setby the DXCVRP bit (PnP register 0xF0, bit 5). WhenDXCVRP is cleared (default), the DXCVR pin is drivenHIGH when the Twisted Pair port is active or SLEEPmode has been entered and driven LOW when the AUIport is active. When DXCVRP is set, the DXCVR pin isdriven LOW when the Twisted Pair port is active orSLEEP mode has been entered and driven HIGH whenthe AUI port is active.

If EADI mode is selected, this pin becomes the EARinput.

The incoming frame will be checked against the inter-nally active address detection mechanisms and theresult of this check will be OR’d with the value on theEAR pin. The EAR pin is defined as REJECT. (See theEADI section for details regarding the function andtiming of this signal).

LEDO-3LED Drivers OutputThese pins sink 12 mA each for driving LEDs. Theirmeaning is software configurable (see section The ISABus Configuration Registers) and they are active LOW.

When EADI mode is selected, the pins named LED1,LED2, and LED3 change in function while LED0continues to indicate 10BASE-T Link Status.

PRDB3-7Private Data Bus Input/OutputThis is the data bus for the Boot PROM and theAddress PROM.

PRDB2/EEDOPrivate data bus bit 2/Data Out Input/OutputA multifunction pin which serves as PRDB2 of theprivate data bus and, when ISACSR3 bit 4 is set,changes to become DATA OUT from the EEPROM.

PRDB1/EEDIPrivate data bus bit 1/Data In Input/OutputA multifunction pin which serves as PRDB1 of theprivate data bus and, when ISACSR3 bit 4 is set,changes to become DATA In to the EEPROM.

PRDB0/EESKPrivate data bus bit 0/Serial Clock Input/OutputA multifunction pin which serves as PRDB0 of theprivate data bus and, when ISACSR3 bit 4 is set,changes to become Serial Clock to the EEPROM.

LED EADI Function

1 SF/BD

2 SRD

3 SRDCLK

18 Am79C961A


SHFBUSYShift Busy Input/OutputThis pin indicates that a read from the externalEEPROM is in progress. It is active only when data isbeing shifted out of the EEPROM due to a hardwareRESET or assertion of the EE_LOAD bit (ISACSR3, bit14). If this pin is left unconnected or pulled low with apull-down resistor, an EEPROM checksum error isforced. Normally, this pin should be connected to VCCthrough a 10K Ω pull-up resistor.

EECSEEPROM CHIP SELECT OutputThis signal is asserted when read or write accessesare being performed to the EEPROM. It is controlled byISACSR3. It is driven at Reset during EEPROM Read.

SLEEPSleep InputWhen SLEEP pin is asserted (active LOW), thePCnet-ISA II controller performs an internal systemreset and proceeds into a power savings mode. All

outputs will be placed in their normal reset condition.All PCnet-ISA II controller inputs will be ignored exceptfor the SLEEP pin itself. Deassertion of SLEEP resultsin the device waking up. The system must delay thestarting of the network controller by 0.5 seconds toallow internal analog circuits to stabilize.

XTAL1Crystal Connection InputThe internal clock generator uses a 20 MHz crystal thatis attached to pins XTAL1 and XTAL2. Alternatively, anexternal 20 MHz CMOS-compatible clock signal can beused to drive this pin. Refer to the section on ExternalCrystal Characteristics for more details.

XTAL2Crystal Connection OutputThe internal clock generator uses a 20 MHz crystal thatis attached to pins XTAL1 and XTAL2. If an externalclock is used, this pin should be left unconnected.

Am79C961A 19


Plug and Play ISA Card State Transitions

Notes:1. CSN = Card Select Number.

2. RESET_DRV causes a state transition from the current state to Wait for Key and sets all CSNs to zero. All logical devices are set to their power-up configuration values.

3. The Wait for Key command causes a state transition from the current state to Wait for Key.

Power upRESET_DRV

State Active Commands

Initiation Key

Set CSN = 0

Wait for Key no active commands


Sleep

ResetWait for KeyWake[CSN]


Isolation

ResetWait for KeySet RD_DATA PortSerial IsolationWake[CSN]


Config

ResetWait for KeyWake[CSN]Resource DataStatusLogical DeviceI/O Range CheckActivateConfiguration Registers

Set CSN

Lose serial location OR(WAKE <> CSN)

WAKE <> CSN

20 Am79C961A


BLOCK DIAGRAM: BUS SLAVE MODE

19364A-3

LED[0-3]

ISA BusInterface

Unit

RCVFIFO

XMTFIFO

FIFOControl

BufferManagement

Unit

EEPROMInterface

Unit

802.3MACCore

Encoder/Decoder(PLS) &AUI Port

10BASE-TMAU

PrivateBus

Control

JTAGPort

Control

AEN

IOCHRDY

IOR

IOWIRQ[3, 4, 5, 9,

10, 11, 12]IOCS16MEMR

MEMW

REF

RESET

SBHE

SD[0-15]

SA[0-15]

SLEEP

SHFBUSYEEDOEEDI

EESKEECS

DXCVR/EAR

CI+/-

DI+/-

XTAL1

XTAL2

DO+/-

RXD+/-

TXD+/-

TXPD+/-

TDO

TMS

TDI

TCK

SMA

IRQ15/APCSBPCS

PRAB[0-15]PRDB[0-7]SROESRWE

SMAMBPAM

DVDD[1-7]

DVSS[1-13]

AVDD[1-4]

AVSS[1-2]

Am79C961A 21


CONNECTION DIAGRAMS: BUS SLAVE MODE

19364A-4

132

1

DV

DD

2T

CK

131

TM

S13

0T

DO

129

TD

I12

8E

EC

S12

7B

PC

S12

6S

HF

BU

SY

125

PR

DB

0/E

ES

K12

4P

RD

B1/

EE

DI

123

PR

DB

2/E

ED

O12

2P

RD

B3

121

DV

SS

212

0P

RD

B4

119

PR

DB

511

8P

RD

B6

117

PR

DB

711

6D

VD

D1

115

LED

011

4LE

D1

113

DV

SS

111

2LE

D2

111

LED

311

0D

XC

VR

/EA

R10

9A

VD

D2

108

CI+

107

CI–

106

DI+

105

DI–

104

AV

DD

110

3D

O+

102

DO

–10

1A

VS

S1

100

XTAL299AVSS298XTAL197AVDD396TXD+95TXPD+94TXD–93TXPD–92AVDD491RXD+90RXD–89DVSS1388SD1587SD786SD1485SD684DVSS983SD1382SD581SD1280SD479DVDD778SD1177SD376SD1075SD274DVSS873SD972SD171SD870SD069SLEEP68DVDD667

34D

VD

D4

35P

RA

B12

36P

RA

B13

37P

RA

B14

38P

RA

B15

39S

A13

40S

A14

41S

A15

42S

RW

E43

AE

N44

IOC

HR

DY

45M

EM

W46

ME

MR

47D

VS

S11

48A

PC

S/IR

Q15

49S

RC

S/IR

Q12

50IR

Q11

51D

VD

D5

52IR

Q10

53IO

CS

1654

BP

AM

55IR

Q3

56IR

Q4

57IR

Q5

58 59D

VS

S12

60S

RO

E61

SM

AM

62IO

R63

IOW

64IR

Q9

65R

ES

ET

66

DVSS32SMA3SA04SA15SA26DVSS107SA38SA49SA510SA611SA712SA813SA914DVSS415SA1016SA11 17SA1218SBHE19DVDD320PRAB021PRAB122PRAB223DVSS524PRAB325PRAB426PRAB527PRAB628PRAB729PRAB830PRAB931DVSS632PRAB1033PRAB11

Top Side View

RE

F

DV

SS

7

22 Am79C961A


PIN DESIGNATIONS: BUS SLAVE MODE

Listed by Pin NumberPin # Name Pin # Name Pin # Name

1 DVSS3

SMA

SA0

SA1

SA2

DVSS10

SA3

SA4

SA5

SA6

SA7

SA8

45 IOCHRDY 89 RXD-

RXD+

AVDD4

TXPD-

TXD-

TXPD+

TXD+

AVDD3

XTAL1

AVSS2

XTAL2

AVSS1

DO-

DO+

AVDD1

DI-

DI+

CI-

CI+

AVDD2

DXCVR/EAR

LED3

LED2

DVSS1

LED1

LED0

2 46 MEMW 90

3 47 MEMR 91

4 48 DVSS11 92

5 49 IRQ15 93

6 50 IRQ12 94

7 51 IRQ11 95

8 52 DVDD5 96

9 53 IRQ10 97

10 54 IOCS16 98

11 55 BPAM 99

12 56 IRQ3 100

13 SA9

DVSS4

SA10

SA11

SA12

SBHE

DVDD3

PRAB0

PRAB1

PRAB2

DVSS5

PRAB3

PRAB4

PRAB5

PRAB6

PRAB7

PRAB8

PRAB9

DVSS6

PRAB10

PRAB11

DVDD4

PRAB12

PRAB13

57 IRQ4 101

14 58 IRQ5 102

15 59 REF 103

16 60 DVSS12 104

17 61 SROE 105

18 62 SMAM 106

19 63 IOR 107

20 64 IOW 108

21 65 IRQ9 109

22 66 RESET 110

23 67 DVDD6 111

24 68 SLEEP 112

25 69 SD0 113

26 70 SD8 114

27 71 SD1 115 DVDD1

PRDB7

PRDB6

PRDB5

PRDB4

DVSS2

PRDB3

PRDB2/EEDO

PRDB1/EEDI

PRDB0/EESK

SHFBUSY

BPCS

EECS

TDI

TDO

TMS

TCK

DVDD2

28 72 SD9 116

29 73 DVSS8 117

30 74 SD2 118

31 75 SD10 119

32 76 SD3 120

33 77 SD11 121

34 78 DVDD7 122

35 79 SD4 123

36 80 SD12 124

37 PRAB14

PRAB15

DVSS7

SA13

SA14

SA15

SRWE

AEN

81 SD5 125

38 82 SD13 126

39 83 DVSS9 127

40 84 SD6 128

41 85 SD14 129

42 86 SD7 130

43 87 SD15 131

44 88 DVSS13 132

Am79C961A 23



Listed by Pin Name

Name Pin# Name Pin# Name Pin#

AEN

AVDD1

AVDD2

AVDD3

AVDD4

AVSS1

AVSS2

BPAM

BPCS

CI-

CI+

DI-

DI+

DO-

DO+

DVDD1

DVDD2

DVDD3

DVDD4

DVDD5

DVDD6

DVDD7

DVSS1

DVSS10

DVSS11

DVSS12

44 IRQ15 49 SA13

SA14

SA15

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SBHE

SD0

SD1

SD10

SD11

SD12

SD13

SD14

SD15

SD2

SD3

SD4

40

103 IRQ3 56 41

108 IRQ4 57 42

96 IRQ5 58 5

91 IRQ9 65 7

100 LED0 114 8

98 LED1 113 9

55 LED2 111 10

126 LED3 110 11

106 MEMR 47 12

107 MEMW 46 13

104 PRAB0 20 18

105 PRAB1 21 69

101 PRAB10 32 71

102 PRAB11 33 75

115 PRAB12 35 77

132 PRAB13 36 80

19 PRAB14 37 82

34 PRAB15 38 85

52 PRAB2 22 87

67 PRAB3 24 74

78 PRAB4 25 76

112 PRAB5 26 79

6 PRAB6 27 SD5

SD6

SD7

SD8

SD9

SHFBUSY

SLEEP

SMA

SMAM

SROE

SRWE

TCK

TDI

TDO

TMS

TXD-

TXD+

TXPD-

TXPD+

XTAL1

XTAL2

81

48 PRAB7 28 84

60 PRAB8 29 86

DVSS13

DVSS2

DVSS3

DVSS4

DVSS5

DVSS6

DVSS7

DVSS8

DVSS9

DXCVR/EAR

EECS

IOCHRDY

IOCS16

IOR

IOW

IRQ10

IRQ11

IRQ12

88 PRAB9 30 70

120 PRDB0/DO 124 72

1 PRDB0/D1 123 125

14 PRDB0/SCLK 122 68

23 PRDB3 121 2

31 PRDB4 119 62

39 PRDB5 118 61

73 PRDB6 117 43

83 PRDB7 116 131

109 REF 59 128

127 RESET 66 129

45 RXD- 89 130

54 RXD+ 90 93

63 SA0 3 95

64 SA1 4 92

53 SA10 15 94

51 SA11 16 97

50 SA12 17 99

24 Am79C961A



Listed by Group


ISA Bus Interface

AEN Address Enable I

IOCHRDY I/O Channel Ready O OD3

IOCS16 I/O Chip Select 16 O OD3

IOR I/O Read Select I

IOW I/O Write Select I

IRQ[3, 4, 5, 9, 10, 11, 12, 15] Interrupt Request O TS3/OD3

MEMR Memory Read Select I

MEMW Memory Write Select I

REF Memory Refresh Active I

RESET System Reset I

SA[0–15] System Address Bus I

SBHE System Byte High Enable I

SD[0–15] System Data Bus I/O TS3

Board Interfaces

IRQ15/APCS IRQ15 or Address PROM Chip Select O TS1

BPCS Boot PROM Chip Select O TS1

BPAM Boot PROM Address Match I

DXCVR/EAR Disable Transceiver I/O TS1

LED0 LED0/LNKST O TS2

LED1 LED1/SFBD/RCVACT O TS2

LED2 LED2/SRD/RXDATD01 O TS2

LED3 LED3/SRDCLK/XMTACT O TS2

PRAB[0–15] PRivate Address Bus I/O TS3

PRDB[3–7] PRivate Data Bus I/O TS1

SLEEP Sleep Mode I

SMA Slave Mode Architecture I

SMAM Shared Memory Address Match I

SROE Static RAM Output Enable O TS3

SRWE Static RAM Write Enable O TS1

XTAL1 Crystal Oscillator Input I

XTAL2 Crystal Oscillator OUTPUT O

SHFBUSY Read access from EEPROM in process O

PRDB(0)/EESK Serial Shift Clock I/O

PRDB(1)/EEDI Serial Shift Data In I/O

PRDB(2)/EEDO Serial Shift Data Out I/O

EECS EEPROM Chip Select O

Am79C961A 25



Listed by Group

Output Driver Types



CI±DI±DO±

Collision Inputs

Receive Data

Transmit Data

I

I

O

Twisted Pair Transceiver Interface (10BASE-T)

RXD±TXD±TXPD±

10BASE-T Receive Data

10BASE-T Transmit Data

10BASE-T Predistortion Control

I

O

O

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK

TDI

TDO

TMS

Test Clock

Test Data Input

Test Data Output

Test Mode Select

I

I

O

I

TS2

Power Supplies

AVDD

AVSS

DVDD

DVSS

Analog Power [1-4]

Analog Ground [1-2]

Digital Power [1-7]

Digital Ground [1-13]

Name Type IOL (mA) IOH (mA) pF




OD3 Open Drain 24 –3 120

26 Am79C961A


PIN DESCRIPTION: BUS SLAVE MODE

ISA InterfaceAEN

Address Enable InputThis signal must be driven LOW when the bus performsan I/O access to the device.

IOCHRDYI/O Channel Ready OutputWhen the PCnet-ISA II controller is being accessed, aHIGH on IOCHRDY indicates that valid data exists onthe data bus for reads and that data has been latchedfor writes.

IOCS16I/O Chip Select 16 Input/OutputWhen an I/O read or write operation is performed, thePCnet-ISA II controller will drive this pin LOW to indi-cate that the chip supports a 16-bit operation at thisaddress. (If the motherboard does not receive thissignal, then the motherboard will convert a 16-bitaccess to two 8-bit accesses).

The PCnet-ISA II controller follows the IEEE P996 spec-ification that recommends this function be implementedas a pure decode of SA0-9 and AEN, with no depen-dency on IOR, or IOW; however, some PC/AT clonesystems are not compatible with this approach. For thisreason, the PCnet-ISA II controller is recommended tobe configured to run 8-bit I/O on all machines. Sincedata is moved by memory cycles there is virtually noperformance loss incurred by running 8-bit I/O andcompatibility problems are virtually eliminated. ThePCnet-ISA II controller can be configured to run8-bit-only I/O by clearing Bit 0 in Plug and Play RegisterF0.

IORI/O Read InputTo perform an Input/Output Read operation on thedevice IOR must be asserted. IOR is only valid if theAEN signal is LOW and the external address matchesthe PCnet-ISA II controller’s predefined I/O addresslocation. If valid, IOR indicates that a slave read opera-tion is to be performed.

IOWI/O Write InputTo perform an Input/Output write operation on thedevice IOW must be asserted. IOW is only valid if AENsignal is LOW and the external address matches thePCnet-ISA II controller’s predefined I/O address loca-tion. If valid, IOW indicates that a slave write operationis to be performed.

IRQ3, 4, 5, 9, 10, 11, 12, 15Interrupt Request OutputAn attention signal which indicates that one or more ofthe following status flags is set: BABL, MISS, MERR,RINT, IDON or TXSTRT. All status flags have a mask bitwhich allows for suppression of IRQ assertion. Theseflags have the following meaning:

MEMRMemory Read InputMEMR goes LOW to perform a memory readoperation.

MEMWMemory Write InputMEMW goes LOW to perform a memory write opera-tion.

REFMemory Refresh InputWhen REF is asserted, a memory refresh cycle is inprogress. During a refresh cycle, MEMR assertionis ignored.

RESETReset InputWhen RESET is asserted HIGH, the PCnet-ISA IIcontroller performs an internal system reset. RESETmust be held for a minimum of 10 XTAL1 periods beforebeing deasserted. While in a reset state, the PCnet-ISAII controller will tristate or deassert all outputs topredefined reset levels. The PCnet-ISA II controllerresets itself upon power-up.

SA0-15System Address Bus InputThis bus carries the address inputs from the systemaddress bus. Address data is stable during commandactive cycle.

BABL Babble

RCVCCO Receive Collision Count Overflow

JAB Jabber

MISS Missed Frame

MERR Memory Error

MPCO Missed Packet Count Overflow

RINT Receive Interrupt

IDON Initialization Done

TXSTRT Transmit Start

Am79C961A 27


SBHESystem Bus High Enable InputThis signal indicates the HIGH byte of the system databus is to be used. There is a weak pull-up resistor onthis pin. If the PCnet-ISA II controller is installed in an8-bit only system like the PC/XT, SBHE will always beHIGH and the PCnet-ISA II controller will perform only8-bit operations. There must be at least one LOW goingedge on this signal before the PCnet-ISA II controllerwill perform 16-bit operations.

SD0-15 System Data Bus Input/OutputThis bus is used to transfer data to and from thePCnet-ISA II controller to system resources via the ISAdata bus. SD0-15 is driven by the PCnet-ISA IIcontroller when performing slave read operations.

Likewise, the data on SD0-15 is latched by thePCnet-ISA II controller when performing slave writeoperations.

Board Interface

APCS/IRQ15Address PROM Chip Select OutputThis signal is asserted when the external AddressPROM is read. When an I/O read operation is per-formed on the first 16 bytes in the PCnet-ISA IIcontroller’s I/O space, APCS is asserted. The outputsof the external Address PROM drive the PROM DataBus. The PCnet-ISA II controller buffers the contents ofthe PROM data bus and drives them on the lower eightbits of the System Data Bus. IOCS16 is not assertedduring this cycle.

BPAMBoot PROM Address Match InputThis pin indicates a Boot PROM access cycle. If noBoot PROM is installed, this pin has a default value ofHIGH and thus may be left connected to VDD.

BPCSBoot PROM Chip Select OutputThis signal is asserted when the Boot PROM is read. IfBPAM is active and MEMR is active, the BPCS signalwill be asserted. The outputs of the external BootPROM drive the PROM Data Bus. The PCnet-ISA IIcontroller buffers the contents of the PROM data busand drives them on the System Data Bus. IOCS16 isnot asserted during this cycle. If 16-bit cycles areperformed, it is the responsibility of external logic toassert MEMCS16 signal.

DXCVR/EARDisable Transceiver/External Address Reject Input/OutputThis pin disables the transceiver. The DXCVR output isconfigured in the initialization sequence. A high levelindicates the Twisted Pair Interface is active and theAUI is inactive, or SLEEP mode has been entered. Alow level indicates the AUI is active and the Twisted Pairinterface is inactive.

If EADI mode is selected, this pin becomes the EARinput.

The incoming frame will be checked against the inter-nally active address detection mechanisms and theresult of this check will be OR’d with the value on theEAR pin. The EAR pin is defined as REJECT. (See theEADI section for details regarding the function and tim-ing of this signal).

LED0-3LED Drivers OutputThese pins sink 12 mA each for driving LEDs. Theirmeaning is software configurable (see section The ISABus Configuration Registers) and they are active LOW.

When EADI mode is selected, the pins named LED1,LED2, and LED3 change in function while LED0continues to indicate 10BASE-T Link Status. TheDXCVR input becomes the EAR input.

PRAB0-15Private Address Bus Input/OutputThe Private Address Bus is the address bus used todrive the Address PROM, Remote Boot PROM, andSRAM. PRAB10-15 are required to be buffered by aBus Buffer with ABOE as its control and SA10-15 as itsinputs.

PRDB3-7Private Data Bus Input/OutputThis is the data bus for the static RAM, the Boot PROM,and the Address PROM.

PRDB2/EEDOPrivate Data Bus Bit 2/Data Out Input/OutputA multifunction pin which serves as PRDB2 of theprivate data bus and, when ISACSR3 bit 4 is set,changes to become DATA OUT from the EEPROM.

LED EADI Function

1 SF/BD

2 SRD

3 SRDCLK

28 Am79C961A


PRDB1/EEDIPrivate Data Bus Bit 1/Data In Input/OutputA multifunction pin which serves as PRDB1 of theprivate data bus and, when ISACSR3 bit 4 is set,changes to become DATA In to the EEPROM.

PRDB0/EESKPrivate Data Bus Bit 0/Serial Clock Input/OutputA multifunction pin which serves as PRDB0 of theprivate data bus and, when ISACSR3 bit 4 is set,changes to become Serial Clock to the EEPROM.

SHFBUSYShift Busy Input/OutputThis pin indicates that a read from the externalEEPROM is in progress. It is active only when data isbeing shifted out of the EEPROM due to a hardwareRESET or assertion of the EE_LOAD bit (ISACSR3, bit14). If this pin is left unconnected or pulled low with apull-down resistor, an EEPROM checksum error isforced. Normally, this pin should be connected to VCCthrough a 10K Ω pull-up resistor.

EECSEEPROM CHIP SELECT OutputThis signal is asserted when read or write accessesare being performed to the EEPROM. It is controlled byISACSR3. It is driven at Reset during EEPROM Read.

SLEEPSleep InputWhen SLEEP input is asserted (active LOW), thePCnet-ISA II controller performs an internal systemreset and proceeds into a power savings mode. All out-puts will be placed in their normal reset condition. AllPCnet-ISA II controller inputs will be ignored except forthe SLEEP pin itself. Deassertion of SLEEP results inthe device waking up. The system must delay thestarting of the network controller by 0.5 seconds toallow internal analog circuits to stabilize.

SMASlave Mode Architecture InputThis pin must be permanently pulled LOW for operationin the Bus Slave mode. It is sampled after the hardwareRESET sequence. In the Bus Slave mode, thePCnet-ISA II can be programmed for Shared Memory

access or Programmed I/O access through thePIOSEL bit (ISACSR2, bit 13).

SMAMShared Memory Address Match InputWhen the Shared Memory architecture is selected(ISACSR2, bit 13), this pin is an input that indicates anaccess to shared memory when asserted. The type ofaccess is decided by MEMR or MEMW.

When the Programmed I/O architecture is selected,this pin should be permanently tied HIGH.

SROEStatic RAM Output Enable OutputThis pin directly controls the external SRAM’s OE pin.

SRCS/IRQ12Static RAM Chip Select OutputThis pin directly controls the external SRAM’s chipselect (CS) pin when the Flash boot ROM option isselected.

When Flash boot ROM option is not selected, this pinbecomes IRQ12.

SRWE/WEStatic RAM Write Enable/Write Enable OutputThis pin (SRWE) directly controls the external SRAM’sWE pin when a F lash memor y dev ice is notimplemented.

When a Flash memory device is implemented, this pinbecomes a global write enable (WE) pin.

XTAL1Crystal Connection InputThe internal clock generator uses a 20 MHz crystal thatis attached to pins XTAL1 and XTAL2. Alternatively, anexternal 20 MHz CMOS-compatible clock signal can beused to drive this pin. Refer to the section on ExternalCrystal Characteristics for more details.

XTAL2Crystal Connection OutputThe internal clock generator uses a 20 MHz crystal thatis attached to pins XTAL1 and XTAL2. If an externalclock is used, this pin should be left unconnected.

Am79C961A 29


PIN DESCRIPTION:NETWORK INTERFACES

AUI

CI+, CI–Control Input InputThis is a differential input pair used to detect Collision(Signal Quality Error Signal).

DI+, DI–Data In InputThis is a differential receive data input pair to thePCnet-ISA II controller.

DO+, DO–Data Out OutputThis is a differential transmit data output pair from thePCnet-ISA II controller.

Twisted Pair Interface

RXD+, RXD–Receive Data InputThis is the 10BASE-T port differential receive inputpair.

TXD+, TXD–Transmit Data OutputThese are the 10BASE-T port differential transmitdrivers.

TXP+, TXP–Transmit Predistortion Control OutputThese are 10BASE-T transmit waveform pre-distortioncontrol differential outputs.

PIN DESCRIPTION:IEEE 1149.1 (JTAG) TEST ACCESS PORT

TCKTest Clock InputThis is the clock input for the boundary scan test modeoperation. TCK can operate up to 10 MHz. TCK doesnot have an internal pull-up resistor and must be con-nected to a valid TTL level of high or low. TCK must notbe left unconnected.

TDITest Data Input InputThis is the test data input path to the PCnet-ISA II con-troller. If left unconnected, this pin has a default valueof HIGH.

TDOTest Data Output OutputThis is the test data output path from the PCnet-ISA IIcontroller. TDO is tri-stated when JTAG port is inactive.

TMSTest Mode Select InputThis is a serial input bit stream used to define the spe-cific boundary scan test to be executed. If left uncon-nected, this pin has a default value of HIGH.

PIN DESCRIPTION:

POWER SUPPLIESAll power pins with a “D” prefix are digital pins con-nected to the digital circuitry and digital I/O buffers. Allpower pins with an “A” prefix are analog power pinsconnected to the analog circuitry. Not all analog pinsare quiet and special precaution must be taken whendoing board layout. Some analog pins are more noisythan others and must be separated from the otheranalog pins.

AVDD1–4Analog Power (4 Pins) PowerSupplies power to analog portions of the PCnet-ISA IIcontroller. Special attention should be paid to theprinted circuit board layout to avoid excessive noise onthese lines.

AVSS1–2Analog Ground (2 Pins) PowerSupplies ground reference to analog portions ofPCnet-ISA II controller. Special attention should bepaid to the printed circuit board layout to avoid exces-sive noise on these lines.

DVDD1–7Digital Power (7 Pins) PowerSupplies power to digital portions of PCnet-ISA II con-troller. Four pins are used by Input/Output buffer driversand two are used by the internal digital circuitry.

DVSS1–13Digital Ground (13 Pins) PowerSupplies ground reference to digital portions ofPCnet-ISA II controller. Ten pins are used by Input/Out-put buffer drivers and two are used by the internaldigital circuitry.

30 Am79C961A


CONNECTION DIAGRAM

123456789101112131415161718192021222324252627282930313233343536

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108107106105104103102101100

999897969594939291908988878685848382818079787776757473

TQFP 144

Am79C961AVC

Am79C961A 31


PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144)



1 NC 37 NC 73 NC 109 NC


3 MASTER 39 SA12 75 SLEEP 111 DO–

4 DRQ7 40 SA13 76 SD0 112 DO+

5 DRQ6 41 SA14 77 SD8 113 AVDD1

6 DRQ5 42 SA15 78 SD1 114 DI–

7 DVSS10 43 DVSS7 79 SD9 115 DI+

8 DACK7 44 SA16 80 DVSS8 116 CI–

9 DACK6 45 SA17 81 SD2 117 CI+

10 DACK5 46 SA18 82 SD10 118 AVDD2

11 LA17 47 SA19 83 SD3 119 DXCVR/EAR

12 LA18 48 AEN 84 SD11 120 LED3

13 LA19 49 IOCHRDY 85 DVDD7 121 LED2

14 LA20 50 MEMW 86 SD4 122 DVSS1

15 DVSS4 51 MEMR 87 SD12 123 LED1

16 LA21 52 DVSS11 88 SD5 124 LED0

17 SA22 53 IRQ15/APCS 89 SD13 125 DVDD1

18 SA23 54 IRQ12/FlashWE 90 DVSS9 126 PRDB7

19 SBHE 55 IRQ11 91 SD6 127 PRDB6


21 SA0 57 IRQ10 93 SD7 129 PRDB4

22 SA1 58 IOCS16 94 SD15 130 DVSS2

23 SA2 59 BALE 95 DVSS13 131 PRDB3

24 DVSS5 60 IRQ3 96 RXD– 132 PRDB2/EEDO

25 SA3 61 IRQ4 97 RXD+ 133 PRDB1/EEDI

26 SA4 62 IRQ5 98 AVDD4 134 PRDB0/EESK

27 SA5 63 REF 99 TXPD– 135 SHFBUSY

28 SA6 64 DVSS12 100 TXD– 136 BPCS

29 SA7 65 DRQ3 101 TXPD+ 137 EECS

30 SA8 66 DACK3 102 TXD+ 138 TDI

31 SA9 67 IOR 103 AVDD3 139 TDO


33 SA10 69 IRQ9 105 AVSS2 141 TCK

34 SA11 70 RESET 106 XTAL2 142 DVDD2

35 NC 71 NC 107 NC 143 NC

36 NC 72 NC 108 NC 144 NC

32 Am79C961A


PIN DESIGNATIONS: BUS MASTER MODE (TQFP 144)

Listed by Pin Name


AEN 48 DVSS3 2 NC 37 SA3 25

AVDD1 113 DVSS4 15 NC 71 SA4 26

AVDD2 118 DVSS5 24 NC 72 SA5 27

AVDD3 103 DVSS6 32 NC 73 SA6 28

AVDD4 98 DVSS7 43 NC 107 SA7 29

AVSS1 110 DVSS8 80 NC 108 SA8 30

AVSS2 105 DVSS9 90 NC 109 SA9 31

BALE 59 DXCVR/EAR 119 NC 143 SBHE 19

BPCS 136 EECS 137 NC 144 SD0 76

CI+ 117 IOCHRDY 49 PRDB0/EESK 134 SD1 78

CI– 116 IOCS16 58 PRDB1/EEDI 133 SD10 82

DACK3 66 IOR 67 PRDB2/EEDO 132 SD11 84

DACK5 10 IOW 68 PRDB3 131 SD12 87

DACK6 9 IRQ10 57 PRDB4 129 SD13 89

DACK7 8 IRQ11 55 PRDB5 128 SD14 92

DI+ 115 IRQ12/FlashWE 54 PRDB6 127 SD15 94

DI– 114 IRQ15/APCS 53 PRDB7 126 SD2 81

DO+ 112 IRQ3 60 REF 63 SD3 83

DO– 111 IRQ4 61 RESET 70 SD4 86

DRQ3 65 IRQ5 62 RXD+ 97 SD5 88

DRQ5 6 IRQ9 69 RXD– 96 SD6 91

DRQ6 5 LA17 11 SA0 21 SD7 93

DRQ7 4 LA18 12 SA1 22 SD8 77

DVDD1 125 LA19 13 SA10 33 SD9 79

DVDD2 142 LA20 14 SA11 34 SHFBUSY 135

DVDD3 20 LA21 16 SA12 39 SLEEP 75

DVDD4 38 LED0 124 SA13 40 TCK 141

DVDD5 56 LED1 123 SA14 41 TDI 138

DVDD6 74 LED2 121 SA15 42 TDO 139

DVDD7 85 LED3 120 SA16 44 TMS 140

DVSS1 122 MASTER 3 SA17 45 TXD+ 102

DVSS10 7 MEMR 51 SA18 46 TXD– 100

DVSS11 52 MEMW 50 SA19 47 TXPD+ 101

DVSS12 64 NC 1 SA2 23 TXPD– 99

DVSS13 95 NC 35 SA22 17 XTAL1 104

DVSS2 130 NC 36 SA23 18 XTAL2 106

Am79C961A 33


PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144)Listed by Pin Number


1 NC 37 NC 73 NC 109 NC


3 SMA 39 PRAB12 75 SLEEP 111 DO-

4 SA0 40 PRAB13 76 SD0 112 DO+

5 SA1 41 PRAB14 77 SD8 113 AVDD1

6 SA2 42 PRAB15 78 SD1 114 DI-

7 DVSS10 43 DVSS7 79 SD9 115 DI+

8 SA3 44 SA13 80 DVSS8 116 CI-

9 SA4 45 SA14 81 SD2 117 CI+

10 SA5 46 SA15 82 SD10 118 AVDD2

11 SA6 47 SRWE 83 SD3 119 DXCVR/EAR

12 SA7 48 AEN 84 SD11 120 LED3

13 SA8 49 IOCHRDY 85 DVDD7 121 LED2

14 SA9 50 MEMW 86 SD4 122 DVSS1

15 DVSS4 51 MEMR 87 SD12 123 LED1

16 SA10 52 DVSS11 88 SD5 124 LED0

17 SA11 53 IRQ15 89 SD13 125 DVDD1

18 SA12 54 IRQ12 90 DVSS9 126 PRDB7

19 SBHE 55 IRQ11 91 SD6 127 PRDB6


21 PRAB0 57 IRQ10 93 SD7 129 PRDB4

22 PRAB1 58 IOCS16 94 SD15 130 DVSS2

23 PRAB2 59 BPAM 95 DVSS13 131 PRDB3

24 DVSS5 60 IRQ3 96 RXD- 132PRDB2/EEDO

25 PRAB3 61 IRQ4 97 RXD+ 133 PRDB1/EEDI

26 PRAB4 62 IRQ5 98 AVDD4 134 PRDB0/EESK

27 PRAB5 63 REF 99 TXPD- 135 SHFBUSY

28 PRAB6 64 DVSS12 100 TXD- 136 BPCS

29 PRAB7 65 SROE 101 TXPD+ 137 EECS

30 PRAB8 66 SMAM 102 TXD+ 138 TDI

31 PRAB9 67 IOR 103 AVDD3 139 TDO


33 PRAB10 69 IRQ9 105 AVSS2 141 TCK

34 PRAB11 70 RESET 106 XTAL2 142 DVDD2

35 NC 71 PCMCIA_MODE 107 NC 143 NC

36 NC 72 NC 108 NC 144 NC

34 Am79C961A


PIN DESIGNATIONS: BUS SLAVE (PIO AND SHARED MEMORY) MODES (TQFP 144)

Listed by Pin Name


AEN 48 EECS 137 PRAB13 40 SA7 12

AVDD1 113 IOCHRDY 49 PRAB14 41 SA8 13

AVDD2 118 IOCS16 58 PRAB15 42 SA9 14

AVDD3 103 IOR 67 PRAB2 23 SBHE 19

AVDD4 98 IOW 68 PRAB3 25 SD0 76

AVSS1 110 IRQ10 57 PRAB4 26 SD1 78

AVSS2 105 IRQ11 55 PRAB5 27 SD10 82

BPAM 59 IRQ12 54 PRAB6 28 SD11 84

BPCS 136 IRQ15 53 PRAB7 29 SD12 87

CI+ 117 IRQ3 60 PRAB8 30 SD13 89

CI– 116 IRQ4 61 PRAB9 31 SD14 92

DI+ 115 IRQ5 62 PRDB0/EESK 134 SD15 94

DI– 114 IRQ9 69 PRDB1/EEDI 133 SD2 81

DO+ 112 LED0 124 PRDB2/EEDO 132 SD3 83

DO– 111 LED1 123 PRDB3 131 SD4 86

DVDD1 125 LED2 121 PRDB4 129 SD5 88

DVDD2 142 LED3 120 PRDB5 128 SD6 91

DVDD3 20 MEMR 51 PRDB6 127 SD7 93

DVDD4 38 MEMW 50 PRDB7 126 SD8 77

DVDD5 56 NC 1 REF 63 SD9 79

DVDD6 74 NC 35 RESET 70 SHFBUSY 135

DVDD7 85 NC 36 RXD+ 97 SLEEP 75

DVSS1 122 NC 37 RXD– 96 SMAM 66

DVSS10 7 NC 72 SA0 4 SMA 3

DVSS11 52 NC 73 SA1 5 SROE 65

DVSS12 64 NC 107 SA10 16 SRWE 47

DVSS13 95 NC 108 SA11 17 TCK 141

DVSS2 130 NC 109 SA12 18 TDI 138

DVSS3 2 NC 143 SA13 44 TDO 139

DVSS4 15 NC 144 SA14 45 TMS 140

DVSS5 24 PCMCIA_MODE 71 SA15 46 TXD+ 102

DVSS6 32 PRAB0 21 SA2 6 TXD– 100

DVSS7 43 PRAB1 22 SA3 8 TXPD+ 101

DVSS8 80 PRAB10 33 SA4 9 TXPD– 99

DVSS9 90 PRAB11 34 SA5 10 XTAL1 104

DXCVR/EAR 119 PRAB12 39 SA6 11 XTAL2 106

Am79C961A 35


FUNCTIONAL DESCRIPTIONThe PCnet-ISA II controller is a highly integrated systemsolution for the PC-AT ISA architecture. It provides a FullDuplex Ethernet controller, AUI port, and 10BASE-Ttransceiver. The PCnet-ISA II controller can be directly in-terfaced to an ISA system bus. The PCnet-ISA II control-ler contains an ISA bus interface unit, DMA BufferManagement Unit, 802.3 Media Access Control function,separate 136-byte transmit and 128-byte receive FIFOs,IEEE defined Attachment Unit Interface (AUI), andTwisted-Pair Transceiver Media Attachment Unit. In addi-tion, a Sleep function has been incorporated which pro-vides low standby current for power sensitive applications.

The PCnet-ISA II controller is register compatible withthe LANCE (Am7990) Ethernet control ler andPCnet-ISA (Am79C960). The DMA Buffer ManagementUnit supports the LANCE descriptor software modeland the PCnet-ISA II controller is software compatiblewith the Novell NE2100 and NE1500T add-in cards.

External remote boot PROMs and Ethernet physicaladdress PROMs are supported. The location of the I/Oregisters, Ethernet address PROM, and the boot PROMare determined by the programming of the registers in-ternal to PCnet-ISA II. These registers are loaded atRESET from the EEPROM, if an EEPROM is utilized.

Normally, the Ethernet physical address will be stored inthe EEPROM with the other configuration data. Thisreduces the parts count, board space requirements,and power consumption. The option to use a standardparallel 8 bit PROM is provided to manufactures whoare concerned about the non-volatile nature ofEEPROMs.

The PCnet-ISA II controller’s bus master architecturebrings to system manufacturers (adapter card andmotherboard makers alike) something they have notbeen able to enjoy with other architectures—a low-costsystem solution that provides the lowest parts countand highest performance. As a bus-mastering device,costly and power-hungry external SRAMs are notneeded for packet buffering. This results in lower sys-tem cost due to fewer components, less real-estate andless power. The PCnet-ISA II controller’s advanced busmastering architecture also provides high data through-put and low CPU utilization for even better performance.

To offer greater flexibility, the PCnet-ISA II controller hasa Bus Slave mode to meet varying application needs.The bus slave mode utilizes a local SRAM memory tostore the descriptors and buffers that are located in sys-tem memory when in Bus Master mode. The SRAM canbe slave accessed on the ISA bus through memorycycles in Shared Memory mode or I/O cycles in Pro-grammed I/O mode. The Shared Memory and Pro-grammed I/O architectures offer maximum compatibilitywith low-end machines, such as PC/XTs that do notsupport bus mastering, and very high end machines

which require local packet buffering for increasedsystem latency.

The network interface provides an Attachment UnitInterface and Twisted-Pair Transceiver functions. Onlyone interface is active at any particular time. The AUIallows for connection via isolation transformer to10BASE5 and 10BASE2, thick and thin based coaxialcables. The Twisted-Pair Transceiver interface allowsfor connection of unshielded twisted-pair cables asspecified by the Section 14 supplement to IEEE 802.3Standard (Type 10BASE-T).

Important Note About The EEPROM Byte MapThe user is cautioned that while the Am79C961A(PCnet-ISA II) and its associated EEPROM are pin com-patible to their predecessors the Am79C961 (PCnet-ISA+)and its associated EEPROM, the byte map structure ineach of the EEPROMs are different from each other.

The EEPROM byte map structure used for theAm79C961A PCnet-ISA II has the addition of “MISC Con-fig 2, ISACSR9" at word location 10Hex. The EEPROMbyte map structure used for the Am79C961 PCnet-ISA+does not have this.

Therefore, should the user intend to replace thePCnet-ISA+ with the PCnet-ISA II, care MUST be taken toreprogram the EEPROM to reflect the new byte mapstructure needed and used by the PCnet-ISA II. For addi-tional information, refer to the section in this data sheetunder EEPROM and the Am79C961 PCnet-ISA+ datasheet (PID #18183) under the sections entitled EEPROMand Serial EEPROM Byte Map.

Bus Master ModeSystem Interface

The PCnet-ISA II controller has two fundamental oper-ating modes, Bus Master and Bus Slave. Within the BusSlave mode, the PCnet-ISA II can be programmed for aShared Memory or Programmed I/O architecture. Theselection of either the Bus Master mode or the BusSlave mode must be done through hard wiring; it is notsoftware configurable. When in the Bus Slave mode, theselection of the Shared Memory or Programmed I/Oarchitecture is done through software with the PIOSELbit (ISACSR2, bit 13).

The optional Boot PROM is in memory address spaceand is expected to be 8–64K. On-chip address compar-ators control device selection is based on the value inthe EEPROM.

The address PROM, board configuration registers, andthe Ethernet controller occupy 24 bytes of I/O spaceand can be located on 16 different starting addresses.

36 Am79C961A


19364A-5

EECS

ISABus

16-Bit System Data

24-Bit SystemAddress

PCnet-ISA IIController

BootPROM

(Optional)

SD[0-15]

SA[0-19]LA[17-23]

BPCS CE OE

D[0-7]

A[0-15]

DODISKCS

ORG

EEPROM(Optional,Common)VCC

SHFBUSY

VCC

PRDB[2]/EEDOPRDB[1]/EEDI

PRDB[0]/EESK

PRDB[0-7]

Bus Master Block Diagram Plug and Play Compatible

19364A-6

Bus Master Block Diagram Plug and Play Compatible

WE

ISABus


PCnet-ISA IIController

IEEEAddressPROM

(Optional)SD[0-15]

SA[0-19]LA[17-23]

PRDB[0-7]

D[0-7]BPCS

A[0-4]

SK

DI

DO

CS

OE

EEPROM(Optional,Common)

EECS

Flash(Optional)

PRDB[0]/EESK

PRDB[1]/EEDI

PRDB[2]/EEDO

G

CS

ORG

D[0-7]

A[0-15]

16-Bit System

Data

SHFBUSY

VCC

IRQ15/APCS IRQ12/FlashWE

with Flash and parallel Address PROM Support

VCC

Am79C961A 37


Bus Slave ModeSystem Interface

The Bus Slave mode is the other fundamental operat-ing mode available on the PCnet-ISA II controller.Within the Bus Slave mode, the PCnet-ISA II can beprogrammed for a Shared Memory or Programmed I/Oarchitecture. In the Bus Slave mode the PCnet-ISA IIcontroller uses the same descriptor and buffer architec-ture as in the Bus Master mode, but these data struc-tures are stored in a static RAM controlled by thePCnet-ISA II controller. When operating with theShared Memory architecture, the local SRAM is visibleas a memory resource on the PC which can beaccessed through memory cycles on the ISA bus inter-face. When operating with the Programmed I/O archi-tecture, the local SRAM is accessible through I/Ocycles on the ISA bus. Specifically, the SRAM is acces-sible using the RAP and IDP I/O ports to access theISACSR0 and ISACSR1 registers, which serve as theSRAM Data port and SRAM Address Pointer port,respectively.

In the Bus Slave mode, the PCnet-ISA II registers andoptional Ethernet physical address PROM look thesame and are accessed in the same way as in the BusMaster mode.

The Boot PROM is selected by an external devicewhich drives the Boot PROM Address Match (BPAM)input to the PCnet-ISA II controller. The PCnet-ISA IIcontroller can perform two 8-bit accesses from the 8-bitBoot PROM and present 16-bits of data to accommo-date 16 bit read accesses on the ISA bus.

When using the Shared Memory architecture mode,access to the local SRAM works the same way asaccess to the Boot PROM, with an external device gen-erating the Shared Memory Address Match (SMAM)signal and the PCnet-ISA II controller performing theSRAM read or write and the 8/16 bit data conversion.

External logic must also drive MEMCS16 appropriatelyfor the 128Kbyte segment decoded from the LA[23:17]signals.

The Programmed I/O architecture mode uses the RAPand IDP ports to allow access to the local SRAMhence, external address decoding is not necessary andthe SMAM pin is not used in Programmed I/O architec-ture mode (SMAM should be tied HIGH in the Pro-grammed I/O architecture mode). Similar to the SharedMemory architecture mode, in the Programmed I/O ar-chitecture mode, 8/16 bit conversion occurs when 16bit reads and writes are performed on the SRAM DataPort (ISACSR1).

Converting the local SRAM accesses from 8-bit cyclesto 16-bit cycles allows use of the much faster 16-bitcycle timing while cutting the number of bus cycles inhalf. This raises performance to more than 400% ofwhat could be achieved with 8-bit cycles. When theShared Memory architecture mode is used, convertingboot PROM accesses to 16-bit cycles allows the twomemory resources to be in the same 128 Kbyte blockof memory without a clash between two devices withdifferent data widths.

The PCnet-ISA II prefetches data from the SRAM toallow fast, minimum wait-state read accesses of con-secutive SRAM addresses. In both the Shared Memoryarchitecture and the Programmed I/O architecture,prefetch data is read from a speculated address thatassumes that successive reads in time will be fromadjacent ascending addresses in the SRAM. At thebeginning of each SRAM read cycle, the PCnet-ISA IIdetermines whether the prefetched data can beassumed to be valid. If the prefetched data can beassumed to be valid, it is driven onto the ISA buswithout inserting any wait states. If the prefetched datacannot be assumed to be valid, the PCnet-ISA II will in-sert wait states into the ISA bus read cycle until thecorrect word is read from the SRAM.

38 Am79C961A


Bus Slave Block DiagramPlug and Play Compatible with Flash Memory Support

EECS

ISABus


PCnet-ISA IIController PRDB[2]/EEDO

PRDB[1]/EEDI

PRDB[0]/EESK

16-BitSystem Data

PRAB[0-15]

IRQ12/SRCS

VCC

D[0-7]

D[0–7]

A[0-15]

A[0–15]

MEMCS16

SA[16] LA[17-23]

VCC

Note:SMAM shown only for Shared Memory architecture designs. SMAM should be tied HIGH on the PCnet-ISA II for ProgrammedI/O architecture designs.

SRWE

SMAM

SMAM

SHFBUSY BPAM

SD[0]

SA[0]

PRDB[0]

SROEBPCS

WE

CS

OE

SRAM

ExternalGlueLogic

BPAM

SHFBUSY

SIN

CLK

EEPROM

WE

CS OE

DO

DI

SK

CS ORG

Flash(Optional)

19364A-7

Am79C961A 39


PLUG AND PLAYPlug and Play is a standardized method of configuringjumperless adapter cards in a system. Plug and Play isa Microsoft standard and is based on a central softwareconfiguration program, either in the operating systemor elsewhere, which is responsible for configuring allPlug and Play cards in a system. Plug and Play is fullysupported by the PCnet-ISA II ethernet controller.

For a copy of the Microsoft Plug and Play specificationcontact Microsoft Inc. This specification should bereferenced in addition to PCnet-ISA II TechnicalReference Manual and this data sheet.

OperationIf the PCnet-ISA II ethernet controller is used to boot offthe network, the device will come up active at RESET,otherwise it will come up inactive. Information stored inthe serial EEPROM is used to identify the card and todescribe the system resources required by the card,such as I/O space, Memory space, IRQs and DMAchannels. This information is stored in a standardizedRead Only format. Operation of the Plug and Playsystem is shown as follows:

Isolate the Plug and Play card

Read the cards resource data

Identify the card

Configure its resources

The Plug and Play mode of operation allows the follow-ing benefits to the end user.

Eliminates all jumpers or dip switches from theadapter card

Ease of use is greatly enhanced

Allows the ability to uniquely address identical cardsin a system, without conflict

Allows the software configuration program or OS toread out the system resource requirementsrequired by the card

Defines a mechanism to set or modify the currentconfiguration of each card

Maintain backward compatibility with other ISA busadapters

Auto-Configuration PortsThree 8 bit I/O ports are used by the Plug and Play con-figuration software on each Plug and Play device tocommunicate with the Plug and Play registers. Theports are listed in the table below. The software config-uration space is defined as a set of 8 bit registers.These registers are used by the Plug and Play softwareconfiguration to issue commands, access the resourceinformation, check status, and configure the PCnet-ISAII controller hardware.

The address and Write_DATA ports are located atfixed, predefined I/O addresses. The Write_Data port islocated at an alias of the Address port. All threeauto-configuration ports use a 12-bit ISA addressdecode.

The READ_DATA port is relocatable within the range0x203–0x3FF by a command wr i t ten to theWRITE_DATA port.

ADDRESS PORT

The internal Plug and Play registers are accessed bywriting the address to the ADDRESS PORT and theneither reading the READ_DATA PORT or writing to theWRITE_DATA PORT. Once the ADDRESS PORT hasbeen written, any number of reads or writes can occurwithout having to rewrite the ADDRESS PORT.

The ADDRESS PORT is also the address to which theinitiation key is written to, which is described later.

WRITE_DATA PORT

The WRITE_DATA PORT is the address to which allwrites to the internal Plug and Play registers occur. Thedestination of the data written to the WRITE_DATAPORT is determined by the last value written to theADDRESS PORT.

READ_DATA PORT

The READ_DATA PORT is used to read informationfrom the internal Plug and Play registers. The registerto be read is determined by the last value of theADDRESS PORT.

The I/O address of the READ_DATA PORT is set bywriting the chosen I/O location to Plug and Play Reg-ister 0. The isolation protocol can determine that theaddress chosen is free from conflict with other devicesI/O ports.

Initiation KeyThe PCnet-ISA II controller is disabled at reset whenoperating in Plug and Play mode. It will not respond toany memory or I/O accesses, nor will the PCnet-ISA IIcontroller drive any interrupts or DMA channels.

The initiation key places the PCnet-ISA II device intothe configuration mode. This is done by writing a pre-defined pattern to the ADDRESS PORT. If the propersequence of I/O writes are detected by the PCnet-ISAII device, the Plug and Play auto-configuration portsare enabled. This pattern must be sequential, i.e., any

Port Name Location Type

ADDRESS 0X279 (Printer Status Port) Write-only

WRITE-DATA0xA79 (Printer status port + 0x0800)

Write-only

READ-DATARelocatable in range 0x0203-0x03FF

Read-only

40 Am79C961A


other I/O access to this I/O port will reset the statemachine which is checking the pattern. Interruptsshould be disabled during this time to eliminate anyextraneous I/O cycles.

The exact sequence for the initiation key is listed belowin hexadecimal.

6A, B5, DA, ED, F6, FB, 7D, BE

DF, 6F, 37, 1B, 0D, 86, C3, 61

B0, 58, 2C, 16, 8B, 45, A2, D1

E8, 74, 3A, 9D, CE, E7, 73, 39

Isolation ProtocolA simple algorithm is used to isolate each Plug andPlay card. This algorithm uses the signals on the ISAbus and requires lock-step operation between the Plugand Play hardware and the isolation software.

The key element of this mechanism is that each cardcontains a unique number, referred to as the serialidentifier for the rest of the discussion. The serial iden-tifier is a 72-bit unique, non-zero, number composed oftwo, 32-bit fields and an 8-bit checksum. The first 32-bitfield is a vendor identifier. The other 32 bits can be anyvalue, for example, a serial number, part of a LANaddress, or a static number, as long as there will neverbe two cards in a single system with the same 64 bitnumber. The serial identifier is accessed bit-serially bythe isolation logic and is used to differentiate the cards.

The shift order for all Plug and Play serial isolation andresource data is defined as bit[0], bit[1], and so onthrough bit[7].

Hardware ProtocolThe isolation protocol can be invoked by the Plug andPlay software at any time. The initiation key, describedearlier, puts all cards into configuration mode. Thehardware on each card expects 72 pairs of I/O readaccesses to the READ_DATA por t. The card’sresponse to these reads depends on the value of eachbit of the serial identifier which is being examined onebit at a time in the sequence shown above.

If the current bit of the serial identifier is a “1", then thecard will drive the data bus to 0x55 to complete the firstI/O read cycle. If the bit is “0", then the card puts its databus driver into high impedance. All cards in high imped-ance will check the data bus during the I/O read cycleto sense if another card is driving D[1:0] to “01". Duringthe second I/O read, the card(s) that drove the 0x55,will now drive a 0xAA. All high impedance cards willcheck the data bus to sense if another card is drivingD[1:0] to “10". Between pairs of Reads, the softwareshould wait at least 30 µs.

If a high impedance card sensed another card drivingthe data bus with the appropriate data during bothcycles, then that card ceases to participate in the cur-rent iteration of card isolation. Such cards, which loseout, will participate in future iterations of the isolationprotocol.

Note: During each read cycle, the Plug and Play hard-ware drives the entire 8-bit databus, but only checksthe lower 2 bits.

StateIsolation

Read all 72 bitsfrom serialidentifier

ID bit = “1H”

SD[1:0] = “01"

Wait for next read from serial isolation register

SD[1:0] = “10"

StateSleep

OneCard

Isolated

Read from serialisolation register

Get one bit fromserial identifier

Yes No

No

Yes

Drive “55H”on SD[7:0]

Leave SD inhigh-impedance

Leave SD inhigh-impedance

Drive “AAH”on SD[7:0]

No

Yes

No

Yes

After I/O readcompletes, fetchnext ID bit from serial identifier

ID = 0;other cardID = 1

19364A-8

Plug and Play ISA CardIsolation Algorithm

Shifting of Serial Identifier

Byte 0

Byte 3

Byte 2

Byte1

Byte 0

Byte 3

Byte 2

Byte 1

Byte 0 Shift

Check-sum

SerialNumber

VendorID

19364A-9

Am79C961A 41


If a card was driving the bus or if the card was in highimpedance and did not sense another card driving thebus, then it should prepare for the next pair of I/Oreads. The card shifts the serial identifier by one bit anduses the shifted bit to decide its response. The abovesequence is repeated for the entire 72-bit serialidentifier.

At the end of this process, one card remains. This cardis assigned a handle referred to as the Card SelectNumber (CSN) that will be used later to select the card.Cards which have been assigned a CSN will not partic-ipate in subsequent iterations of the isolation protocol.Cards must be assigned a CSN before they willrespond to the other commands defined in thespecification.

It should be noted that the protocol permits the 8-bitchecksum to be stored in non-volatile memory on thecard or generated by the on-card logic in real-time. Thesame LFSR algorithm described in the initiation keysection of the Plug and Play specification is used in thechecksum generation.

Software ProtocolThe Plug and Play software sends the initiation key toall Plug and Play cards to place them into configurationmode. The software is then ready to perform the isola-tion protocol.

The Plug and Play software generates 72 pairs of l/Oread cycles from the READ_DATA port. The softwarechecks the data returned from each pair of I/O reads forthe 0x55 and 0xAA driven by the hardware. If both0x55 and 0xAA are read back, then the softwareassumes that the hardware had a “1" bit in that posi-tion. All other results are assumed to be a “0.”

During the first 64 bits, software generates a checksumusing the received data. The checksum is comparedwith the checksum read back in the last 8 bits of thesequence.

There are two other special considerations for the soft-ware protocol. During an iteration, it is possible that the0x55 and 0xAA combination is never detected. It is alsopossible that the checksum does not match If either ofthese cases occur on the first iteration, it must beassumed that the READ_DATA port is in conflict. If aconflict is detected, then the READ_DATA port isrelocated. The above process is repeated until a non-conflicting location for the READ_DATA port is found.The entire range between 0x203 and 0x3FF is avail-able, however in practice it is expected that only a fewlocations will be tried before software determines thatno Plug and Play cards are present.

During subsequent iterations, the occurrence of eitherof these two special cases should be interpreted as theabsence of any further Plug and Play cards (i.e. the lastcard was found in the previous iteration). Thisterminates the isolation protocol.

Note: The software must delay 1 ms prior to startingthe first pair of isolation reads, and must wait 250 µsecbetween each subsequent pair of isolation reads. Thisdelay gives the ISA card time to access informationfrom possibly very slow storage devices.

Plug and Play Card Control RegistersThe state transitions and card control commands forthe PCnet-ISA II controller are shown in the followingfigure.

42 Am79C961A


19364A-10

Plug and Play ISA Card State Transitions

Lose serialisolation OR(WAKE <> CSN)

Power upRESET or

Reset Command

Active CommandsState

Wait for Key No activecommands

SLEEP


ResetWait for KeyWake[CSN]

Isolation


ResetWait for KeySet RD_DataPort

Serial IsolationWake[CSN]

Config


ResetWait for KeyWake[CSN]Resource DataStatusLogical DeviceI/O Range CheckActivateConfigurationRegisters

Set CSN = 0

Initiation Key

Set CSN

(WAKE = 0) AND (CSN = 0) (WAKE ≠ 0) AND (Wake = CSN)

(WAKE <> CSN)

Notes1. CSN = Card Select Number

2. RESET or the Reset command causes a state transition from the current state to Wait for Key and sets all CSNs to zero.

3. The Wait for Key command causes a state transition from the current state to Wait for Key.

Plug and Play Registers

The PCnet-ISA II controller supports all of the definedPlug and Play card control registers. Refer to the tableson the following pages for detailed information.

Am79C961A 43


Plug and Play Standard Registers

NameAddress

Port Value Definition

Set RD_DATA Port 0x00 Writing to this location modifies the address of the port used for reading from the Plug and Play ISA cards. Bits[7:0] become I/O read port address bits [9:2].

Reads from this register are ignored. I/O Address bits 11:10 should = 00, and 1:0 = 11.

Serial Isolation 0x01 A read to this register causes a Plug and Play card in the Isolation state to compare one bit of the board’s ID. This process is fully described above. This register is read only.

Config Control 0x02 Bit[0] - Reset all logical devices and restore configuration registers to theirpower-up values.

Bit[1] - Return to the Wait for Key state

Bit[2] - Reset CSN to 0

A write to bit[0] of this register performs a reset function on all logical devices. This resets the contents of configuration registers to their default state. All card’s logical devices enter their default state and the CSN is preserved.

A write to bit[1] of this register causes all cards to enter the Wait for Key state but all CSNs are preserved and logical devices are not affected.

A write to bit[2] of this register causes all cards to reset their CSN to zero.

This register is write-only. The values are not sticky, that is, hardware will automatically clear them and there is no need for software to clear the bits.

Wake[CSN] 0x03 A write to this port will cause all cards that have a CSN that matches the writedata[7:0] to go from the Sleep state to either the Isolation state if the write data for this command is zero or the Config state if the write data is not zero. This register is write-only. Writing to this register resets the EEPROM pointer to the beginning of the Plug and Play Data Structure.

Resource Data 0x04 A read from this address reads the next byte of resource information. The Status register must be polled until bit[0] is set before this register may be read. This register is read-only.

Status 0x05 Bit[0] when set indicates it is okay to read the next data byte from the ResourceData register. This register is read-only.

Card Select Number 0x06 A write to this port sets a card’s CSN. The CSN is a value uniquely assigned toeach ISA card after the serial identification process so that each card may beindividually selected during a Wake [CSN] command. This register is read/write.

Logical Device Number 0x07 Selects the current logical device. This register is read only. The PCnet-ISA II controller has only 1 logical device, and this register contains a value of 0x00

44 Am79C961A


Plug and Play Logical DeviceConfiguration RegistersThe PCnet-ISA II controller supports a subset of thedefined Plug and Play logical device control registers.The reason for only supporting a subset of the registersis that the PCnet-ISA II controller does not require asmany system resources as Plug and Play allows. For

instance, Memory Descriptor 2 is not used, as thePCnet-ISA II controller only requires two memorydescriptors, one for the Boot PROM/Flash, and one forthe SRAM in Shared Memory Mode.

Plug and Play Logical Device Control Registers

Memory Space Configuration

I/O Space ConfigurationI/O Interrupt Configuration

NameAddress

Port Value Definition

Activate 0x30 For each logical device there is one activate register that controls whether or not the logical device is active on the ISA bus. Bit[0], if set, activates the logical device. Bits[7:1] are reserved and must be zero. This is a read/write register. Before a logical device is activated, I/O range check must be disabled.

I/O Range Check 0x31 This register is used to perform a conflict check on the I/O port range programmed for use by a logical device.

Bit[7:2] Reserved

Bit 1[1] Enable I/O Range check, if set then I/O Range Check is enabled. I/O range check is only valid when the logical device is inactive.

Bit[0], if set, forces the logical device to respond to I/O reads of the logical device’s assigned I/O range with a 0x55 when I/O range check is in operation. If clear, the logical device drives 0xAA. This register is read/write.

NameRegister

Index Definition

Memory base addressbits[23:16] descriptor 0

0x40 Read/write value indicating the selected memory base address bits[23:16] for memory descriptor 0. This is the Boot Prom Space.

Memory base addressbits [23:16] descriptor 0

0x41 Read/write value indicating the selected memory base address bits[15:08] for memory descriptor 0.

Memory control 0x42 Bit[1] specifies 8/16-bit control. The encoding relates to memory control(bits[4:3]) of the information field in the memory descriptor.

Bit[0], =0, indicates the next field is used as a range length for decode(implies range length and base alignment of memory descriptor are equal).

Bit[0] is read-only.

Memory upper limitaddress;bits [23:16] or rangelength;bits [15:08] fordescriptor 0

0x43 Read/write value indicating the selected memory high address bits[23:16] for memory descriptor 0.

If bit[0] of memory control is 0, this is the range length.

If bit[0] of memory control is 1, this is considered invalid.

Memory upper limitbits [15:08] or rangelength;bits [15:08] fordescriptor 0

0x44 Read/write value indicating the selected memory high address bits[15:08] for memory descriptor 0, either a memory address or a range length as described above.

Memory descriptor 1 0x48-0x4C Memory descriptor 1. This is the SRAM Space for Shared Memory.

NameRegister

Index Definition

I/O port base addressbits[15:08] descriptor 0

0x60 Read/write value indicating the selected I/O lower limit address bits[15:08] forI/O descriptor 0. If a logical device indicates it only uses 10 bit encoding, then bits[15:10] do not need to be supported.

Am79C961A 45


DMA Channel Configuration

DETAILED FUNCTIONS

EEPROMInterface

The EEPROM supported by the PCnet-ISA II controlleris an industry standard 93C56 2-Kbit EEPROM devicewhich uses a 4-wire interface. This device directly inter-faces to the PCnet-ISA II controller through a 4-wireinterface which uses 3 of the private data bus pins forData In, Data Out, and Serial Clock. The Chip Selectpin is a dedicated pin from the PCnet-ISA II controller.

Note: All data stored in the EEPROM is stored inbit-reversal format. Each word (16 bits) must be writteninto the EEPROM with bit 15 swapped with bit 0, bit 14swapped with bit 1, etc.This is a 2-Kbit device organized as 128 x 16 bit words.A map of the device as used in the PCnet-ISA II con-troller is below. The information stored in the EEPROMis as follows:

Important Note About The EEPROM Byte MapThe user is cautioned that while the Am79C961A(PCnet-ISA II) and its associated EEPROM are pincompatible to their predecessors the Am79C961(PCnet-ISA+) and its associated EEPROM, the bytemap structure in each of the EEPROMs are differentfrom each other.

The EEPROM byte map structure used for theAm79C961A PCnet-ISA II has the addition of “MISCConfig 2, ISACSR9" at word location 10Hex. TheEEPROM byte map structure used for the Am79C961PCnet-ISA+ does not have this.

Therefore, should the user intend to replace thePCnet-ISA+ with the PCnet-ISA II, care MUST be takento reprogram the EEPROM to reflect the new byte mapstructure needed and used by the PCnet-ISA II. Foradditional information, refer to the Am79C961PCnet-ISA+ data sheet (PID #18183) under the sec-tions entitled EEPROM and Serial EEPROM Byte Map.

I/O port base addressbits[07:00] descriptor 0

0x61 Read/write value indicating the selected I/O lower limit address bits[07:00] forI/O descriptor 0.

NameRegister

Index Definition

Interrupt request level select 0

0x70Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt level used for Interrupt 0. One selects IRQL 1, fifteen selects IRQL fifteen. IRQL 0 is not a valid interrupt selection and represents no interrupt selection.

Interrupt request type select 0

0x71

Read/write value indicating which type of interrupt is used for the Request Level selected above.

Bit[1] : Level, 1 = high, 0 = low

Bit[0] : Type, 1 = level, 0 = edge

The PCnet-ISA II controller only supports Edge High and Level Low Interrupts.

NameRegister

Index Definition

NameRegister

Index Definition

DMA channel select 0 0x74Read/write value indicating selected DMA channels. Bits[2:0] select which DMA channel is in use for DMA 0. Zero selects DMA channel 0, seven selects DMA channel 7. DMA channel 4, the cascade channel is used to indicate no DMA channel is active.

DMA channel select 1 0x75 Read only with a value of 0x04.

IEEE address 6 bytesReserved10 bytesEISA ID4 bytesISACSRs14 bytesPlug and Play Defaults19 bytes8-Bit Checksum1 byteExternal Shift Chain2 bytesPlug and Play Config Info192 bytes

46 Am79C961A


Basic EEPROM Byte MapThe following is a byte map of the XXC56 series ofEEPROMs used by the PCnet-ISA II Ethernet

Controller. This byte map is for the case where anon-PCnet Family compatible software driver isimplemented.

Note: Checksum is calculated on words 0 through 0x1Bh (first 56 bytes).

Byte 1

Byte 3

Byte 5

Byte 7

Byte 9

Byte 11

Byte 13

Byte 15

EISA Byte 1

EISA Byte 3

Byte 0

Byte 2

Byte 4

Byte 6

Byte 8

Byte 10

Byte 12

Byte 14

EISA Byte 0

EISA Byte 2

MSRDA, ISACSR0

MSWRA, ISACSR1

MISC Config 1, ISACSR2

LED1 Config, ISACSR5




PnP 0x61

Pnp 0x71

Unused

PnP 0x41

PnP 0x43

Unused

PnP 0x49

PnP 0x4B

Unused

8–Bit Checksum

PnP 0x60

PnP 0x70

PnP 0x74

PnP 0x40

PnP 0x42

PnP 0x44

PnP 0x48

PnP 0x4A

PnP 0x4C

PnP 0xF0

External Shift Chain

Unused Locations

Plug and Play Starting Location

IEEE Address (0h)

(8h)

Internal Registers

(11h)

Plug and Play Reg.

(1Ah)

(20h)

EISA Config Reg.

(Ah)

(1Bh)

(1Ch)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

10

11

12

13

14

15

16

17

18

19

1B

1C

20

..1F

WordLocation

I/O Ports

Interrupts

DMA Channels

ROM Memory

RAM Memory

Vendor Byte

(Bytes 0 – 5)

Am79C961A 47


AMD Device Driver Compatible EEPROM Byte MapThe following is a byte map of the XXC56 seriesof EEPROMs used by the PCnet-ISA II EthernetController. This byte map is for the case where a

PCnet Family compatible software driver is imple-mented.

(This byte map is an application reference for use indeveloping AMD software devices.)

Note: Checksum 1 is calculated on words 0 through 5 plus word 7.

Checksum 2 is calculated on words 0 through 0x1Bh (first 56 bytes).

IEEE Address

Internal Registers

Plug and Play Reg.

See Appendix C

EISA Config Reg.

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

11

12

13

14

15

16

17

18

19

1A

1B

1C

20

..1F

WordLocation

I/O Ports

Interrupts

DMA Channels

ROM Memory

RAM Memory

Vendor Byte

See Appendix C

(Bytes 0–5)

Byte 1

Byte 3

Byte 5

ASCII W (0 x 57H)

EISA Byte 1

EISA Byte 3

Byte 0

Byte 2

Byte 4

ASCII W (0 x 57H)

EISA Byte 0

EISA Byte 2

MSRDA, ISACSR0

MSWRA, ISACSR1

MISC Config, ISACR2





PnP 0x61

Pnp 0x71

Unused

PnP 0x41

PnP 0x43

Unused

PnP 0x49

PnP 0x4B

Unused

8-Bit Checksum

PnP 0x60

PnP 0x70

PnP 0x74

PnP 0x40

PnP 0x42

PnP 0x44

PnP 0x48

PnP 0x4A

PnP 0x4C

PnP 0xF0

External Shift Chain

Unused Locations

Plug and Play Starting Location

User Space 1

16-Bit Checksum 1

Reserved

HWID (01H)

Reserved

Reserved

10

48 Am79C961A


Plug and Play Register MapThe following chart and its bit descriptions show theinternal configuration registers associated with the

Plug and Play operation. These registers control theconfiguration of the PCnet-ISA II controller.

Plug and Play Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x00 READ_DATA

0x01 SERIAL ISOLATION

0x02 0 0 0 0 0 RST WAIT RSTCSN KEY ALL

0x03 WAKE [CSN]

0x04 RESOURCE_DATA

0x05 0 0 0 0 0 0 0 READSTATUS

0x06 CSN

0x07 LOGICAL DEVICE NUMBER

0x30 0 0 0 0 0 0 0 ACTIVATE

0x31 0 0 0 0 0 0 IORNG IORNG

READ_DATA Address of Plug and Play READ_DATA Port.

SERIAL_ISOLATION Used in the Serial Isolation process.

RST_CSN Resets CSN register to zero.

WAIT_KEY Resets Wait for Key State.

RST_ALL Resets all logical devices.

WAKE [CSN] Will wake up if write data matches CSN Register.

READ_STATUS Read Status of RESOURCE DATA.

RESOURCE_DATA Next pending byte read from EEPROM.

CSN Plug and Play CSN Value.

ACTIVATE Indicates that the PCnet-ISA II device should be activated.

IORNG Bits used to enable the I/O Range Check Command.

Am79C961A 49


The following chart and its bit descriptions show theinternal command registers associated with the Plug

and Play operation. These registers control thePCnet-ISA II controller Plug and Play operation.

PCnet–ISA II’s Legacy Bit Feature DescriptionThe current PCnet-ISA II chip is designed such that italways responds to Plug and Play configuration soft-ware. There are situations where this response to thePlug and Play software is undesirable. An example ofthis is when a fixed configuration is required, or whenthe only possible resource available for the PCnet-ISAII conflicts with a present but not used resource such asIRQ, or when the chip is used in a system with a buggyPnP BIOS.

To function in the situations above, a new feature hasbeen added to the PCnet-ISA II chip. This new feature

makes the chip ignore the PnP software’s special initi-ation key sequence (6A). This will effectively turn thechip into the “Legacy” mode operation, where it will bevisible in the I/O space, and only special setup pro-grams will be able to reconfigure it. In case theEEPROM is missing, empty, or corrupted, the chip willstill recognize AMD’s special initiation key sequence(6B).

To enable this feature, a one has to be written into theLGCY_EN bit, which is bit 6 of the Plug and Play regis-ter 0xF0. A preferred method would be set this bit inthe Vendor Byte (PnP 0xF0) field of the EEPROMlocated in word offset 0x1A.

Plug and Play Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x60 0 0 0 0 0 0 1 IOAM3

0x61 IOAM2 IOAM1 IOAM0 0 0 0 0 0

0x70 0 0 0 0 IRQ3 IRQ2 IRQ1 IRQ0

0x71 0 0 0 0 0 0 IRQ_LVL IRQ_TYPE

0x74 0 0 0 0 0 DMA2 DMA1 DMA0

0x40 0 0 0 0 1 1 0 BPAM3

0x41 BPAM2 BPAM1 BPAM0 0 0 0 0 0

0x42 0 0 0 0 0 0 BP_16B 0

0x43 1 1 1 1 1 1 1 BPSZ3

0x44 BPSZ2 BPSZ1 BPSZ0 0 0 0 0 0

0x48 0 0 0 0 1 1 SRAM4 SRAM3

0x49 SRAM2 SRAM1 SRAM0 0 0 0 0 0

0x4A 0 0 0 0 0 0 SR16B 0

0x4B 1 1 1 1 1 1 1 SRSZ3

0x4c SRSZ2 SRSZ1 SRSZ0 0 0 0 0 0

0xF0 0 LGCY_EN DXCVRP FL_SEL BP_CS APROM_EN AEN_CS IO_MODE

50 Am79C961A


Plug & Play Register Locations Detailed Description (Refer to the Plug & Play Register Map above).IOAM[3:0] I/O Address Match to bits [8:5] of SA

bus (PnP 0x60–0x61). Controls thebase address of PCnet-ISA II. TheIOAM will be written with a valuefrom the EEPROM.

IRQ[3:0] IRQ selection on the ISA bus (PnP0x70). Controls which interrupt willbe asserted. ISA Edge sensitive orEISA level mode is controlled byIRQ_TYPE bit in PnP 0x71. Defaultis ISA Edge Sensitive. The IRQ sig-nals will not be driven unless PnPactivate register bit is set.

IRQ Type IRQ Type(PnP 0x71). Indicates thetype of interrupt setting; Level is 1,Edge is 0.

IRQ_LVL IRQ Level (PnP 0x71). A read-onlyregister bit that indicates the type ofsetting, active high or low. Alwayscomplement of IRQ_TYPE.

DMA[2:0] DMA Channel Select (PnP 0x74).Controls the DRQ and DMA selec-tion of PCnet-ISA II. The DMA[2:0]

register will be written with a valuefrom the EEPROM. For Bus MasterMode Only The DRQ signals willnot be driven unless Plug and Playactivate register bit is set.

BPAM[3:0] Boot PROM Address Match to bits[16:13] of SA bus (PnP 0x40–0x41).Selects the location where the BootPROM Address match decode isstarted. The BPAM will be writtenwith a value from the EEPROM.

BP_16B Boot PROM 16-bit access (PnP0x42). Is asserted if Boot PROMcycles should respond as an 16-bitdevice. In Bus Master mode, all bootPROM cycles will only be 8 bits inwidth.

BPSZ[3:0] Boot PROM Size (PnP 0x43–0x44).Selects the size of the boot PROMselected.

SRAM[4:0] Static RAM Address Match to bits[17:13] of SA bus (PnP 0x48-0x49).Selects the starting location of theShared Memory when using the

IOAM[3:0] Base Address (Hex)0 0 0 0 2000 0 0 1 2200 0 1 0 2400 0 1 1 2600 1 0 0 2800 1 0 1 2A00 1 1 0 2C00 1 1 1 2E01 0 0 0 300 1 0 0 1 3201 0 1 0 3401 0 1 1 3601 1 0 0 3801 1 0 1 3A01 1 1 0 3C01 1 1 1 3E0

IRQ[3:0] ISA IRQ Pin

0 0 1 1 IRQ3 (Default)

0 1 0 0 IRQ4

0 1 0 1 IRQ5

1 0 0 1 IRQ9

1 0 1 0 IRQ10

1 0 1 1 IRQ11

1 1 0 1 IRQ12

1 1 1 0 IRQ15

DMA[2:0] DMA Channel (DRQ/DACK Pair)

0 1 1 Channel 3

1 0 1 Channel 5

1 1 0 Channel 6

1 1 1 Channel 7

1 0 0 No DMA Channel

BPAM[3:0]Address

Location (Hex)Size Supported(K bytes)

0 0 0 0 C0000 8, 16, 32, 640 0 0 1 C2000 80 0 1 0 C4000 8, 160 0 1 1 C6000 80 1 0 0 C8000 8, 16, 320 1 0 1 CA000 80 1 1 0 CC000 8, 160 1 1 1 CE000 81 0 0 0 D0000 8, 16, 32, 641 0 0 1 D2000 81 0 1 0 D4000 8, 161 0 1 1 D6000 81 1 0 0 D8000 8, 16, 321 1 0 1 DA000 81 1 1 0 DC000 8, 161 1 1 1 DE000 8

BPSZ[3:0] Boot PROM Size

0 x x x No Boot PROM Selected

1 1 1 1 8 K

1 1 1 0 16 K

1 1 0 0 32 K

1 0 0 0 64 K

Am79C961A 51


Shared Memory architecture mode.The SRAM[2:0] bits are used for per-forming address decoding on theSA[15:13] address bits as shown inthe table below. SRAM[4] andSRAM[3] must reflect the externaladdress match logic for SA[17] andSA[16], respectively. The SRAM[4:0]bits are ignored when in the BusMaster mode or in the ProgrammedI/O Architecture mode.

SR_16B Static RAM 16-bit access (PnP0x4A). If asserted, the PCnet-ISA IIwill respond to SRAM cycles as a16-bit device. This bit should be setif external logic is designed to assertthe MEMCS16 s igna l whenaccesses to the shared memory aredecoded. This bit is ignored when inthe Bus Master mode or in the Pro-grammed I/O Architecture mode.

SRSZ[3:0] Static RAM size (PnP 0x4B-0x4C).Selects the size of the static RAM.The SRSZ[3:0] bits are ignoredwhen in the Bus Master mode or inthe Programmed I/O Architecturemode.

Vendor Defined Byte (PnP 0xF0)LGCY_EN Legacy mode enable. When written

with a one, the PCnet-ISA II will notrespond to the Plug and Play initia-tion key sequence (6A) but willrespond to the AMD key sequence(6B). Therefore, it cannot be recon-figured by the Plug and Play soft-ware. When set to zero (default), the

PCnet-ISA II will respond to the 6Akey sequence if the EEPROM readwas successful, otherwise it will re-spond to the 6B key sequence.

DXCVRP DXCVR Polarity. The DXCVRP bitsets the polarity of the DXCVR pin.When DXCVRP is cleared (default),the DXCVR pin is driven HIGH whenthe Twisted Pair port is active orSLEEP mode has been entered anddriven LOW when the AUI port isactive. When DXCVRP is set, theDXCVR pin is driven LOW when theTwisted Pair port is active or SLEEPmode has been entered and drivenHIGH when the AUI port is active.

The DXCVRP should generally beleft cleared when the PCnet-ISA II isbeing used with an external DC-DCconverter that has an active lowenable pin. The DXCVRP shouldgenera l l y be se t when thePCnet-ISA II is being used with anexternal DC-DC converter that hasan active high enable pin.

IO_MODE I/O Mode. When set to one, theinternal selection will respond as a16-bit port, (i.e. drive IOCS16 pin).When IO_MODE is set to zero,(Default), the internal I/O selectionwill respond as an 8-bit port.

AEN_CS External Decode Logic for I/O Reg-isters. When written with a one, thePCnet-ISA II will use the AEN pin asI/O chip select bar, to allow for exter-nal decode logic for the upper ad-dress bit of SA [9:5]. The purpose ofthis pin is to allow I/O locations, notsupported with the IOAM[3:0],selection, to be defined outside therange 0x200–0x3F7. When set to azero, (Default), I/O Selection will useIOAM[3:0].

APROM_EN External Parallel IEEE AddressPROM. When set, the IRQ15 pin isreconfigured to be an Address ChipSelect low, similar to APCS pin in theexisting PCnet-ISA (Am79C960)device. The purpose of this bit is toallow for both a serial EEPROM andparallel PROM to coexist. WhenAPROM_EN is se t , the IEEEaddress located in the serial EE-PROM will be ignored and parallelaccess will occur over the PRDBbus. When APROM_EN is cleared,

SRAM[2:0] SA[15:13]SRAM Size(K bytes)

0 0 0 0 0 0 8, 16, 32, 64

0 0 1 0 0 1 8

0 1 0 0 1 0 8, 16

0 1 1 0 1 1 8

1 0 0 1 0 0 8, 16, 32

1 0 1 1 0 1 8

1 1 0 1 1 0 8, 16

1 1 1 1 1 1 8

SRSZ[3:0] Shared Memory Size

0 x x x No Static RAM Selected

1 1 1 1 8 K

1 1 1 0 16 K

1 1 0 0 32 K

1 0 0 0 64 K

52 Am79C961A


default state, the IEEE address willbe read in from the serial device andwritten to an internal RAM. Whenthe I/O space of the IEEE PROM isselected, PCnet-ISA II, will accessthe contents of this RAM for I/O readcycles. I/O write cycles wil l beignored.

BP_CS Boot PROM Chip Select. WhenBP_CS is set to one, BALE will actas an external chip select (activelow) above bit 15 of the address bus.BALE = 0, will select the boot PROMwhen MEMR is asserted low if theBP_CS bit is set and BPAM[2:0]match SA[15:13] and BPSZ[3:0]matches the selected size. WhenBP_CS is set to zero. BALE will actas the normal address latch strobeto capture the upper address bits formemory access to the boot PROM.BP_CS is by default low. The pri-mary purpose of this bit is to allownon-ISA bus applications to supportlarger Boot PROMS or non-standardBoot PROM/Flash locations.

FL_SEL Flash Memory Device Selected.When set , the Boot PROM isreplaced with an external Flashmemory device. In Bus MasterMode, BPCS is replaced wi thF lash_OE. IRQ12 becomesFlash_WE. The Flash’s CS pin isgrounded. In shared memory mode,BPCS is replaced with Flash_CS.IRQ12 becomes Static_RAM_CSpin. The SROE and SRWE signalsare connected to both the SRAMand Flash memory devices. FL_SELis cleared by a reset, which is thedefault.

Checksum FailureAfter RESET, the PCnet-ISA II controller beginsreading the EEPROM and storing the information inregisters inside PCnet-ISA II controller. PCnet-ISA IIcontroller does a checksum on word locations 0-1Bhinclusive and if the byte checksum = FFh, then thedata read from the EEPROM is considered good. Ifthe checksum is not equal to FFh, then thePCnet-ISA II controller enters what is called softwarerelocatable mode.

In software relocatable mode, the device functions thesame as in Plug and Play mode, except that it does notrespond to the same initiation key as Plug and Playsupports. Instead, a different key is used to bring

PCnet-ISA II controller out of the Wait For Key state.This key is as follows:

6B, 35, 9A, CD, E6, F3, 79, BC

5E, AF, 57, 2B, 15, 8A, C5, E2

F1, F8, 7C, 3E, 9F, 4F, 27, 13

09, 84, 42, A1, D0, 68, 34, 1A

Use Without EEPROMIn some designs, especially PC motherboard applica-t ions, i t may be des i rable to e l im ina te theEEPROM altogether. This would save money, space,and power consumption.

The operation of this mode is similar to when thePCnet-ISA II controller encounters a checksum error,except that to enter this mode the SHFBUSY pin is leftunconnected. The device will enter software relocat-able mode, and the BIOS on the motherboard canwake up the device, configure it, load the IEEE address(possibly stored in Flash ROM) into the PCnet-ISA IIcontroller, and activate the device.

External Scan ChainThe External Scan Chain is a set of bits stored in theEEPROM which are not used in the PCnet-ISA II con-troller but which can be used with external hardware toallow jumperless configuration of external devices.

A f te r RESET, the PCnet - ISA I I con t ro l le rbegins reading the EEPROM and storing the informa-t ion in reg is te rs ins ide the PCnet - ISA I Icontroller. SHFBUSY is held high during the read of theEEPROM. If external circuitry is added, such as a shiftregister, which is clocked from SCLK and is attached toDO from the EEPROM, data read out of the EEPROMwill be shifted into the shift register. After reading theEEPROM to the end of the External Shift Chain, and ifthere is a correct checksum, SHFBUSY will go low.This will be used to latch the information fromthe EEPROM into the shift register. If the checksum isinvalid, SHFBUSY will not go low, indicating that theEEPROM may be bad.

Flash PROMUse

Instead of using a PROM or EPROM for the BootPROM, it may be desirable to use a Flash or EEPROMtype of device for storing the Boot code. This wouldallow for in-system updates and changes to the infor-mation in the Boot ROM without opening up the PC. Itmay also be desirable to store statistics or drivers in theFlash device.

InterfaceTo use a Flash-type device with the PCnet-ISAII controller, Flash Select is set in register 0F0h of the

Am79C961A 53


Plug and Play registers. Flash Select is clearedby RESET (default).

In bus master mode, BPCS becomes Flash_OE andIRQ12 becomes Flash_WE. The Flash ROM devicesCS pin is connected to ground.

In shared memory mode, BPCS becomes Flash_CSand IRQ12 becomes the static RAM Chip Select, andthe SROE and SRWE signals are connected to boththe SRAM and Flash devices.

Optional IEEE Address PROMNormally, the Ethernet physical address will be storedin the EEPROM with the other configuration data. Thisreduces the parts count, board space requirements,and power consumption. The option to use a standardparallel 8 bit PROM is provided to manufacturers whoare concerned about the non-volat i le natureof EEPROMs.

To use a 8 bit parallel PROM to store the IEEE addressdata instead of storing it in the EEPROM, theAPROM_EN bit is set in the Plug and Play registers bythe EEPROM upon RESET. IRQ15 is redefined by thesetting of this bit to be APCS, or ADDRESS PROMCHIP SELECT. This pin is connected to an external 8bit PROM, such as a 27LS19. The address pins of thePROM are connected to the lower address pins of theISA bus, and the data lines are connected to the privatedata bus.

In this mode, any accesses to the IEEE address will bepassed to the external PROM and the data will bepassed through the PCnet-ISA II controller tothe system data bus.

EISA Configuration RegistersThe PCnet-ISA II controller has support for the 4-byteEISA Configuration Registers. These are used in EISAsystems to identify the card and load the appropriateconfiguration file for that card. This feature is enabledusing bit 10 of ISACSR2. When set to 1, the EISA Con-figuration registers will be enabled and will be read atI/O location 0xC80–0xC83. The contents of these 4registers are stored in the EEPROM and are automat-ically read in at RESET.

Bus Interface Unit (BIU)The bus interface unit is a mixture of a 20 MHz statemachine and asynchronous logic. It handles two typesof accesses; accesses where the PCnet-ISA II control-ler is a slave and accesses where the PCnet-ISA II con-troller is the Current Master.

In slave mode, signals like IOCS16 are asserted anddeasserted as soon as the appropriate inputsare received. IOCHRDY is asynchronously driven LOWif the PCnet-ISA II controller needs a wait state. It is

released synchronously when the PCnet-ISA II control-ler is ready.

When the PCnet-ISA II controller is the Current Master,all the signals it generates are synchronous to theon-chip 20 MHz clock.

DMA TransfersThe BIU will initiate DMA transfers according to thetype of operation being performed. There are three pri-mary types of DMA transfers:

1. Initialization Block DMA Transfers

During initialization, the PCnet-ISA II transfers 12words from the initialization block in memory to internalregisters. These 12 words are transferred through dif-ferent bus mastership period sequences, depending onwhether the TIMER bit (CSR4, bit 13) is set and, ifTIMER is set, on the value in the Bus Activity Timerregister (CSR82).

If the TIMER bit is reset (default), the 12 words arealways transferred during three separate bus master-ship periods. During each bus mastership period, fourwords (8 bytes) will be read from contiguous memoryaddresses.

If the TIMER bit is set, the 12 words may be transferredusing anywhere from 1 to 3 bus mastership periods,depending on the value of the Bus Activity Timer regis-ter (CSR82). During each bus mastership period, aminimum of four words (8 bytes) will be read from con-tiguous memory addresses. If the TIMER bit is set andthe value in the Bus Activity Timer register allows it, 8or all 12 words of the initialization block are read duringa single bus mastership period.

2. Descriptor DMA Transfers

Descriptor DMA transfers are performed to read orwrite to transmit or receive descriptors. All transmit andreceive descriptor READ accesses require 3 wordreads (TMD1, TMD0, then TMD2 for transmit descrip-tors and RMD1, RMD0, then RMD2 for receive descrip-tors). Transmit and receive descriptor WRITE accessesto unchained descriptors or the last descriptor in achain (ENP set) require 2 word writes (TMD1 thenTMD3 for transmit and RMD1 then RMD3 for receive).Transmit and receive descriptor WRITE accesses tochained descriptors that do not have ENP set require 1word write (TMD1 for transmit and RMD1 for receive).During descriptor write accesses, only the bytes whichneed to be written are written, as controlled by the SA0and SBHE pins.

If the TIMER bit is reset (default), all accesses during asingle bus mastership period will be either all read or allwrite and will be to only one descriptor. Hence, whenthe TIMER bit is reset, the bus mastership periods fordescriptor accesses are always either 3, 2, or 1 cycles

54 Am79C961A


long, depending on which descriptor operation is beingperformed.

If the TIMER bit is set, the 3, 2, or 1 cycles required ina descriptor access may be performed as a part of abus mastership period in which any combination ofdescriptor reads and writes and buffer reads and writesare performed. When the TIMER bit is set, the BusActivity Timer (CSR82) and the bus access require-ments of the PCnet-ISA II govern the operations per-formed during a single bus mastership period.

3. FIFO DMA Transfers

FIFO DMA transfers occur when the PCnet-ISA IImicrocode determines that transfers to and/or from theFIFOs are required. Once the PCnet-ISA II BIU hasbeen granted bus mastership, it will perform a series ofconsecutive transfer cycles before relinquishing thebus.

When the Bus Activity Timer is disabled by clearing theTIMER (CSR4, bit 13) bit, all FIFO DMA transferswithin a bus mastership period will be either read orwrite cycles, and all transfers will be to adjacent,ascending addresses. When the Bus Activity Timer isenabled by setting the TIMER bit, DMA transfers withina bus mastership period may consist of any mixture ofread and write cycles, without restriction on theaddress ordering. This mode of operation allows thePCnet-ISA II to accomplish more during each busownership period.

The number of data transfer cycles contained within asingle bus mastership period is in general dependenton the programming of the DMAPLUS (CSR4, bit 14)and the TIMER (CSR4, bit 13) options. Several otherfactors will also affect the length of the bus mastershipperiod. The possibilities are as follows:

If DMAPLUS = 0 and TIMER = 0, a maximum of 16transfers to or from the FIFO will be performed bydefault. This default value may be changed by writing tothe DMA Burst Register (CSR80, bits 7:0). SinceTIMER = 0, all FIFO DMA transfers within a bus mas-tership period will be either read or write cycles, and alltransfers will be to adjacent, ascending addresses.Note that DMAPLUS = 0 merely sets a maximum valuefor the number of FIFO transfers that may occur duringone bus mastership period. The minimum number oftransfers in the bus mastership period will be deter-mined by the settings of the FIFO watermarks and theconditions of the FIFOs, and the value of the Bus Activ-ity Timer (CSR82) if the TIMER bit is set.

If DMAPLUS = 1 and TIMER = 0, the bus mastershipperiod will continue until the transmit FIFO is filled to itshigh threshold (read transfers) or the receive FIFO isemptied to its low threshold (write transfers). Othervariables may also affect the end point of the bus mas-tership period in this mode, including the particularconditions existing within the FIFOs, and receive and

transmit status conditions. Since TIMER = 0, all FIFODMA transfers within a bus mastership period will beeither read or write cycles, and all transfers will be toadjacent, ascending addresses.

If TIMER = 1, the bus mastership period will continueuntil all “pending bus operations” are completed or untilthe Bus Activity Timer value (CSR82) has expired.These bus operations may consist of any mixture ofdescriptor and buffer read and write accesses. If DMA-PLUS = 1, “pending bus operations” includes any de-scriptor accesses and buffer accesses that need to beperformed. If DMAPLUS = 0, “pending bus operations”include any descriptor accesses that need to be per-formed and any buffer accesses that need to be per-formed up to the limit specified by the DMA BurstRegister (CSR80, bits 7:0).

Note that when TIMER=1, following a last bus transac-tion during a bus mastership period, the PCnet-ISA IImay keep ownership of the bus for up to approximately1µs. The PCnet-ISA II determines whether there arefurther pending bus operations by waiting approxi-mately 1µs after the completion of every bus operation(e.g. a descriptor or FIFO access). If, during the 1 µsperiod, no further bus operations are requested by theinternal Buffer Management Unit, the PCnet-ISA IIdetermines that there are no further pending opera-tions and gives up bus ownership. This 1 µs of unusedbus ownership time is more than made up for by theefficiency gained by being able to perform any mixtureof descriptor and buffer read and write accesses duringa single bus ownership period.

The FIFO thresholds are programmable (see descrip-tion of CSR80), as are the DMA Burst Register and BusActivity Timer values. The exact number of transfercycles in the case of DMAPLUS = 1 will be dependenton the latency of the system bus to the PCnet-ISA IIcontroller’s DMA request and the speed of bus opera-tion, but will be limited by the value in the Bus ActivityTimer register (if the TIMER bit is set), the FIFO condi-tion, and receive and transmit status. Barring a time-outby either of these registers, or exceptional receive andtransmit events, or an end of packet signal from theFIFO, the FIFO watermark settings and the extent ofBus Grant latency will be the major factors determiningthe number of accesses performed during any givenarbitration cycle when DMAPLUS = 1.

The IOCHRDY response of the memory device will alsoaffect the number of transfers when DMAPLUS = 1,since the speed of the accesses will affect the state ofthe FIFO. During accesses, the FIFO may be filling oremptying on the network end. A slower memoryresponse will allow additional data to accumulateinside of the FIFO (during write transfers from thereceive FIFO). If the accesses are slow enough, a com-plete word may become available before the end of thearbitration cycle and thereby increase the number of

Am79C961A 55


transfers in that cycle. The general rule is that thelonger the Bus Grant latency or the slower the bustransfer operations (or clock speed) or the higher thetransmit watermark or the lower the receive watermarkor any combination thereof, the longer will be the aver-age bus mastership period.

Buffer Management Unit (BMU)The buffer management unit is a microcoded 20 MHzstate machine which implements the initialization blockand the descriptor architecture.

Initialization

PCnet-ISA II controller initialization includes the read-ing of the initialization block in memory to obtain theoperating parameters. The initialization block is readwhen the INIT bit in CSR0 is set. The INIT bit should beset before or concurrent with the STRT bit to insure cor-rect operation. See previous section “1. InitializationBlock DMA Transfer.” Once the initialization block hasbeen read in and processed, the BMU knows wherethe receive and transmit descriptor rings are. On com-pletion of the read operation and after internal registershave been updated, IDON will be set in CSR0, and aninterrupt generated if IENA is set.

The Initialization Block is vectored by the contents ofCSR1 (least significant 16 bits of address) and CSR2(most significant 8 bits of address). The block containsthe user defined conditions for PCnet-ISA II controlleroperation, together with the address and length infor-mation to allow linkage of the transmit and receivedescriptor rings.

There is an alternative method to initialize thePCnet-ISA II controller. Instead of initialization via theinitialization block in memory, data can be writtendirectly into the appropriate registers. Either methodmay be used at the discretion of the programmer. If theregisters are written to directly, the INIT bit must not beset, or the initialization block will be read in, thus over-writing the previously written information. Please referto Appendix D for details on this alternative method.

Reinitialization

The transmitter and receiver section of the PCnet-ISAII controller can be turned on via the initialization block(MODE Register DTX, DRX bits; CSR15[1:0]). Thestate of the transmitter and receiver are monitoredthrough CSR0 (RXON, TXON bits). The PCnet-ISA IIcontroller should be reinitialized if the transmitter and/or the receiver were not turned on during the originalinitialization and it was subsequently required to acti-vate them, or if either section shut off due to the detec-tion of an error condition (MERR, UFLO, TX BUFFerror).

Reinitialization may be done via the initialization blockor by setting the STOP bit in CSR0, followed by writingto CSR15, and then setting the START bit in CSR0.

Note that this form of restart will not perform the samein the PCnet-ISA II controller as in the LANCE. In par-ticular, the PCnet-ISA II controller reloads the transmitand receive descriptor pointers (working registers) withtheir respective base addresses. This means that thesoftware must clear the descriptor’s own bits and resetits descriptor ring pointers before the restart of thePCnet-ISA controller. The reload of descriptor baseaddresses is performed in the LANCE only after initial-ization, so a restart of the LANCE without initializationleaves the LANCE pointing at the same descriptorlocations as before the restart.

Suspend

The PCnet-ISA II controller offers a suspend mode thatallows easy updating of the CSR registers withoutgoing through a full reinitialization of the device. Thesuspend mode also allows stopping the device withorderly termination of all network activity.

The host requests the PCnet-ISA II controller to enterthe suspend mode by setting SPND (CSR5, bit 0) toONE. The host must poll SPND until it reads back ONEto determine that the PCnet-ISA II controller has en-tered the suspend mode. When the host sets SPND toONE, the PCnet-ISA II controller first finishes allon-going transmit activity and updates the correspond-ing transmit descriptor entries. It then finishes allon-going receive activity and updates the correspond-ing receive descriptor entr ies. It then sets theread-version of SPND to ONE and enters the suspendmode. In suspend mode, all of the CSR registers areaccessible. As long as the PCnet-ISA II controller is notreset while in suspend mode (by asserting the RESETpin, reading the RESET register, or by setting theSTOP bit), no reinitialization of the device is requiredafter the device comes out of suspend mode. WhenSPND is set to ZERO, the PCnet-ISA II controller willleave the suspend mode and will continue at the trans-mit and receive descriptor ring locations where it hadleft when it entered the suspend mode.

Buffer Management

Buffer management is accomplished through messagedescriptor entries organized as ring structures in mem-ory. There are two rings, a receive ring and a transmitring. The size of a message descriptor entry is 4 words(8 bytes).

Descriptor Rings

Each descriptor ring must be organized in a contiguousarea of memory. At initialization time (setting the INITbit in CSR0), the PCnet-ISA II controller reads theuser-defined base address for the transmit and receivedescriptor rings, which must be on an 8-byte boundary,as well as the number of entries contained in thedescriptor rings. By default, a maximum of 128 ringentries is permitted when utilizing the initializationblock, which uses values of TLEN and RLEN to specify

56 Am79C961A


the transmit and receive descriptor ring lengths. How-ever, the ring lengths can be manually defined (up to65535) by writing the transmit and receive ring lengthregisters (CSR76,78) directly.

Each ring entry contains the following information:

The address of the actual message data buffer inuser or host memory

The length of the message buffer

Status information indicating the condition of thebuffer

Receive descriptor entries are similar (but not identical)to transmit descriptor entries. Both are composed offour registers, each 16 bits wide for a total of 8 bytes.

To permit the queuing and de-queuing of messagebuffers, ownership of each buffer is allocated to eitherthe PCnet-ISA II controller or the host. The OWN bitwithin the descriptor status information, either TMD or

RMD (see section on TMD or RMD), is used for thispurpose. “Deadly Embrace” conditions are avoided bythe ownership mechanism. Only the owner is permittedto relinquish ownership or to write to any field in thedescriptor entry. A device that is not the current ownerof a descriptor entry cannot assume ownership orchange any field in the entry.

Descriptor Ring Access Mechanism

At initialization, the PCnet-ISA II controller reads thebase address of both the transmit and receive descrip-tor rings into CSRs for use by the PCnet-ISA II control-ler during subsequent operation.

When transmit and receive functions begin, the baseaddress of each ring is loaded into the current descrip-tor address registers and the address of the nextdescriptor entry in the transmit and receive rings iscomputed and loaded into the next descriptor addressregisters.

Am79C961A 57


Polling

When there is no channel activity and there is no pre-or post-receive or transmit activity being performed bythe PCnet-ISA II controller then the PCnet-ISA II con-troller will periodically poll the current receive andtransmit descriptor entries in order to ascertain theirownership. If the DPOLL bit in CSR4 is set, then thetransmit polling function is disabled.

A typical polling operation consists of the following: ThePCnet-ISA II controller will use the current receivedescriptor address stored internally to vector to theappropriate Receive Descriptor Table Entry (RDTE). Itwill then use the current transmit descriptor address(stored internally) to vector to the appropriate TransmitDescriptor Table Entry (TDTE). These accesses will bemade to RMD1 and RMD0 of the current RDTE andTMD1 and TMD0 of the current TDTE at periodic poll-

Initialization Block

24-Bit Base Address Pointer to

Initialization Block

IADR[15:0]IADR[23:16]RES

CSR1CSR2

TDRA[15:0]

MODEPADR[15:0]

PADR[31:16]PADRF[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLEN RES RDRA[23:16]

TLEN RES TDRA[23:16]

RCV Buffers

•••

RX DESCRIPTOR RINGS

RMD0RMD1 RMD2 RMD3

RCV Descriptor Ring

N N NN

••

•

1st desc. start

2nd desc. start

RMD0

XMT Buffers

•••

RX DESCRIPTOR RINGS

TMD0TMD1 TMD2 TMD3

RX DESCRIPTOR RINGS

XMT Descriptor Ring

M M MM

••

•

1st desc. start

2nd desc. start

TMD0

Data Buffer 1

Data Buffer 2

Data Buffer

N

Data Buffer 1

Data Buffer 2

Data Buffer

M

19364A-11Initialization Block and Descriptor Rings

58 Am79C961A


ing intervals. All information collected during pollingactivity will be stored internally in the appropriateCSRs. (i.e. CSR18–19, CSR40, CSR20–21, CSR42,CSR50, CSR52). Unowned descriptor status will beinternally ignored.

A typical receive poll occurs under the followingconditions:

1. PCnet-ISA II controller does not possess ownershipof the current RDTE andthe poll time has elapsed and RXON = 1,

or

2. PCnet-ISA II controller does not possess ownershipof the next RDTE andthe poll time has elapsed andRXON = 1,

If RXON = 0, the PCnet-ISA II controller will never pollRDTE locations.

If RXON = 1, the system should always have at leastone RDTE available for the possibility of a receiveevent. When there is only one RDTE, there is no pollingfor next RDTE.

A typical transmit poll occurs under the followingconditions:

1. PCnet-ISA II controller does not possess ownershipof the current TDTE andDPOLL = 0 andTXON = 1 andthe poll time has elapsed,

or

2. PCnet-ISA II controller does not possess ownershipof the current TDTE andDPOLL = 0 andTXON = 1 anda packet has just been received,

or

3. PCnet-ISA II controller does not possess ownershipof the current TDTE andDPOLL = 0 andTXON = 1 anda packet has just been transmitted.

The poll time interval is nominally defined as 32,768crystal clock periods, or 1.6 ms. However, the poll timeregister is controlled internally by microcode, so anyother microcode controlled operation will interrupt theincrementing of the poll count register. For example,when a receive packet is accepted by the PCnet-ISA IIcontroller, the device suspends execution of thepoll-time-incrementing microcode so that a receivemicrocode rout ine may instead be executed.Poll-time-incrementing code is resumed when thereceive operation has completely finished. Note, how-

ever, that following the completion of any receive ortransmit operation, a poll operation will always be per-formed. The poll time count register is never reset. Notethat if a non-default is desired, then a strict sequenceof setting the INIT bit in CSR0, waiting for the IDON bitin CSR0, then writing to CSR47, and then setting STRTin CSR0 must be observed, otherwise the default valuewill not be overwritten. See the CSR47 section fordetails.

Setting the TDMD bit of CSR0 will cause the microcodecontroller to exit the poll counting code and immedi-ately perform a polling operation. If RDTE ownershiphas not been previously established, then an RDTEpoll will be performed ahead of the TDTE poll.

Transmit Descriptor Table Entry (TDTE)

If, after a TDTE access, the PCnet-ISA II controllerfinds that the OWN bit of that TDTE is not set, then thePCnet-ISA II controller resumes the poll time count andre-examines the same TDTE at the next expiration ofthe poll time count.

If the OWN bit of the TDTE is set, but STP = 0, thePCnet-ISA II controller will immediately request the busin order to reset the OWN bit of this descriptor; this con-dition would normally be found following a LCOL orRETRY error that occurred in the middle of a transmitpacket chain of buffers. After resetting the OWN bit ofthis descriptor, the PCnet-ISA II controller will againimmediately request the bus in order to access the nextTDTE location in the ring.

If the OWN bit is set and the buffer length is 0, the OWNbit will be reset. In the LANCE the buffer length of 0 isinterpreted as a 4096-byte buffer. It is acceptable tohave a 0 length buffer on transmit with STP=1 orSTP=1 and ENP = 1. It is not acceptable to have 0length buffer with STP = 0 and ENP = 1.

If the OWN bit is set and the start of packet (STP) bit isset, then microcode control proceeds to a routine thatwill enable transmit data transfers to the FIFO.

If the transmit buffers are data chained (ENP = 0 in thefirst buffer), then the PCnet-ISA II controller will lookahead to the next transmit descriptor after it has per-formed at least one transmit data transfer from the firstbuffer. More than one transmit data transfer may possi-bly take place, depending upon the state of the trans-mitter. The transmit descriptor look ahead reads TMD0first and TMD1 second. The contents of TMD0 andTMD1 will be stored in Next TX Descriptor Address(CSR32), Next TX Byte Count (CSR66) and Next TXStatus (CSR67) regardless of the state of the OWN bit.This transmit descriptor lookahead operation isperformed only once.

If the PCnet-ISA II controller does not own the nextTDTE (i.e. the second TDTE for this packet), then it willcomplete transmission of the current buffer and then

Am79C961A 59


update the status of the current (first) TDTE with theBUFF and UFLO bits being set. If DXSUFLO is 0 (bit 6CSR3), then this will cause the transmitter to be dis-abled (CSR0, TXON = 0). The PCnet-ISA II controllerwill have to be restarted to restore the transmit function.The situation that matches this description implies thatthe system has not been able to stay ahead of thePCnet-ISA II controller in the transmit descriptor ringand therefore, the condition is treated as a fatal error.To avoid this situation, the system should always setthe transmit chain descriptor own bits in reverse order.

If the PCnet-ISA II controller does own the secondTDTE in a chain, it will gradually empty the contents ofthe first buffer (as the bytes are needed by the transmitoperation), perform a single-cycle DMA transfer toupdate the status (reset the OWN bit in TMD1) of thefirst descriptor, and then it may perform one data DMAaccess on the second buffer in the chain before execut-ing another lookahead operation. (i.e. a lookahead tothe third descriptor).

The PCnet-ISA II controller can queue up to two pack-ets in the transmit FIFO. Call them packet “X” andpacket “Y”, where “Y” is after “X”. Assume that packet“X” is currently being transmitted. Because thePCnet-ISA II controller can perform lookahead datatransfer over an ENP, it is possible for the PCnet-ISA IIcontroller to update a TDTE in a buffer belonging topacket “Y” while packet “X” is being transmitted ifpacket “Y” uses data chaining. This operation will resultin non-sequential TDTE accesses as packet “X” com-pletes transmission and the PCnet-ISA II controllerwrites out its status, since packet “X”’s TDTE is beforethe TDTE accessed as part of the lookahead datatransfer from packet “Y”.

This should not cause any problem for properly writtensoftware which processes buffers in sequence, waitingfor ownership before proceeding.

If an error occurs in the transmission before all of thebytes of the current buffer have been transferred, thenTMD2 and TMD1 of the current buffer will be written; inthat case, data transfers from the next buffer will notcommence. Instead, following the TMD2/TMD1 update,the PCnet-ISA II controller will go to the next transmitpacket, if any, skipping over the rest of the packet whichexperienced an error, including chained buffers.

This is done by returning to the polling microcodewhere it will immediately access the next descriptorand find the condition OWN = 1 and STP = 0 asdescribed earlier. In that case, the PCnet-ISA II control-ler will reset the own bit for this descriptor and continuein like manner until a descriptor with OWN = 0 (no moretransmit packets in the ring) or OWN = 1 and STP = 1(the first buffer of a new packet) is reached.

At the end of any transmit operation, whether success-ful or with errors, and the completion of the descriptor

updates, the PCnet-ISA II controller will always performanother poll operation. As described earlier, this polloperation will begin with a check of the current RDTE,unless the PCnet-ISA II controller already owns thatdescriptor. Then the PCnet-ISA II controller willproceed to polling the next TDTE. If the transmitdescriptor OWN bit has a zero value, then thePCnet-ISA II controller will resume poll time countincrementation. If the transmit descriptor OWN bit hasa value of ONE, then the PCnet-ISA II controller willbegin filling the FIFO with transmit data and initiate atransmission. This end-of-operation poll avoids insert-ing poll time counts between successive transmitpackets.

Whenever the PCnet-ISA II controller completes atransmit packet (either with or without error) and writesthe status information to the current descriptor, then theTINT bit of CSR0 is set to indicate the completion of atransmission. This causes an interrupt signal if theIENA bit of CSR0 has been set and the TINTM bit ofCSR3 is reset.

Receive Descriptor Table Entry (RDTE)

If the PCnet-ISA II controller does not own both the cur-rent and the next Receive Descriptor Table Entry, thenthe PCnet-ISA II controller will continue to poll accord-ing to the polling sequence described above. If thereceive descriptor ring length is 1, there is no nextdescriptor, and no look ahead poll will take place.

If a poll operation has revealed that the current and thenext RDTE belongs to the PCnet-ISA II controller, thenadditional poll accesses are not necessary. Future polloperations will not include RDTE accesses as long asthe PCnet-ISA II controller retains ownership to the cur-rent and the next RDTE.

When receive activity is present on the channel, thePCnet-ISA II controller waits for the complete addressof the message to arrive. It then decides whether toaccept or reject the packet based on all active address-ing schemes. If the packet is accepted the PCnet-ISAII controller checks the current receive buffer statusregister CRST (CSR40) to determine the ownership ofthe current buffer.

If ownership is lacking, then the PCnet-ISA II controllerwill immediately perform a (last ditch) poll of the currentRDTE. If ownership is still denied, then the PCnet-ISAII controller has no buffer in which to store the incomingmessage. The MISS bit will be set in CSR0 and aninterrupt will be generated if IENA = 1 (CSR0) andMISSM = 0 (CSR3). Another poll of the current RDTEwill not occur until the packet has finished.

If the PCnet-ISA II controller sees that the last poll(either a normal poll or the last-ditch effort described inthe above paragraph) of the current RDTE shows validownership, then it proceeds to a poll of the next RDTE.

60 Am79C961A


Following this poll, and regardless of the outcome ofthis poll, transfers of receive data from the FIFO maybegin.

Regardless of ownership of the second receivedescriptor, the PCnet-ISA II controller will continue toperform receive data DMA transfers to the first buffer,using burst-cycle DMA transfers. If the packet lengthexceeds the length of the first buffer, and thePCnet-ISA II controller does not own the second buffer,ownership of the current descriptor will be passed backto the system by writing a zero to the OWN bit of RMD1and status will be written indicating buffer (BUFF = 1)and possibly overflow (OFLO = 1) errors.

If the packet length exceeds the length of the first (cur-rent) buffer, and the PCnet-ISA II controller does ownthe second (next) buffer, ownership will be passed backto the system by writing a zero to the OWN bit of RMD1when the first buffer is full. Receive data transfers to thesecond buffer may occur before the PCnet-ISA II con-troller proceeds to look ahead to the ownership of thethird buffer. Such action will depend upon the state ofthe FIFO when the status has been updated on the firstdescriptor. In any case, lookahead will be performed tothe third buffer and the information gathered will bestored in the chip, regardless of the state of the owner-ship bit. As in the transmit flow, lookahead operationsare performed only once.

This activity continues until the PCnet-ISA II controllerrecognizes the completion of the packet (the last byte ofthis receive message has been removed from the FIFO).The PCnet-ISA II controller will subsequently update thecurrent RDTE status with the end of packet (ENP) indi-cation set, write the message byte count (MCNT) of thecomplete packet into RMD2 and overwrite the “current”entries in the CSRs with the “next” entries.

Media Access ControlThe Media Access Control engine incorporates theessential protocol requirements for operation of a com-pliant Ethernet/802.3 node, and provides the interfacebetween the FIFO sub-system and the ManchesterEncoder/Decoder (MENDEC).

This section describes operation of the MAC enginewhen operating in Half Duplex mode. When in HalfDuplex mode, the MAC engine is fully compliant to Sec-tion 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard 1990Second Edition) and ANSI/IEEE 802.3 (1985). Whenoperating in Full Duplex mode, the MAC engine behaviorchanges as described in the Full Duplex Operation sec-tion.

The MAC engine provides programmable enhancedfeatures designed to minimize host supervision and preor post-message processing. These features includethe ability to disable retries after a collision, dynamicFCS generation on a packet-by-packet basis, and auto-

matic pad field insertion and deletion to enforceminimum frame size attributes.

The two primary attributes of the MAC engine are:

Transmit and receive message data encapsulation

— Framing (frame boundary delimitation, framesynchronization)

— Addressing (source and destination addresshandling)

— Error detection (physical medium transmissionerrors)

Media access management

— Medium allocation (collision avoidance)

— Contention resolution (collision handling)

Transmit and Receive Message Data Encapsulation

The MAC engine provides minimum frame sizeenforcement for transmit and receive packets. WhenAPAD_XMT = 1 (bit 11 in CSR4), transmit messageswill be padded with sufficient bytes (containing 00h) toensure that the receiving station will observe an infor-mation field (destination address, source address,length/type, data and FCS) of 64-bytes. WhenASTRP_RCV = 1 (bit 10 in CSR4), the receiver willautomatically strip pad bytes from the received mes-sage by observing the value in the length field, andstripping excess bytes if this value is below the mini-mum data size (46 bytes). Both features can be inde-pendently over-ridden to allow illegally short (less than64 bytes of packet data) messages to be transmittedand/or received. The use of these features reduce busbandwidth usage because the pad bytes are not trans-ferred to or from host memory.

Framing (frame boundary delimitation, framesynchronization)

The MAC engine will autonomously handle the con-struction of the transmit frame. Once the Transmit FIFOhas been filled to the predetermined threshold (set byXMTSP in CSR80), and providing access to the chan-nel is currently permitted, the MAC engine will com-mence the 7-byte preamble sequence (10101010b,where first bit transmitted is a 1). The MAC engine willsubsequently append the Start Frame Delimiter (SFD)byte (10101011b) followed by the serialized data fromthe Transmit FIFO. Once the data has been completed,the MAC engine will append the FCS (most significantbit first) which was computed on the entire data portionof the message.

Note that the user is responsible for the correct order-ing and content in each of the fields in the frame,including the destination address, source address,length/type and packet data.

The receive section of the MAC engine will detect anincoming preamble sequence and lock to the encoded

Am79C961A 61


clock. The internal MENDEC will decode the serial bitstream and present this to the MAC engine. The MACwill discard the first 8 bits of information before search-ing for the SFD sequence. Once the SFD is detected,all subsequent bits are treated as part of the frame. TheMAC engine will inspect the length field to ensure min-imum frame size, strip unnecessary pad characters (ifenabled), and pass the remaining bytes through theReceive FIFO to the host. If pad stripping is performed,the MAC engine will also strip the received FCS bytes,although the normal FCS computation and checkingwill occur. Note that apart from pad stripping, the framewill be passed unmodified to the host. If the length fieldhas a value of 46 or greater, the MAC engine will notattempt to validate the length against the number ofbytes contained in the message.

If the frame terminates or suffers a collision before64 bytes of information (after SFD) have beenreceived, the MAC engine will automatically delete thef rame f rom the Rece ive F IFO, w i thout hos tintervention.

Addressing (source and destination addresshandling)

The first 6 bytes of information after SFD will be inter-preted as the destination address field. The MACengine provides facilities for physical, logical, andbroadcast address reception. In addition, multiplephysical addresses can be constructed (perfectaddress filtering) using external logic in conjunctionwith the EADI interface.

Error detection (physical medium transmissionerrors)

The MAC engine provides several facilities whichreport and recover from errors on the medium. In addi-tion, the network is protected from gross errors due toinability of the host to keep pace with the MAC engineactivity.

On completion of transmission, the following transmitstatus is available in the appropriate TMD and CSRareas:

The exact number of transmission retry attempts(ONE, MORE, or RTRY).

Whether the MAC engine had to Defer (DEF) due tochannel activity.

Loss of Carrier, indicating that there was an inter-ruption in the ability of the MAC engine to monitor itsown transmission. Repeated LCAR errors indicatea potent ial ly faul ty t ransceiver or networkconnection.

Late Collision (LCOL) indicates that the transmis-sion suffered a collision after the slot time. This isindicative of a badly configured network. Late colli-

sions should not occur in a normal operating net-work.

Collision Error (CERR) indicates that the trans-ceiver did not respond with an SQE Test messagewithin the predetermined time after a transmissioncompleted. This may be due to a failed transceiver,disconnected or faulty transceiver drop cable, or thefact the transceiver does not support this feature (orthe feature is disabled).

In addition to the reporting of network errors, the MACengine will also attempt to prevent the creation of anynetwork error due to the inability of the host to servicethe MAC engine. During transmission, if the host failsto keep the Transmit FIFO filled sufficiently, causing anunderflow, the MAC engine will guarantee the messageis either sent as a runt packet (which will be deleted bythe receiving station) or has an invalid FCS (which willalso cause the receiver to reject the message).

The status of each receive message is available in theappropriate RMD and CSR areas. FCS and Framingerrors (FRAM) are reported, although the receivedframe is still passed to the host. The FRAM error willonly be reported if an FCS error is detected and thereare a non-integral number of bits in the message. TheMAC engine will ignore up to seven additional bits atthe end of a message (dribbling bits), which can occurunder normal network operating conditions. The recep-tion of eight additional bits will cause the MAC engineto de-serialize the entire byte, and will result in thereceived message and FCS being modified.

The PCnet-ISA II controller can handle up to 7 dribblingbits when a received packet terminates. During thereception, the CRC is generated on every serial bit(including the dribbling bits) coming from the cable,although the internally saved CRC value is onlyupdated on the eighth bit (on each byte boundary). Theframing error is reported to the user as follows:

1. If the number of the dribbling bits are 1 to 7 andthere is no CRC error, then there is no Framing error(FRAM = 0).

2. If the number of the dribbling bits are less than 8and there is a CRC error, then there is also aFraming error (FRAM = 1).

3. If the number of dribbling bits = 0, then there is noFraming error. There may or may not be a CRC(FCS) error.

Counters are provided to report the Receive CollisionCount and Runt Packet Count used for network statis-tics and utilization calculations.

Note that if the MAC engine detects a received packetwhich has a 00b pattern in the preamble (after the first8 bits, which are ignored), the entire packet will beignored. The MAC engine will wait for the network to goinactive before attempting to receive the next packet.

62 Am79C961A


Media Access Management

The basic requirement for all stations on the network isto provide fairness of channel allocation. The 802.3/Ethernet protocol defines a media access mechanismwhich permits all stations to access the channel withequality. Any node can attempt to contend for the chan-nel by waiting for a predetermined time (Inter PacketGap interval) after the last activity, before transmittingon the medium. The channe l i s a mul t id ropcommunications medium (with various topological con-figurations permitted) which allows a single station totransmit and all other stations to receive. If two nodessimultaneously contend for the channel, their signalswill interact, causing loss of data (defined as a collision).It is the responsibility of the MAC to attempt to avoid andrecover from a collision, to guarantee data integrity forthe end-to-end transmission to the receiving station.

Medium Allocation (collision avoidance)

The IEEE 802.3 Standard (ISO/IEC 8802-3 1990)requires that the CSMA/CD MAC monitor the mediumtraffic by looking for carrier activity. When carrier isdetected the medium is considered busy, and the MACshould defer to the existing message.

The IEEE 802.3 Standard also allows optional two partdeferral after a receive message.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:

“Note: It is possible for the PLS carrier senseindication to fail to be asserted during a colli-sion on the media. If the deference processsimply times the interpacket gap based on thisindication it is possible for a short interFramegap to be generated, leading to a potential re-ception failure of a subsequent frame. To en-hance system robustness the following option-al measures, as specified in 4.2.8, are recom-mended when InterFrameSpacingPart1 isother than zero:

(1) Upon completing a transmission, start timingthe interpacket gap, as soon as transmittingand carrier Sense are both false.

(2) When timing an interpacket gap following re-ception, reset the interpacket gap timing if car-rier Sense becomes true during the first 2/3 ofthe interpacket gap timing interval. During thefinal 1/3 of the interval the timer shall not be re-set to ensure fair access to the medium. An ini-tial period shorter than 2/3 of the interval ispermissible including zero.”

The MAC engine implements the optional receive twopart de fe r ra l a lgo r i thm, w i th a fi rs t pa r tinter-frame-spacing time of 6.0 µs. The second part ofthe inter-frame-spacing interval is therefore 3.6 µs.

The PCnet-ISA II controller will perform the two-partdeferral algorithm as specified in Section 4.2.8 (Pro-cess Deference). The Inter Packet Gap (IPG) timer will

start timing the 9.6 µs InterFrameSpacing after thereceive carrier is de-asserted. During the first partdeferral (InterFrameSpacingPar t1 – IFS1) thePCnet-ISA II controller will defer any pending transmitframe and respond to the receive message. The IPGcounter will be reset to zero continuously until the car-rier de-asserts, at which point the IPG counter willresume the 9.6 µs count once again. Once the IFS1period of 6.0 µs has elapsed, the PCnet-ISA II control-ler wi l l begin t iming the second part deferral(InterFrameSpacingPart2 – IFS2) of 3.6 µs. Once IFS1has completed, and IFS2 has commenced, thePCnet-ISA II controller will not defer to a receive packetif a transmit packet is pending. This means that thePCnet-ISA II controller will not attempt to receive thereceive packet, since it will start to transmit, and gener-ate a collision at 9.6 µs. The PCnet-ISA II controller willguarantee to complete the preamble (64-bit) and jam(32-bit) sequence before ceasing transmission andinvoking the random backoff algorithm.

In addition, transmit two part deferral is implementedas an option which can be disabled using theDXMT2PD bit (CSR3). Two-part deferral after transmis-sion is useful for ensuring that severe IPG shrinkagecannot occur in specific circumstances, causing atransmit message to follow a receive message soclosely as to make them indistinguishable.

During the time period immediately after a transmis-sion has been completed, the external transceiver (inthe case of a standard AUI connected device), shouldgenerate the SQE Test message (a nominal 10 MHzburst of 5-15 bit times duration) on the CI± pair (within0.6 µs – 1.6 µs after the transmission ceases). Duringthe time period in which the SQE Test message isexpected the PCnet-ISA II controller will not respond toreceive carrier sense.

See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1):

“At the conclusion of the output function, theDTE opens a time window during which it ex-pects to see the signal_quality_error signal as-serted on the Control In circuit. The time win-dow begins when the CARRIER_STATUS be-comes CARRIER_OFF. If execution of the out-put function does not cause CARRIER_ON tooccur, no SQE test occurs in the DTE. The du-ration of the window shall be at least 4.0 µs butno more than 8.0 µs. During the time windowthe Carrier Sense Function is inhibited.”

The PCnet-ISA II controller implements a carrier sense“blinding” period within 0 – 4.0 µs from de-assertion ofcarrier sense after transmission. This effectively meansthat when transmit two par t deferral is enabled(DXMT2PD is cleared) the IFS1 time is from 4 µs to 6µs after a transmission. However, since IPG shrinkagebelow 4 µs will rarely be encountered on a correctlyconfigured network, and since the fragment size will be

Am79C961A 63


larger than the 4 µs blinding window, then the IPGcounter will be reset by a worst case IPG shrinkage/fragment scenario and the PCnet-ISA II controller willdefer its transmission. In addition, the PCnet-ISA IIcontroller will not restart the “blinding” period if carrieris detected within the 4.0 µs – 6.0 µs IFS1 period, butwill commence timing of the entire IFS1 period.

Contention resolution (collision handling)

Collision detection is performed and reported to theMAC engine by the integrated Manchester Encoder/Decoder (MENDEC).

If a collision is detected before the complete preamble/SFD sequence has been transmitted, the MAC Enginewill complete the preamble/SFD before appending thejam sequence. If a collision is detected after the pream-ble/SFD has been completed, but prior to 512 bitsbeing transmitted, the MAC Engine will abort the trans-mission, and append the jam sequence immediately.The jam sequence is a 32-bit all zeroes pattern.

The MAC Engine will attempt to transmit a frame a totalof 16 times (initial attempt plus 15 retries) due to nor-mal collisions (those within the slot time). Detection ofco l l i s ion w i l l cause the t ransmiss ion to bere-scheduled, dependent on the backoff time that theMAC Engine computes. If a single retry was required,the ONE bit will be set in the Transmit Frame Status(TMD1 in the Transmit Descriptor Ring). If more thanone retry was required, the MORE bit will be set. If all16 attempts experienced collisions, the RTRY bit (inTMD2) will be set (ONE and MORE will be clear), andthe transmit message will be flushed from the FIFO. Ifretries have been disabled by setting the DRTY bit inthe MODE register (CSR15), the MAC Engine willabandon transmission of the frame on detection of thefirst collision. In this case, only the RTRY bit will be setand the transmit message will be flushed from theFIFO.

If a collision is detected after 512 bit times have beentransmitted, the collision is termed a late collision. TheMAC Engine will abort the transmission, append thejam sequence, and set the LCOL bit. No retry attemptwill be scheduled on detection of a late collision, andthe FIFO will be flushed.

The IEEE 802.3 Standard requires use of a “truncatedbinary exponential backoff” algorithm which provides acontrolled pseudo-random mechanism to enforce thecollision backoff interval, before re-transmission isattempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming),the CSMA/CD sublayer delays before attempt-ing to re-transmit the frame. The delay is an in-teger multiple of slot Time. The number of slottimes to delay before the nth re-transmission

attempt is chosen as a uniformly distributedrandom integer r in the range:

0 ≤ r < 2k, where k = min (n,10).”

The PCnet-ISA II controller provides an alternativealgorithm, which suspends the counting of the slottime/IPG during the time that receive carrier sense isdetected. This algorithm aids in networks where largenumbers of nodes are present, and numerous nodescan be in collision. The algorithm effectively acceler-ates the increase in the backoff time in busy networks,and allows nodes not involved in the collision to accessthe channel while the colliding nodes await a reductionin channel activity. Once channel activity is reduced,the nodes resolving the collision time out their slot timecounters as normal.

Manchester Encoder/Decoder (MENDEC)The integrated Manchester Encoder/Decoder providesthe PLS (Physical Layer Signaling) functions requiredfor a fully compliant IEEE 802.3 station. The MENDECprovides the encoding function for data to be transmit-ted on the network using the high accuracy on-boardoscillator, driven by either the crystal oscillator or an ex-ternal CMOS-level compatible clock. The MENDECalso provides the decoding function from data receivedfrom the network. The MENDEC contains a Power OnReset (POR) circuit, which ensures that all analog por-tions of the PCnet-ISA II controller are forced into theircorrect state during power-up, and prevents erroneousdata transmission and/or reception during this time.

External Crystal Characteristics

When using a crystal to drive the oscillator, the crystalspecification shown in the specification table may beused to ensure less than ±0.5 ns jitter at DO±.

External Crystal Characteristics

Requires trimming crystal spec; no trim is 50 ppm total

Parameter Min Nom Max Unit

1. Parallel Resonant Frequency 20 MHz

2. Resonant Frequency Error (CL = 20 pF)

–50 +50 PPM

3.Change in Resonant Frequency With Respect To Temperature (0° – 70° C; CL = 20 pF)*

–40 +40 PPM

4. Crystal Capacitance 20 pF

5. Motional Crystal Capacitance (C1)

0.022 pF

6. Series Resistance 25 Ω

7. Shunt Capacitance 7 pF

8. Drive Level TBD mW

64 Am79C961A


External Clock Drive Characteristics

When driving the oscillator from an external clocksource, XTAL2 must be left floating (unconnected). Anexternal clock having the following characteristics mustbe used to ensure less than ±0.5 ns jitter at DO±.

MENDEC Transmit Path

The transmit section encodes separate clock and NRZdata input signals into a standard Manchester encodedserial bit stream. The transmit outputs (DO±) aredesigned to operate into terminated transmission lines.When operating into a 78 Ω terminated transmissionline, the transmit signaling meets the required outputlevels and skew for Cheapernet, Ethernet, andIEEE-802.3.

Transmitter Timing and Operation

A 20 MHz fundamental-mode crystal oscillator pro-vides the basic timing reference for the MENDEC por-tion of the PCnet-ISA II controller. The crystal input isdivided by two to create the internal transmit clock ref-erence. Both clocks are fed into the ManchesterEncoder to generate the transitions in the encodeddata stream. The internal transmit clock is used by theMENDEC to internally synchronize the Internal Trans-mit Data (ITXDAT) from the controller and InternalTransmit Enable (ITXEN). The internal transmit clock isalso used as a stable bit-rate clock by the receive sec-tion of the MENDEC and controller.

The oscillator requires an external 0.005% crystal, oran external 0.01% CMOS-level input as a reference.The accuracy requirements, if an external crystal isused, are tighter because allowance for the on-chiposcillator must be made to deliver a final accuracy of0.01%.

Transmission is enabled by the controller. As long asthe ITXEN request remains active, the serial output ofthe controller will be Manchester encoded and appearat DO±. When the internal request is dropped by thecontroller, the differential transmit outputs go to one oftwo idle states, dependent on TSEL in the ModeRegister (CSR15, bit 9):

Receive Path

The principal functions of the receiver are to signal thePCnet-ISA II controller that there is information on thereceive pair, and to separate the incoming Manchesterencoded data stream into clock and NRZ data.

The receiver section (see Receiver Block Diagram)consists of two parallel paths. The receive data path isa zero threshold, wide bandwidth line receiver. Thecarrier path is an offset threshold bandpass detectingline receiver. Both receivers share common biasnetworks to allow operation over a wide input commonmode range.

Input Signal Conditioning

Transient noise pulses at the input data stream arerejected by the Noise Rejection Filter. Pulse widthrejection is proportional to transmit data rate which isfixed at 10 MHz for Ethernet systems but which couldbe different for proprietary networks. DC inputs morenegative than minus 100 mV are also suppressed.

The Carrier Detection circuitry detects the presence ofan incoming data packet by discerning and rejectingnoise from expected Manchester data, and controls thestop and start of the phase-lock loop during clockacquisit ion. Clock acquisit ion requires a validManchester bit pattern of 1010b to lock onto the incom-ing message.

When input amplitude and pulse width conditions aremet at DI±, a clock acquisition cycle is initiated.

Clock Acquisition

When there is no activity at DI± (receiver is idle), thereceive oscillator is phase-locked to STDCLK. The firstnegative clock transition (bit cell center of first validManchester “0") after clock acquisition begins inter-rupts the receive oscillator. The oscillator is thenrestarted at the second Manchester “0" (bit time 4) andis phase-locked to it. As a result, the MENDECacquires the clock from the incoming Manchester bitpattern in 4 bit times with a “1010" Manchester bit pat-tern.

The internal receiver clock, IRXCLK, and the internalreceived data, IRXDAT, are enabled 1/4 bit time afterclock acquisition in bit cell 5. IRXDAT is at a HIGH statewhen the receiver is idle (no IRXCLK). IRXDAT how-ever, is undefined when clock is acquired and mayremain HIGH or change to LOW state whenever IRX-CLK is enabled. At 1/4 bit time through bit cell 5, thecontroller portion of the PCnet-ISA II controller seesthe first IRXCLK transition. This also strobes in theincoming fifth bit to the MENDEC as Manchester “1".IRXDAT may make a transition after the IRXCLK risingedge in bit cell 5, but its state is still undefined. TheManchester “1" at bit 5 is clocked to IRXDAT output at1/4 bit time in bit cell 6.

Clock Frequency: 20 MHz ±0.01%

Rise/Fall Time (tR/tF): < 6 ns from 0.5 V to VDD–0.5

XTAL1 HIGH/LOW Time (tHIGH/tLOW):

40 – 60% duty cycle

XTAL1 Falling Edge to Falling Edge Jitter:

< ±0.2 ns at 2.5 V input (VDD/2)

TSEL LOW:The idle state of DO± yields “zero” differential to operate transformer-coupled loads

TSEL HIGH:In this idle state, DO+ is positive with respect to DO– (logical HIGH).

Am79C961A 65


PLL Tracking

After clock acquisition, the phase-locked clock is com-pared to the incoming transition at the bit cell center(BCC) and the resulting phase error is applied to a cor-rect ion c i rcu i t . Th is c i rcu i t ensures that the

phase-locked clock remains locked on the receivedsignal. Individual bit cell phase corrections of theVoltage Controlled Oscillator (VCO) are limited to 10%of the phase difference between BCC and phase-locked clock.

Receiver Block Diagram

Carrier Tracking and End of Message

The carrier detection circuit monitors the DI± inputsafter IRXCRS is asserted for an end of message.IRXCRS de-asserts 1 to 2 bit times after the last posi-tive transition on the incoming message. This initiatesthe end of reception cycle. The time delay from the lastrising edge of the message to IRXCRS deassert allowsthe last bit to be strobed by IRXCLK and transferred tothe controller section, but prevents any extra bit(s) atthe end of message. When IRXCRS de-asserts anIRXCRS hold off timer inhibits IRXCRS assertion for atleast 2 bit times.

Data Decoding

The data receiver is a comparator with clocked outputto minimize noise sensitivity to the DI± inputs. Inputerror is less than ±35 mV to minimize sensitivity to inputrise and fall time. IRXCLK strobes the data receiveroutput at 1/4 bit time to determine the value of theManchester bit, and clocks the data out on IRXDAT onthe fol lowing IRXCLK. The data receiver alsogenerates the signal used for phase detector compari-son to the internal MENDEC voltage controlledoscillator (VCO).

Differential Input Terminations

The differential input for the Manchester data (DI±)should be externally terminated by two 40.2 Ω ±1%resistors and one optional common-mode bypasscapacitor, as shown in the Differential Input Terminationdiagram below. The differential input impedance, ZIDF,and the common-mode input impedance, ZICM, are

specified so that the Ethernet specification for cabletermination impedance is met using standard 1%resistor terminators. If SIP devices are used, 39 Ω isthe nearest usable equivalent value. The CI± differen-tial inputs are terminated in exactly the same way asthe DI± pair.

Collision Detection

A MAU detects the collision condition on the networkand generates a differential signal at the CI± inputs.This collision signal passes through an input stagewhich detects signal levels and pulse duration. Whenthe signal is detected by the MENDEC it sets the inter-nal collision signal, ICLSN, HIGH. The condition contin-ues for approximately 1.5 bit times after the lastLOW-to-HIGH transition on CI±.

Data Receiver

Manchester Decoder

Noise Reject Filter

Carrier Detect Circuit

*Internal signal

DI±IRXDAT*

IRXCLK*

IRXCRS*

19364A-12

PCnet-ISA II

DI+

DI

40.2 Ω 40.2 Ω

0.01 µF to 0.1 µF

AUI Isolation Transformer

Differential Input Termination

19364A-13

66 Am79C961A


Jitter Tolerance Definition

The MENDEC utilizes a clock capture circuit to align itsinternal data strobe with an incoming bit stream. Theclock acquisition circuitry requires four valid bits withthe values 1010b. Clock is phase-locked to the nega-tive transition at the bit cell center of the second “0" inthe pattern.

Since data is strobed at 1/4 bit time, Manchester tran-sitions which shift from their nominal placementthrough 1/4 bit time will result in improperly decodeddata. With this as the criteria for an error, a definition of“Jitter Handling” is:

The peak deviation approaching or crossing1/4 bit cell position from nominal input transi-tion, for which the MENDEC section willproperly decode data.


The AUI is the PLS (Physical Layer Signaling) to PMA(Physical Medium Attachment) interface which con-nects the DTE to a MAU. The differential interface pro-vided by the PCnet-ISA II controller is fully compliantwith Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).

After the PCnet-ISA II controller initiates a transmis-sion, it will expect to see data “looped-back” on the DI±pair (when the AUI port is selected). This will internallygenerate a “carrier sense”, indicating that the integrityof the data path to and from the MAU is intact, and thatthe MAU is operating correctly. This “carrier sense” sig-nal must be asserted within sometime before end oftransmission. If “carrier sense” does not become activein response to the data transmission, or becomes inac-tive before the end of transmission, the loss of carrier(LCAR) error bit will be set in the Transmit DescriptorRing (TMD3, bit 11) after the packet has beentransmitted.

Twisted Pair Transceiver (T-MAU)This section describes operation of the T-MAU whenoperating in the Half Duplex mode. When in HalfDuplex mode, the T-MAU implements the MediumAttachment Unit (MAU) functions for the Twisted PairMedium as specified by the supplement to IEEE 802.3standard (Type 10BASE-T). When operating in FullDuplex mode, the MAC engine behavior changes asdescribed in the Full Duplex Operation section. TheT-MAU provides twisted pair driver and receiver cir-cuits, including on-board transmit digital predistortionand receiver squelch, and a number of additional fea-tures including Link Status indication, AutomaticTwisted Pair Receive Polarity Detection/Correction andIndication, Receive Carrier Sense, Transmit Active andCollision Present indication.

Twisted Pair Transmit Function

The differential driver circuitry in the TXD± and TXP±pins provides the necessary electrical driving capabilityand the pre-distortion control for transmitting signalsover maximum length Twisted Pair cable, as specifiedby the 10BASE-T supplement to the IEEE 802.3 Stan-dard. The transmit function for data output meets thepropagation delays and jitter specified by the standard.

Twisted Pair Receive Function

The receiver complies with the receiver specificationsof the IEEE 802.3 10BASE-T Standard, including noiseimmunity and received signal rejection criteria (‘SmartSquelch’). Signals meeting these criteria appearing atthe RXD± differential input pair are routed to theMENDEC. The receiver function meets the propagationdelays and jitter requirements specified by the stan-dard. The receiver squelch level drops to half its thresh-old value after unsquelch to allow reception ofminimum amplitude signals and to offset carrier fade inthe event of worst case signal attenuation conditions.

Note that the 10BASE-T Standard defines the receiveinput amplitude at the external Media Dependent Inter-face (MDI). Filter and transformer loss are not speci-fied. The T-MAU receiver squelch levels are designedto account for a 1 dB insertion loss at 10 MHz for thetype of receive filters and transformers usually used.

Normal 10BASE-T compatible receive thresholds areinvoked when the LRT bit (CSR15, bit 9) is LOW. Whenthe LRT bit is set, the Low Receive Threshold option isinvoked, and the sensitivity of the T-MAU receiver isincreased. Increasing T-MAU sensitivity allows the useof lines longer than the 100 m target distance of stan-dard 10BASE-T (assuming typical 24 AWG cable).Increased receiver sensitivity compensates for theincreased signal attenuation caused by the additionalcable distance.

However, making the receiver more sensitive meansthat it is also more susceptible to extraneous noise, pri-marily caused by coupling from co-resident services(crosstalk). For this reason, end users may wish toinvoke the Low Receive Threshold option on 4-paircable only. Multi-pair cables within the same outersheath have lower crosstalk attenuation, and may allownoise emitted from adjacent pairs to couple into thereceive pair, and be of sufficient amplitude to falselyunsquelch the T-MAU.

Link Test Function

The link test function is implemented as specified by10BASE-T standard. During periods of transmit pairinactivity,’Link beat pulses’ will be periodically sent overthe twisted pair medium to constantly monitor mediumintegrity.

Am79C961A 67


When the link test function is enabled (DLNKTST bit inCSR15 is cleared), the absence of link beat pulses andreceive data on the RXD± pair will cause the TMAU togo into the Link Fail state. In the Link Fail state, datatransmission, data reception, data loopback and thecollision detection functions are disabled and remaindisabled until valid data or greater than 5 consecutivelink pulses appear on the RXD± pair. During Link Fail,the Link Status (LNKST indicated by LED0) signal isinactive. When the link is identified as functional, theLNKST signal is asserted, and LED0 output will beactivated. Upon power up or assertion of the RESETpin, the T-MAU will be forced into the Link Fail state.Reading the RESET register of the PCnet-ISA+ (soft-ware RESET) has no effect on the T-MAU

In order to inter-operate with systems which do notimplement Link Test, this function can be disabled bysetting the DLNKTST bit. With Link Test disabled, theData Driver, Receiver and Loopback functions as wellas Collision Detection remain enabled irrespective ofthe presence or absence of data or link pulses on theRXD± pair. Link Test pulses continue to be sent regard-less of the state of the DLNKTST bit.

Polarity Detection and Reversal

The T-MAU receive function includes the ability toinvert the polarity of the signals appearing at the RXD±pair if the polarity of the received signal is reversed(such as in the case of a wiring error). This featureallows data packets received from a reverse wiredRXD± input pair to be corrected in the T-MAU prior totransfer to the MENDEC. The polarity detection func-tion is activated following reset or Link Fail, and willreverse the receive polarity based on both the polarityof any previous link beat pulses and the polarity of sub-sequent packets with a valid End Transmit Delimiter(ETD).

When in the Link Fail state, the T-MAU will recognizelink beat pulses of either positive or negative polarity.Exit from the Link Fail state occurs at the reception of5 – 6 consecutive link beat pulses of identical polarity.On entry to the Link Pass state, the polarity of the last5 link beat pulses is used to determine the initialreceive polarity configuration and the receiver isreconfigured to subsequently recognize only link beatpulses of the previously recognized polarity.

Positive link beat pulses are defined as transmitted sig-nal with a positive amplitude greater than 585 mV witha pulse width of 60 ns – 200 ns. This positive excursionmay be followed by a negative excursion. This definitionis consistent with the expected received signal at a cor-rectly wired receiver, when a link beat pulse, which fitsthe template of Figure 14-12 of the 10BASE-T Stan-dard, is generated at a transmitter and passed through100 m of twisted pair cable.

Negative link beat pulses are defined as transmittedsignals with a negative amplitude greater than 585 mVwith a pulse width of 60 ns – 200 ns. This negativeexcursion may be followed by a positive excursion. Thisdefinition is consistent with the expected received sig-nal at a reverse wired receiver, when a link beat pulsewhich fits the template of Figure 14-12 in the10BASE-T Standard is generated at a transmitter andpassed through 100 m of twisted pair cable.

The polarity detection/correction algorithm will remain“armed” until two consecutive packets with valid ETD ofidentical polarity are detected. When “armed,” thereceiver is capable of changing the initial or previouspolarity configuration according to the detected ETDpolarity.

On receipt of the first packet with valid ETD followingreset or link fail, the T-MAU will use the inferred polarityinformation to configure its RXD± input, regardless ofits previous state. On receipt of a second packet with avalid ETD with correct polarity, the detection/correctionalgorithm will “lock-in” the received polarity. If the sec-ond (or subsequent) packet is not detected as confirm-ing the previous polarity decision, the most recentlydetected ETD polarity will be used as the default. Notethat packets with invalid ETD have no effect on updat-ing the previous polarity decision. Once two consecu-tive packets with valid ETD have been received, theT-MAU will lock the correction algorithm until either aLink Fail condition occurs or RESET is asserted.

During polarity reversal, an internal POL signal will beactive. During normal polarity conditions, this internalPOL signal is inactive. The state of this signal can beread by software and/or displayed by LED whenenabled by the LED control bits in the ISA Bus Config-uration Registers (ISACSR5, 6, 7).

Twisted Pair Interface Status

Three internal signals (XMT, RCV and COL) indicatewhether the T-MAU is transmitting, receiving, or in acollision state. These signals are internal signals andthe behavior of the LED outputs depends on how theLED output circuitry is programmed.

The T-MAU will power up in the Link Fail state and thenormal algorithm will apply to allow it to enter the LinkPass state. In the Link Pass state, transmit or receiveactivity will be indicated by assertion of RCV signalgoing active. If T-MAU is selected using the PORTSELbits in CSR15, when moving from AUI to T-MAU selec-tion, the T-MAU will be forced into the Link Fail state.

In the Link Fail state, XMT, RCV and COL are inactive.

Collision Detect Function

Activity on both twisted pair signals RXD± and TXD±constitutes a collision, thereby causing the COL signalto be asserted. (COL is used by the LED control cir-cuits) COL will remain asserted until one of the two col-

68 Am79C961A


liding signals changes from active to idle. COL staysactive for 2 bit times at the end of a collision.

Signal Quality Error (SQE) Test(Heartbeat) Function

The SQE function is disabled when the 10BASE-T portis selected and in Link Fail state.

Jabber Function

The Jabber function inhibits the twisted pair transmitfunction of the T-MAU if the TXD± circuit is active for anexcessive period (20 ms–150 ms). This prevents anyone node from disrupting the network due to a‘stuck-on’ or faulty transmitter. If this maximum transmittime is exceeded, the T-MAU transmitter circuitry is dis-abled, the JAB bit is set (CSR4, bit 1), and the COL sig-nal asserted. Once the transmit data stream to theT-MAU is removed, an “unjab” time of 250 ms – 750 mswill elapse before the T-MAU deasserts COL andre-enables the transmit circuitry.

Power Down

The T-MAU circuitry can be made to go into low powermode. This feature is useful in battery powered or lowduty cycle systems. The T-MAU will go into power downmode when RESET is active, coma mode is active, orthe T-MAU is not selected. Refer to the Power DownMode section for a description of the various powerdown modes.

Any of the three conditions listed above resets theinternal logic of the T-MAU and places the device intopower down mode. In this mode, the Twisted Pair driverpins (TXD±,TXP±) are asserted LOW, and the internalT-MAU status signals (LNKST, RCVPOL, XMT, RCVand COLLISION) are inactive.

Once the SLEEP pin is deasserted, the T-MAU will beforced into the Link Fail state. The T-MAU will move tothe Link Pass state only after 5–6 link beat pulses and/or a single received message is detected on the RXD±pair.

In Snooze mode, the T-MAU receive circuitry willremain enabled even while the SLEEP pin is drivenLOW.

The T-MAU circuitry will always go into power downmode if RESET is asserted, coma is enabled, or theT-MAU is not selected.

Full Duplex OperationThe PCnet-ISA II supports Full Duplex operation on the10BASE-T, AUI, and GPSI ports. Full Duplex operationallows simultaneous transmit and receive activity onthe TXD± and RXD± pairs of the 10BASE-T port, theDO± and DI± pairs of the AUI port, and the TXDAT andRXDAT pins of the GPSI port. It is enabled by the FDENand AUIFD bits located in ISACSR9. When operating in

the Full Duplex mode, the following changes to deviceoperation are made:

Bus Interface/Buffer Management Unit changes:

1. The first 64 bytes of every transmit frame are notpreserved in the transmit FIFO during transmissionof the first 512 bits transmitted on the network, asdescribed in the Transmit Exception Conditions sec-tion. Instead, when Full Duplex mode is active anda frame is being transmitted, the XMTFW bits(CSR80, bits 9, 8) always govern when transmitDMA is requested.

2. Successful reception of the first 64 bytes of everyreceive frame is not a requirement for Receive DMAto begin as described in the Receive ExceptionConditions section. Instead, receive DMA will berequested as soon as either the RCVFW threshold(CSR80 bits 12, 13) is reached or a complete validreceive frame is in the Receive FIFO, regardless oflength. This receive FIFO operation is identical towhen the RPA bit (CSR124, bit 3) is set during HalfDuplex mode operation.

MAC Engine changes:

1. Changes to the Transmit Deferral mechanism:

A. Transmission is not deferred while receive isactive.

B. The Inter Packet Gap (IPG) counter which gov-erns transmit deferral during the IPG betweenback-to-back transmits is started when transmitactivity for the first packet ends instead of whentransmit and carrier activity ends.

2. When the AUI or GPSI port is active, Loss of Carrier(LCAR) reporting is disabled (LCAR is still reportedwhen the 10BASE-T port is active if a packet istransmitted while in the Link Fail state).

3. The 4.0 µs carrier sense blinding period after atransmission during which the SQE test normallyoccurs is disabled.

4. When the AUI or GPSI port is active, the SQE Testerror (Collision Error, CERR) reporting is disabled(CERR is still reported when the 10BASE-T port isactive if a packet is transmitted while in the Link Failstate).

5. The collision indication input to the MAC Engine isignored.

T-MAU changes:

1. The transmit to receive loopback path in theT-MAU is disabled.

2. The collision detect circuit is disabled.

3. The “heartbeat” generation (SQE Test function)is disabled.

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EADI (External Address Detection Interface)This interface is provided to allow external address fil-tering. It is selected by setting the EADISEL bit inISACSR2. This feature is typically utilized for terminalservers, bridges and/or router type products. The useof external logic is required to capture the serial bitstream from the PCnet-ISA II controller, compare it witha table of stored addresses or identifiers, and performthe desired function.

The EADI interface operates directly from the NRZdecoded data and clock recovered by the Manchesterdecoder or input to the GPSI, allowing the externaladdress detection to be performed in parallel withframe reception and address comparison in the MACStation Address Detection (SAD) block.

SRDCLK is provided to allow clocking of the receive bitstream into the external address detection logic.SRDCLK runs only during frame reception activity.Once a received frame commences and data and clockare available, the EADI logic will monitor the alternating(“1,0") preamble pattern until the two ones of the StartFrame Delimiter (“1,0,1,0,1,0,1,1") are detected, atwhich point the SF/BD output will be driven HIGH.

After SF/BD is asserted the serial data from SRDshould be de-serialized and sent to a content address-able memory (CAM) or other address detection device.

To allow simple serial to parallel conversion, SF/BD isprovided as a strobe and/or marker to indicate thedelineation of bytes, subsequent to the SFD. This pro-vides a mechanism to allow not only capture and/or de-coding of the physical or logical (group) address, it alsofacilitates the capture of header information todetermine protocol and or inter-networking information.The EAR pin is driven LOW by the external addresscomparison logic to reject the frame.

If an internal address match is detected by comparisonwith either the Physical or Logical Address field, theframe will be accepted regardless of the condition ofEAR. Incoming frames which do not pass the internaladdress comparison will continue to be received. Thisallows approximately 58 byte times after the last desti-nation address bit is available to generate the EARsignal, assuming the device is not configured to acceptrunt packets. EAR will be ignored after 64 byte timesafter the SFD, and the frame will be accepted if EARhas not been asserted before this time. If Runt PacketAccept is configured, the EAR signal must begenerated prior to the receive message completion,which could be as short as 12 byte times (assuming 6bytes for source address, 2 bytes for length, no data, 4bytes for FCS) after the last bit of the destinationaddress is available. EAR must have a pulse width of atleast 200 ns.

Note that setting the PROM bit (CSR15, bit 15) willcause all receive frames to be received, regardless ofthe state of the EAR input.

If the DRCUPA bit (CSR15.B) is set and the logicaladdress (LADRF) is set to zero, only frames which arenot rejected by EAR will be received.

The EADI interface will operate as long as the STRT bitin CSR0 is set, even if the receiver and/or transmitterare disabled by software (DTX and DRX bits in CSR15set). This situation is useful as a power down mode inthat the PCnet-ISA II controller will not perform anyDMA operations; this saves power by not utilizing theISA bus driver circuits. However, external circuitrycould still respond to specific frames on the network tofacilitate remote node control.

The table below summarizes the operation of the EADIfeatures.

Internal/External Address Recognition Capabilities

General Purpose Serial Interface (GPSI)The PCnet-ISA II controller contains a GeneralPurpose Serial Interface (GPSI) designed for testingthe digital portions of the chip. The MENDEC, AUI, andtwisted pair interface are by-passed once the device isset up in the special “test mode” for accessing the GPSIfunctions. Although this access is intended only fortest ing the device, some users may find thenon-encoded data functions useful in some special

applications. Note, however, that the GPSI functionscan be accessed only when the PCnet-ISA II devicesoperate as a bus master.

The PCnet-ISA II GPSI signals are consistent with theLANCE digital serial interface. Since the GPSI func-tions can be accessed only through a special testmode, expect some loss of functionality to the devicewhen the GPSI is invoked. The AUI and 10BASE-Tanalog interfaces are disabled along with the internal

PROM EAR Required Timing Received Messages

1 X No timing requirements All Received Frames

0 1 No timing requirements All Received Frames

0 0 Low for 200 ns within 512 bits after SFD Physical/Logical Matches

70 Am79C961A


MENDEC logic. The LA (unlatched address) pins areremoved and become the GPSI signals, therefore, only20 bits of address space is available. The table belowshows the GPSI pin configuration:

To invoke the GPSI signals, follow the procedure below:

1. After reset or I/O read of Reset Address, write 10bto PORTSEL bits in CSR15.

2. Set the ENTST bit in CSR4

3. Set the GPSIEN bit in CSR124 (see note below)

(The pins LA17–LA23 will change function after thecompletion of the above three steps.)

4. Clear the ENTST bit in CSR4

5. Clear Media Select bits in ISACSR2

6. Define the PORTSEL bits in the MODE register(CSR15) to be 10b to define GPSI port. The MODEregister image is in the initialization block.

Note: LA pins will be tristated before writing to GPSIEN bit. After writing to GPSIEN, LA[17–21] will be inputs, LA[22–23] will be outputs.

GPSI Pin Configurations

Note:The GPSI Function is available only in the Bus Master Mode of operation.

GPSI FunctionGPSI

I/O TypeLANCE

GPSI PinPCnet-ISA II

GPSI PinPCnet-ISA IIPin Number

PCnet-ISA II Normal Pin Function

Receive Data I RX RXDAT 5 LA17

Receive Clock I RCLK SRDCLK 6 LA18

Receive Carrier Sense I RENA RXCRS 7 LA19

Collision I CLSN CLSN 9 LA20

Transmit Clock I TCLK STDCLK 10 LA21

Transmit Enable O TENA TXEN 11 LA22

Transmit Data O TX TXDAT 12 LA23

Am79C961A 71


IEEE 1149.1 Test Access Port InterfaceAn IEEE 1149.1 compatible boundary scan Test AccessPort is provided for board-level continuity test and diag-nostics. All digital input, output, and input/output pins aretested. Analog pins, including the AUI differential driver(DO±) and receivers (DI±, CI±), and the crystal input(XTAL1/XTAL2) pins, are tested. The T-MAU driversTXD±, TXP±, and receiver RXD± are also tested.

The following is a brief summary of the IEEE 1149.1compatible test functions implemented in thePCnet-ISA II controller.

Boundary Scan Circuit

The boundary scan test circuit requires four extra pins(TCK, TMS, TDI and TDO), defined as the Test AccessPort (TAP). It includes a finite state machine (FSM), aninstruction register, a data register array, and apower-on reset circuit. Internal pull-up resistors areprovided for the TDI, TCK, and TMS pins. The TCK pinmust not be left unconnected. The boundary scan cir-cuit remains active during sleep.

TAP FSM

The TAP engine is a 16-state FSM, driven by the TestClock (TCK) and the Test Mode Select (TMS) pins. ThisFSM is in its reset state at power-up or RESET. Anindependent power-on reset circuit is provided toensure the FSM is in the TEST_LOGIC_RESET stateat power-up.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements(BYPASS, EXTEST and SAMPLE instructions), three

additional instructions (IDCODE, TRIBYP and SETBYP)are provided to further ease board-level testing. Allunused instruction codes are reserved. See the tablebelow for a summary of supported instructions.

Instruction Register and Decoding Logic

After hardware or software RESET, the IDCODEinstruction is always invoked. The decoding logic givessignals to control the data flow in the DATA registersaccording to the current instruction.

Boundary Scan Register (BSR)

Each BSR cell has two stages. A flip-flop and a latchare used in the SERIAL SHIFT STAGE and the PARAL-LEL OUTPUT STAGE, respectively.

There are four possible operational modes in the BSR cell:

Other Data Registers

(1) BYPASS REG (1 BIT)(2) DEV ID REG (32 bits

IEEE 1149.1 Supported Instruction Summary

Power Saving ModesThe PCnet-ISA II controller supports two hardwarepower-savings modes. Both are entered by assertingthe SLEEP pin LOW.

In coma mode, the PCnet-ISA II controller will go intodeep sleep with no support to automatically wake itselfup. Sleep mode is enabled when the AWAKE bit in

ISACSR2 is reset. This mode is the default powerdownmode.

In Snooze mode, enabled by setting the AWAKE bit inISACSR2 and driving the SLEEP pin LOW, the T-MAUreceive circuitry will remain enabled even while theSLEEP pin is driven LOW. The LED0 output will alsocontinue to function, indicating a good 10BASE-T link if

1 Capture2 Shift3 Update4 System Function

Bits 31–28: Version

Bits 27–12: Part number (2261h)

Bits 11–1: Manufacturer ID. The 11 bitmanufacturer ID code for AMD is00000000001 according to JEDECPublication 106-A.

Bit 0: Always a logic 1

InstructionName Description

SelectedData Reg Mode

InstructionCode

EXTEST External Test BSR Test 0000

IDCODE ID Code Inspection ID REG Normal 0001

SAMPLE Sample Boundary BSR Normal 0010

TRIBYP Force Tristate Bypass Normal 0011

SETBYP Control Boundary to 1/0 Bypass Test 0100

BYPASS Bypass Scan Bypass Normal 1111

72 Am79C961A


there are link beat pulses or valid frames present. ThisLED0 pin can be used to drive a LED and/or externalhardware that directly controls the SLEEP pin of thePCnet-ISA II controller. This configuration effectivelywakes the system when there is any activity on the10BASE-T link.

Access Operations (Software)We begin by describing how byte and word data areaddressed on the ISA bus, including conversion cycleswhere 16-bit accesses are turned into 8-bit accessesbecause the resource accessed did not support 16-bitoperations. Then we describe how registers and otherresources are accessed. This section is for the deviceprogrammer, while the next section (bus cycles) is forthe hardware designer.

I/O Resources

The PCnet-ISA II controller has both I/O and memoryresources. In the I/O space the resources are orga-nized as indicated in the following table:

The PCnet-ISA II controller does not respond to anyaddresses outside of the offset range 0-17h. I/O offsets18h and up are not used by the PCnet-ISA II controller.

I/O Register Access

The register address port (RAP) is shared by the regis-ter data port (RDP) and the ISACSR data port (IDP) tosave registers. To access the Ethernet controller’s RDPor IDP, the RAP should be written first, followed by theread or write access to the RDP or IDP. I/O registeraccesses should be coded as 16-bit accesses, even ifthe PCnet-ISA II controller is hardware configured for8-bit I/O bus cycles. It is acceptable (and transparent)for the motherboard to turn a 16-bit software accessinto two separate 8-bit hardware bus cycles. The moth-erboard accesses the low byte before the high byte andthe PCnet-ISA II controller has circuitry to specificallysupport this type of access.

The reset register causes a reset when read. Any valuewill be accepted and the cycle may be 8 or 16 bits wide.Writes are ignored.

All PCnet-ISA II controller register accesses should becoded as 16-bit operations.

“Note that the RAP is cleared on Reset.”

IEEE Address Access

The address PROM may be an external memorydevice that contains the node’s unique physical Ether-net address and any other data stored by the boardmanufacturer. The software accesses must be 16-bit.This information may be stored in the EEPROM.

Boot PROM Access

The boot PROM is an external memory resourcelocated by the address selected by the EEPROM or theBPAM input in slave mode. It may be softwareaccessed as an 8-bit or 16-bit resource but the latter isrecommended for best performance.

Static RAM Access

The static RAM is only present in the Bus Slave mode.In the Bus Slave mode, two SRAM access schemesare available. When the Shared Memory architecturemode is selected, the SRAM is accessed using ISAmemory cycles to the address range selected by theSMAM input. It may be accessed as an 8 or 16-bitresource but the latter is recommended for best perfor-mance. When the Programmed I/O architecture modeis selected, the SRAM is accessed through ISACSR0and ISACSR1 using the RAP and IDP.

Bus Cycles (Hardware)The PCnet-ISA II controller supports both 8-bit and16-bit hardware bus cycles. The following sections out-line where any limitations apply based upon the archi-tecture mode and/or the resource that is beingaccessed (PCnet-ISA II controller registers, addressPROM, boot PROM, or shared memory SRAM). Forcompleteness, the following sections are arranged byarchitecture (Bus Master Mode or Bus Slave Mode).SRAM resources apply only to Bus Slave Mode.

All resources (registers, PROMs, SRAM) are pre-sented to the ISA bus by the PCnet-ISA II controller.With few exceptions, these resources can be config-ured for either 8-bit or 16-bit bus cycles. The I/Oresources (registers, address PROM) are width config-ured using the EEPROM. The memory resources (bootPROM, SRAM) are width configured by external hard-ware.

For 16-bit memory accesses, hardware external to thePCnet-ISA II controller asserts MEMCS16 when eitherof the two memory resources is selected. The ISA busrequires that all memory resources within a block of128 Kbytes be the same width, either 8- or 16-bits. Thereason for this is that the MEMCS16 signal is generallya decode of the LA17-23 address lines. 16-bit memorycapability is desirable since two 8-bit accesses take thesame amount of time as four 16-bit accesses.

All accesses to 8-bit resources (which do not returnMEMCS16 or IOCS16) use SD0-7. If an odd byte isaccessed, the Current Master swap buffer turns on.

Offset #Bytes Register

0h 16 IEEE Address

10h 2 RDP

12h 2 RAP(shared by RDP and IDP)

14h 2 Reset

16h 2 IDP

Am79C961A 73


During an odd byte read the swap buffer copies thedata from SD0-7 to the high byte. During an odd bytewrite the Current Master swap buffer copies the datafrom the high byte to SD0-7. The PCnet-ISA II control-ler can be configured to be an 8-bit I/O resource evenin a 16-bit system; this is set by the EEPROM. It is rec-ommended that the PCnet-ISA II controller be config-ured for 8-bit only I/O bus cycles for maximumcompatibility with PC/AT clone motherboards.

When the PCnet-ISA II controller is in an 8-bit systemsuch as a PC/XT, SBHE and IOCS16 must be leftunconnected (these signals do not exist in the PC/XT).This will force ALL resources (I/O and memory) to sup-port only 8-bit bus cycles. The PCnet-ISA II controllerwill function in an 8-bit system only if configured for BusSlave Mode.

Accesses to 16-bit resources (which do returnMEMCS16 or IOCS16) use either or both SD0–7 andSD8–15. A word access is indicated by A0=0 andSBHE=0 and data is transferred on all 16 data lines. Aneven byte access is indicated by A0=0 and SBHE=1and data is transferred on SD0–7. An odd-byte accessis indicated by A0=1 and SBHE=0 and data is trans-ferred on SD8-15. It is illegal to have A0=1 andSBHE=1 in any bus cycle. The PCnet-ISA II controllerreturns only IOCS16; MEMCS16 must be generated byexternal hardware if desired. The use of MEMCS16applies only to Shared Memory Mode.

The following table describes all possible types of ISAbus accesses, including Permanent Master as CurrentMaster and PCnet-ISA II controller as Current Master.The PCnet-ISA II controller will not work with 8-bit

memory while it is Current Master. Any descriptions of8-bit memory accesses are for when the PermanentMaster is Current Master.

The two byte columns (D0–7 and D8–15) indicatewhether the bus master or slave is driving the byte.CS16 is a shorthand for MEMCS16 and IOCS16.

Bus Master Mode

The PCnet-ISA II controller can be configured as a BusMaster only in systems that support bus mastering. Inaddition, the system is assumed to support 16-bitmemory (DMA) cycles (the PCnet-ISA II controllerdoes not use the MEMCS16 signal on the ISA bus).This does not preclude the PCnet-ISA II controller fromdoing 8-bit I/O transfers. The PCnet-ISA II controller willnot function as a bus master in 8-bit platforms such asthe PC/XT.

Refresh Cycles

Although the PCnet-ISA II controller is neither an origi-nator or a receiver of refresh cycles, it does need toavoid unintentional activity during a refresh cycle in busmaster mode. A refresh cycle is performed as follows:First, the REF signal goes active. Then a valid refreshaddress is placed on the address bus. MEMR goes ac-tive, the refresh is performed, and MEMR goes inac-tive. The refresh address is held for a short time andthem goes invalid. Finally, REF goes inactive. Duringa refresh cycle, as indicated by REF being active, thePCnet-ISA II controller ignores DACK if it goes activeuntil it goes inactive. It is necessary to ignore DACKduring a refresh because some motherboards gener-ate a false DACK at that time.

ISA Bus Accesses

Address PROM Cycles External PROM

The Address PROM is a small (16 bytes) 8-bit PROMconnected to the PCnet-ISA II controller Private Data

Bus. The PCnet-ISA II controller will support only 8-bitISA I/O bus cycles for the address PROM; this limita-tion is transparent to software and does not preclude16-bit software I/O accesses. An access cycle begins

R/W A0 SBHE CS16 D0–7 D8–15 Comments

RD 0 1 x Slave Float Low byte RD

RD 1 0 1 Slave Float High byte RD with swap

RD 0 0 1 Slave Float 16-Bit RD converted to low byte RD

RD 1 0 0 Float Slave High byte RD

RD 0 0 0 Slave Slave 16-Bit RD

WR 0 1 x Master Float Low byte WR

WR 1 0 1 Master Float High byte WR with swap

WR 0 0 1 Master Master 16-Bit WR converted tolow byte WR

WR 1 0 0 Float Master High byte WR

WR 0 0 0 Master Master 16-Bit WR

74 Am79C961A


with the Permanent Master driving AEN LOW, drivingthe addressess valid, and driving IOR active. ThePCnet-ISA II controller detects this combination of sig-nals and arbitrates for the Private Data Bus (PRDB) ifnecessary. IOCHRDY is driven LOW during accessesto the address PROM.

When the Private Data Bus becomes available, thePCnet-ISA II controller drives APCS active, releasesIOCHRDY, turns on the data path from PRD0-7, andenables the SD0-7 drivers (but not SD8-15). Duringthis bus cycle, IOCS16 is not driven active. This condi-tion is maintained until IOR goes inactive, at which timethe bus cycle ends. Data is removed from SD0-7 within30 ns.

Address PROM Cycles Using EEPROM Data

Default mode. In this mode, the IEEE address informa-tion is stored not in an external parallel PROM but in theEEPROM along with other configuration information.PCnet-ISA II will respond to I/O reads from the IEEEaddress (the first 16 bytes of the I/O map) by supplyingdata from an internal RAM inside PCnet-ISA II. This in-ternal RAM is loaded with the IEEE address at RESETand is write protected.

Ethernet Controller Register Cycles

Ethernet controller registers (RAP, RDP, IDP) are natu-rally 16-bit resources but can be configured to operatewith 8-bit bus cycles provided the proper protocol is fol-lowed. This means on a read, the PCnet-ISA II control-ler will only drive the low byte of the system data bus; ifan odd byte is accessed, it will be swapped down. Thehigh byte of the system data bus is never driven by thePCnet-ISA II controller under these conditions. On awrite cycle, the even byte is placed in a holding register.An odd byte write is internally swapped up and aug-mented with the even byte in the holding register to pro-vide an internal 16-bit write. This allows the use of 8-bitI/O bus cycles which are more likely to be compatiblewith all ISA-compatible clones, but requires that bothbytes be written in immediate succession. This isaccomplished simply by treating the PCnet-ISA II con-troller registers as 16-bit software resources. Themotherboard will convert the 16-bit accesses done bysoftware into two sequential 8-bit accesses, an evenbyte access followed immediately by an odd byteaccess.

An access cycle begins with the Permanent Masterdriving AEN LOW, driving the address valid, and drivingIOR or IOW active. The PCnet-ISA II controller detectsthis combination of signals and drives IOCHRDY LOW.IOCS16 will also be driven LOW if 16-bit I/O bus cyclesare enabled. When the register data is ready,IOCHRDY will be released HIGH. This condition ismaintained until IOR or IOW goes inactive, at whichtime the bus cycle ends.

RESET Cycles

A read to the reset address causes an PCnet-ISA IIcontroller reset. This has the same effect as assertingthe RESET pin on the PCnet-ISA+ controller (whichhappens on system power up or on a hard boot) exceptthat the T-MAU is NOT reset. The T-MAU will retain itslink pass/fail state, disregarding the software RESETcommand. The subsequent write cycle needed in theNE2100 LANCE based family of Ethernet cards is notrequired but does not have any harmful effects.IOCS16 is not asserted in this cycle.

ISA Configuration Register Cycles

The ISA configuration registers are accessed by plac-ing the address of the desired register into the RAP andreading the IDP. The ISACSR bus cycles are identicalto all other PCnet-ISA II controller register bus cycles.

Boot PROM Cycles

The Boot PROM is an 8-bit PROM connected to thePCnet-ISA II controller Private Data Bus (PRDB) andcan occupy up to 64K of address space. Since thePCnet-ISA II controller does not generate MEMCS16,only 8-bit ISA memory bus cycles to the boot PROMare supported in Bus Master Mode; this limitation istransparent to software and does not preclude 16-bitsoftware memory accesses. A boot PROM accesscycle begins with the Permanent Master driving theaddresses valid, REF inactive, and MEMR active. (AENis not involved in memory cycles). The PCnet-ISA IIcontroller detects this combination of signals, drivesIOCHRDY LOW, and reads a byte out of the BootPROM. The data byte read is driven onto the lower sys-tem data bus lines and IOCHRDY is released. Thiscondition is maintained until MEMR goes inactive, atwhich time the access cycle ends.

The BPCS signal generated by the PCnet-ISA II con-troller is three 20 MHz clock cycles wide (300 ns).Including delays, the Boot PROM has 275 ns torespond to the BPCS signal from the PCnet-ISA II con-troller. This signal is intended to be connected to theCS pin on the boot PROM, with the PROM OE pin tiedto ground.

Current Master Operation

Current Master operation only occurs in the Bus Mastermode. It does not occur in the Bus Slave mode.

There are three phases to the use of the bus by thePCnet-ISA II controller as Current Master, the ObtainPhase, the Access Phase, and the Release Phase.

Obtain Phase

A Master Mode Transfer Cycle begins by assertingDRQ. When the Permanent Master asserts DACK, thePCnet-ISA II controller asserts MASTER, signifying ithas taken control of the ISA bus. The Permanent Mas-ter tristates the address, command, and data lines

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within 60 ns of DACK going active. The PermanentMaster drives AEN inactive within 71 ns of MASTERgoing active.

Access Phase

The ISA bus requires a wait of at least 125 ns afterMASTER is asserted before the new master is allowedto drive the address, command, and data lines. ThePCnet-ISA II controller will actually wait 3 clock cyclesor 150 ns.

The following signals are not driven by the PermanentMaster and are simply pulled HIGH: BALE, IOCHRDY,IOCS16, MEMCS16, SRDY. Therefore, the PCnet-ISAII controller assumes the memory which it is accessingis 16 bits wide and can complete an access in the timeprogrammed for the PCnet-ISA II controller MEMR andMEMW signals. Refer to the ISA Bus ConfigurationRegister description section.

Release Phase

When the PCnet-ISA II controller is finished with thebus, it drives the command lines inactive. 50 ns later,the controller tri-states the command, address, anddata lines and drives DRQ inactive. 50 ns later, the con-troller drives MASTER inactive.

The Permanent Master drives AEN active within 71 nsof MASTER going inactive. The Permanent Master isallowed to drive the command lines no sooner than 60ns after DACK goes inactive.

Master Mode Memory Read Cycle

After the PCnet-ISA II controller has acquired the ISAbus, it can perform a memory read cycle. All timing isgenerated relative to the 20 MHz clock (network clock).Since there is no way to tell if memory is 8-bit or 16-bitor when it is ready, the PCnet-ISA II controller bydefault assumes 16-bit, 1 wait state memory. The waitstate assumption is based on the default value in theMSRDA register in ISACSR0.

The cycle begins with SA0-19, SBHE, and LA17-23being presented. The ISA bus requires them to be validfor at least 28 ns before a read command and thePCnet-ISA II controller provides one clock or 50 ns ofsetup time before asserting MEMR.

The ISA bus requires MEMR to be active for at least219 ns, and the PCnet-ISA II controller provides adefault of 5 clocks, or 250 ns, but this can be tuned forfaster systems with the Master Mode Read Active(MSRDA) register (see section 2.5.2). Also, ifIOCHRDY is driven LOW, the PCnet-ISA II controllerwill wait. The wait state counter must expire andIOCHRDY must be HIGH for the PCnet-ISA II controllerto continue.

The PCnet-ISA II controller then accepts the memoryread data. The ISA bus requires all command lines toremain inactive for at least 97 ns before starting

another bus cycle and the PCnet-ISA II controller pro-vides at least two clocks or 100 ns of inactive time.

The ISA bus requires read data to be valid no morethan 173 ns after receiving MEMR active and thePCnet-ISA II controller requires 10 ns of data setuptime. The ISA bus requires read data to provide at least0 ns of hold time and to be removed from the bus within30 ns after MEMR goes inactive. The PCnet-ISA II con-troller requires 0 ns of data hold time.

Master Mode Memory Write Cycle

After the PCnet-ISA II controller has acquired the ISAbus, it can perform a memory write cycle. All timing isgenerated relative to a 20 MHz clock which happens tobe the same as the network clock. Since there is noway to tell if memory is 8- or 16-bit or when it is ready,the PCnet-ISA II controller by default assumes 16-bit, 1wait state memory. The wait state assumption is basedon the default value in the MSWRA register inISACSR1.

The cycle begins with SA0-19, SBHE, and LA17-23being presented. The ISA bus requires them to be validat least 28 ns before MEMW goes active and data to bevalid at least 22 ns before MEMW goes active. ThePCnet-ISA II controller provides one clock or 50 ns ofsetup time for all these signals.

The ISA bus requires MEMW to be active for at least219 ns, and the PCnet-ISA II controller provides adefault of 5 clocks, or 250 ns, but this can be tuned forfaster systems with the Master Mode Write Active(MSWRA) register (ISACSR1). Also, if IOCHRDY isdriven LOW, the PCnet-ISA II controller will wait.IOCHRDY must be HIGH for the PCnet-ISA II controllerto continue.

The ISA bus requires data to be valid for at least 25 nsafter MEMW goes inactive, and the PCnet-ISA II con-troller provides one clock or 50 ns.

The ISA bus requires all command lines to remaininactive for at least 97 ns before starting another buscycle. The PCnet-ISA II controller provides at least twoclocks or 100 ns of inactive time when bit 4 in ISACSR2is set. The EISA bus requires all command lines toremain inactive for at least 170 ns before startinganother bus cycle. When bit 4 in ISACSR4 is cleared,the PCnet-ISA II controller provides 200 ns of inactivetime.

Back-to-Back DMA Requests

The PCnet-ISA II provides for fair bus bandwidth shar-ing between two bus mastering devices on the ISA busthrough an adaptive delay which is inserted betweenback-to-back DMA requests.

When the PCnet-ISA II requires bus access immedi-ately following a bus ownership period, it first checksthe status of the three currently unused DRQ pins. If a

76 Am79C961A


lower priority DRQ pin than the one currently beingused by the PCnet-ISA II is asserted, the PCnet-ISA IIwill wait 2.6 µs after the deassertion of DACK beforere-asserting its DRQ pin. If no lower priority DRQ pin isasserted, the PCnet-ISA II may re-assert its DRQ pinafter as short as 1.1 µs following DACK deassertion.The priorities assumed by the PCnet-ISA II are orderedDRQ3, DRQ5, DRQ6, DRQ7, with DRQ3 having high-est priority and DRQ7 having the lowest priority. Thispriority ordering matches that used by typical ISA busDMA controllers.

This adaptive delay scheme allows for fair bus band-width sharing when two bus mastering devices, e.g.two PCnet-ISA II devices, are on an ISA bus. The con-troller using the higher priority DMA channel cannotlock out the controller using the lower priority DMAchannel because of the 2.6 µs delay that is insertedbefore DRQ reassertion when a lower priority DRQ pinis asserted. When there is no lower priority DMArequest asserted, the PCnet-ISA II re-requests the busimmediately, providing optimal performance whenthere is no competition for bus access.

Bus Slave Mode

The PCnet-ISA II can be configured to be a bus slavefor systems that do not support bus mastering orrequire a local memory to tolerate high bus latencies.In the Bus Slave mode, the I/O map of the PCnet-ISA IIis identical to the I/O map when in the Bus Mastermode (see I/O Resources section). Hence, the addressPROM, controller registers, and Reset por t areaccessed through I/O cycles on the ISA bus. However,the initialization block, descriptor rings, and buffers,which are located in system memory when in the BusMaster mode, are located in a local SRAM when in theBus Slave mode. The local SRAM can be accessed bymemory cycles on the ISA bus (Shared Memory archi-tecture) or by I/O cycles on the ISA bus (ProgrammedI/O mode).

Address PROM Cycles External PROM

The Address PROM is a small (16 bytes) 8-bit PROMconnected to the PCnet-ISA II controller Private DataBus (PRDB). The PCnet-ISA II controller will supportonly 8-bit ISA I/O bus cycles for the address PROM;this limitation is transparent to software and does notpreclude 16-bit software I/O accesses. An access cyclebegins with the Permanent Master driving AEN LOW,driving the addresses valid, and driving IOR active. ThePCnet-ISA II controller detects this combination of sig-nals and arbitrates for the Private Data Bus if neces-sary. IOCHRDY is always driven LOW during addressPROM accesses.

When the Private Data Bus becomes available, thePCnet-ISA II controller drives APCS active, releasesIOCHRDY, turns on the data path from PRD0-7, andenables the SD0-7 drivers (but not SD8-15). During this

bus cycle, IOCS16 is not driven active. This condition ismaintained until IOR goes inactive, at which time theaccess cycle ends. Data is removed from SD0-7 within30 ns.

The PCnet-ISA II controller will perform 8-bit ISA buscycle operation for all resources (registers, PROMs,SRAM) if SBHE has been left unconnected, such as inthe case of an 8-bit system like the PC/XT.

Ethernet Controller Register Cycles

Ethernet controller registers (RAP, RDP, ISACSR) arenaturally 16-bit resources but can be configured tooperate with 8-bit bus cycles provided the proper pro-tocol is followed. This is programmable by theEEPROM. This means on a read, the PCnet-ISA II con-troller will only drive the low byte of the system databus; if an odd byte is accessed, it will be swappeddown. The high byte of the system data bus is neverdriven by the PCnet-ISA II controller under these con-ditions. On a write, the even byte is placed in a holdingregister. An odd-byte write is internally swapped up andaugmented with the even byte in the holding register toprovide an internal 16-bit write. This allows the use of8-bit I/O bus cycles which are more likely to be compat-ible with all clones, but requires that both bytes be writ-ten in immediate succession. This is accomplishedsimply by treating the PCnet-ISA II controller controllerregisters as 16-bit software resources. The mother-board will convert the 16-bit accesses done by softwareinto two sequential 8-bit accesses, an even-byteaccess followed immediately by an odd-byte access.

An access cycle begins with the Permanent Masterdriving AEN LOW, driving the address valid, and drivingIOR or IOW active. The PCnet-ISA II controller detectsthis combination of signals and drives IOCHRDY LOW.IOCS16 will also be driven LOW if 16-bit I/O bus cyclesare enabled. When the register data is ready,IOCHRDY will be released HIGH. This condition ismaintained until IOR or IOW goes inactive, at whichtime the bus cycle ends.

The PCnet-ISA II controller will perform 8-bit ISA buscycle operation for all resources (registers, PROMs,SRAM) if SBHE has been left unconnected, such as inthe case of an 8-bit system like the PC/XT.

RESET Cycles

A read to the reset address causes an PCnet-ISA IIcontroller reset. This has the same effect as assertingthe RESET pin on the PCnet-ISA+ controller (whichhappens on system power up or on a hard boot) exceptthat the T-MAU is NOT reset. The T-MAU will retain itslink pass/fail state, disregarding the software RESETcommand. The subsequent write cycle needed in theNE2100 LANCE- based family of Ethernet cards is notrequired but does not have any harmful effects.IOCS16 is not asserted in this cycle.

Am79C961A 77


ISA Configuration Register Cycles

The ISA configuration register is accessed by placingthe address of the desired register into the RAP andreading the IDP. The ISACSR bus cycles are identicalto all other PCnet-ISA II controller register bus cycles.

Boot PROM Cycles

The Boot PROM is an 8-bit PROM connected to thePCnet-ISA II controller Private Data Bus (PRDB), andcan occupy up to 64 Kbytes of address space. InShared Memory Mode, an external address compara-tor is responsible for asserting BPAM to the PCnet-ISAII controller. BPAM is intended to be a perfect decodeof the boot PROM address space, i.e. LA17-23, SA16.The LA bus must be latched with BALE in order to pro-vide stable signal for BPAM. REF inactive must be usedby the external logic to gate boot PROM addressdecoding. This same logic must assert MEMCS16 tothe ISA bus if 16-bit Boot PROM bus cycles aredesired.

In the Bus Slave mode, boot PROM cycles can be pro-grammed to be 8 or 16-bit ISA memory cycles with theBP_16B bit (PnP 0x42). If the BP_16B bit is set, thePCnet-ISA II assumes 16-bit ISA memory cycles forthe boot PROM. In this case, the external hardwareresponsible for generating BPAM must also generateMEMCS16. A 16-bit boot PROM bus cycle begins withthe Permanent Master driving the addresses valid andMEMR active. (AEN is not involved in memory cycles).External hardware would assert BPAM and MEMCS16.The PCnet-ISA II controller detects this combination ofsignals, drives IOCHRDY LOW, and reads two bytesout of the boot PROM. The data bytes read from thePROM are driven by the PCnet-ISA II controller ontoSD0-15 and IOCHRDY is released. This condition ismaintained until MEMR goes inactive, at which time theaccess cycle ends.

The PCnet-ISA II controller will perform 8-bit ISA buscycle operation for all resource (registers, PROMs,SRAM) if SBHE has been left unconnected, such as inthe case of an 8-bit system like the PC/XT.

The BPCS signal generated by the PCnet-ISA II con-troller is three 20 MHz clock cycles wide (350 ns).Including delays, the Boot PROM has 275 ns torespond to the BPCS signal from the PCnet-ISA II con-troller. This signal is intended to be connected to theCS pin on the boot PROM, with the PROM OE pin tiedto ground.

Static RAM Cycles – Shared Memory Architecture

In the Shared Memory Architecture mode, the SRAM isan 8-bit device connected to the PCnet-ISA II controllerPrivate Bus, and can occupy up to 64 Kbytes ofaddress space. The SRAM is memory mapped into theISA memory space at an address range determined byexternal decode logic. The external address compara-

tor is responsible for asserting SMAM to the PCnet-ISAII controller. SMAM is intended to be a perfect decodeof the SRAM address space, i.e. LA17-23, SA16 for 64Kbytes of SRAM. The LA signals must be latched byBALE in order to provide a stable decode for SMAM.The PCnet-ISA II controller assumes 16-bit ISA mem-ory bus cycles for the SRAM, so this same logic mustassert MEMCS16 to the ISA bus if 16-bit bus cycles areto be supported.

A 16-bit SRAM bus cycle begins with the PermanentMaster driving the addresses valid, REF inactive, andeither MEMR or MEMW active. (AEN is not involved inmemory cycles). External hardware would assertSMAM and MEMCS16. The PCnet-ISA II controllerdetects this combination of signals and initiates theSRAM access.

In a write cycle, the PCnet-ISA II controller stores thedata into an internal holding register, allowing the ISAbus cycle to finish normally. The data in the holding reg-ister will then be written to the SRAM without the needfor ISA bus control. In the event the holding register isalready filled with unwritten SRAM data, the PCnet-ISAII controller will extend the ISA write cycle by drivingIOCHRDY LOW until the unwritten data is stored in theSRAM. The current ISA bus cycle will then completenormally.

In a read cycle, the PCnet-ISA II controller arbitrates forthe Private Bus. If it is unavailable, the PCnet-ISA IIcontroller drives IOCHRDY LOW. The PCnet-ISA IIcontroller compares the 16 bits of address on the Sys-tem Address Bus with that of a data word held in aninternal pre-fetch register.

If the address does not match that of the prefetchedSRAM data, then the PCnet-ISA II controller drivesIOCHRDY LOW and reads two bytes from the SRAM.The PCnet-ISA II controller then proceeds as thoughthe addressed data location had been prefetched.

If the internal prefetch buffer contains the correct data,then the pre-fetch buffer data is driven on the SystemData bus. If IOCHRDY was previously driven LOW dueto either Private Data Bus arbitration or SRAM access,then it is released HIGH. The PCnet-ISA II controllerremains in this state until MEMR is de-asserted, atwhich time the PCnet-ISA II controller performs a newprefetch of the SRAM. In this way memory read waitstates can be minimized.

The PCnet-ISA II controller performs prefetches of theSRAM between ISA bus cycles. The SRAM isprefetched in an incrementing word address fashion.Prefetched data are invalidated by any other activity onthe Private Bus, including Shared Memory Writes byeither the ISA bus or the network interface, and alsoaddress and boot PROM reads.

78 Am79C961A


The only way to configure the PCnet-ISA II controllerfor 8-bit ISA bus cycles for SRAM accesses is to con-figure the entire PCnet-ISA II controller to support only8-bit ISA bus cycles. This is accomplished by leavingthe SBHE pin disconnected. The PCnet-ISA II control-ler will perform 8-bit ISA bus cycle operation for allresources (registers, PROMs, SRAM) if SBHE hasnever been driven active since the last RESET, such asin the case of an 8-bit system like the PC/XT. In thiscase, the external address decode logic must notassert MEMCS16 to the ISA bus, which will be the caseif MEMCS16 is left unconnected. It is possible to man-ufacture a dual 8/16 bit PCnet-ISA II controller adaptercard, as the MEMCS16 and SBHE signals do not existin the PC/XT environment.

At the memory device level, each SRAM Private Busread cycle takes two 50 ns clock periods for a maxi-mum read access time of 75 ns. The timing looks likethis:

The address and SROE go active within 20 ns of theclock going HIGH. Data is required to be valid 5 nsbefore the end of the second clock cycle. Address andSROE have a 0 ns hold time after the end of the secondclock cycle. Note that the PCnet-ISA II controller doesnot normally provide a separate SRAM CS signal;SRAM CS must always be asserted.

SRAM Private Bus write cycles require three 50 nsclock periods to guarantee non-negative address setupand hold times with regard to SRWE. The timing isillustrated as follows:

Address and data are valid 20 ns after the rising edgeof the first clock period. SRWE goes active 20 ns afterthe falling edge of the first clock period. SRWE goesinactive 20 ns after the falling edge of the third clockperiod. Address and data remain valid until the end ofthe third clock period. Rise and fall times are nominally5 ns. Non-negative setup and hold times for addressand data with respect to SRWE are guaranteed. SRWEhas a pulse width of typically 100 ns, minimum 75 ns.

Static RAM Cycles – Programmed I/O Architecture

In the Programmed I/O Architecture mode, the SRAMis an 8-bit device connected to the PCnet-ISA II control-ler Private Bus, and can occupy up to 64 Kbytes ofaddress space. The SRAM is accessed through theISACSR0 and ISACSR1 registers which serve as theSRAM Data port and SRAM Address pointer, respec-tively. Since the ISACSRs are used to access theSRAM, simple I/O accesses (to RAP and IDP) whichare decoded by the PCnet-ISA II are used to accessthe SRAM without any external decoding logic.

The RAP and IDP ports are naturally 16-bit resourcesand can be accessed with 16-bit ISA I/O cycles if theIO_MODE bit (PnP 0xF0) is set. As discussed in theEthernet Controller Register Cycles section, 8-bit I/Ocycles are also allowed, provided the proper protocol isfollowed. This protocol requires that byte accessesmust be performed in pairs, with the even byte accessalways being followed by associated odd byte access.In the Programmed I/O architecture mode, whenaccessing the SRAM Data Por t in par t icu lar(ISACSR0), the restrictions on byte accesses areslightly different. Even byte accesses (accesses whereA0 = 0, SBHE = 1) may be performed to ISACSR0 with-out any restriction. A corresponding odd byte accessneed not be performed following the even byte accessas is required when accessing all other controller reg-isters. In fact, odd byte accesses (accesses where A0= 1, SBHE = 1) may not be performed to ISACSR0, ex-cept when they are the result of a software 16-bitaccess that are automatically converted to two byte ac-cesses by motherboard logic.

Since the internal PCnet-ISA II registers are used toaccess the SRAM in the Programmed I/O architecturemode, the access cycle on the ISA bus is identical tothat described in the Ethernet Controller RegisterCycles section.

To minimize the number of I/O cycles required toaccess the SRAM, the PCnet-ISA II auto-incrementsthe SRAM Address Pointer (ISACSR1) by one or twofollowing every read or write to the SRAM Data Port(ISACSR0). If a single byte read or write to the SRAMData Port occurs, the SRAM Address Pointer is auto-matically incremented by 1. If a word read or write tothe SRAM Data Port occurs, the SRAM AddressPointer is automatically incremented by 2. This allows

XTAL1(20 MHz)

Address

SROE

19364A-14

Static RAM Read Cycle

Address/Data

SRWE

XTAL1(20 MHz)

Static RAM Write Cycle 19364A-15

Am79C961A 79


reads and writes to adjacent ascending addresses inthe SRAM to be performed without intervening writes tothe SRAM Address Pointer. Since buffer accessescomprise a high percentage of all accesses to theSRAM, and buffer accesses are typically performed inadjacent ascending order, the auto-increment of theSRAM Address Pointer reduces the required ISA buscycles significantly.

In addition to the auto-incrementing of the SRAMAddress pointer, the PCnet-ISA II performs write post-ing on writes to the SRAM and read prefetching onreads from the SRAM to maximize performance in theProgrammed I/O architecture mode.

Write Posting: When a write cycle to the SRAM DataPort occurs, the PCnet-ISA II controller stores the datainto an internal holding register, allowing the ISA buscycle to finish normally. The data in the holding registerwill then be written to the SRAM without the need forISA bus control. In the event that the holding register isalready filled with unwritten SRAM data, the PCnet-ISAII controller will extend the ISA write cycle by drivingOCHRDY LOW until the unwritten data is stored in theSRAM. Once the data is written into the SRAM, thenew write data is stored into the internal holding regis-ter and IOCHRDY is released allowing the ISA buscycle to complete.

Read Prefetching: To gain performance on readaccesses to the SRAM, the PCnet-ISA II performsprefetches of the SRAM after every read from theSRAM Data Port. The prefetch is performed using thespecu la ted address tha t resu l t s f rom theauto-increment that occurs on the SRAM AddressPointer following every access to the SRAM Data Port.Following every read access, the 16-bit word followingthe just-read SRAM byte or word is prefetched andplaced in a holding register. If a word read from theSRAM Data Port occurs before a “prefetch invalidationevent” occurs, the prefetched word is driven onto theSD[15:0] pins without a wait state (no IOCHRDY LOWassertion). A “prefetch invalidation event” is defined asany activity on the Private Bus other than SRAM reads.This includes SRAM writes by either the ISA bus or thenetwork interface, address or boot PROM reads, or anywrite to the SRAM Address Pointer.

The PCnet-ISA II interface to the SRAM in the Pro-grammed I/O architecture mode is identical to that inthe Shared Memory Architecture mode. Hence, theSRAM Read and Write cycle descriptions and dia-grams shown in the “Static RAM Cycles – SharedMemory Architecture” section apply.

Transmit OperationThe transmit operation and features of the PCnet-ISAII controller are controlled by programmable options.

Transmit Function Programming

Automatic transmit features, such as retry on collision,FCS generation/transmission, and pad field insertion,can all be programmed to provide flexibility in the(re-)transmission of messages.

Disable retry on collision (DRTY) is controlled by theDRTY bit of the Mode register (CSR15) in the initializa-tion block.

Automatic pad field insertion is controlled by theAPAD_XMT bit in CSR4. If APAD_XMT is set, auto-matic pad field insertion is enabled, the DXMTFCS fea-ture is over-ridden, and the 4-byte FCS will be added tothe transmitted frame unconditionally. If APAD_XMT iscleared, no pad field insertion will take place and runtpacket transmission is possible.

The disable FCS generation/transmission feature canbe programmed dynamically on a frame by framebasis. See the ADD_FCS description of TMD1.

Transmit FIFO Watermark (XMTFW in CSR80) sets thepoint at which the BMU (Buffer Management Unit)requests more data from the transmit buffers for theFIFO. This point is based upon how many 16-bit bustransfers (2 bytes) could be performed to the existingempty space in the transmit FIFO.

Transmit Start Point (XMTSP in CSR80) sets the pointwhen the transmitter actually tries to go out on themedia. This point is based upon the number of byteswritten to the transmit FIFO for the current frame.

When the entire frame is in the FIFO, attempts at trans-mission of preamble will commence regardless of thevalue in XMTSP. The default value of XMTSP is 10b,meaning 64 bytes full.

Automatic Pad Generation

Transmit frames can be automatically padded to extendthem to 64 data bytes (excluding preamble). Thisallows the minimum frame size of 64 bytes (512 bits) for802.3/Ethernet to be guaranteed with no software inter-vention from the host/controlling process. Setting theAPAD_XMT bit in CSR4 enables the automatic pad-ding feature. The pad is placed between the LLC datafield and FCS field in the 802.3 frame. FCS is alwaysadded if the frame is padded, regardless of the state ofDXMTFCS. The transmit frame will be padded by byteswith the value of 00h. The default value of APAD_XMTis 0, and this will disable auto pad generation afterRESET.

It is the responsibility of upper layer software to cor-rectly define the actual length field contained in themessage to correspond to the total number of LLCData bytes encapsulated in the packet (length field asdefined in the IEEE 802.3 standard). The length valuecontained in the message is not used by the PCnet-ISAII controller to compute the actual number of pad bytes

80 Am79C961A


to be inserted. The PCnet-ISA II controller will appendpad bytes dependent on the actual number of bitstransmitted onto the network. Once the last data byteof the frame has completed prior to appending theFCS, the PCnet-ISA II controller will check to ensurethat 544 bits have been transmitted. If not, pad bytesare added to extend the frame size to this value, andthe FCS is then added.

The 544 bit count is derived from the following:

Minimum frame size (excluding preamble,including FCS) 64 bytes 512 bitsPreamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bitsTo be classed as a minimum-size frame at the receiver,the transmitted frame must contain:

Preamble + (Min Frame Size + FCS) bits

At the point that FCS is to be appended, the transmittedframe should contain:

Preamble + (Min Frame Size - FCS) bits64+ (512- 32) bits

A minimum-length transmit frame from the PCnet-ISAII controller will, therefore, be 576 bits after the FCS isappended.

Transmit FCS Generation

Automatic generation and transmission of FCS for atransmit frame depends on the value of DXMTFCS bitin CSR15. When DXMTFCS = 0 the transmitter will

generate and append the FCS to the transmitted frame.I f the automat ic padd ing feature is invoked(APAD_XMT is SET in CSR4), the FCS will beappended by the PCnet-ISA II controller regardless ofthe state of DXMTFCS. Note that the calculated FCS istransmitted most-significant bit first. The default valueof DXMTFCS is 0 after RESET.

Transmit Exception Conditions

Exception conditions for frame transmission fall intotwo distinct categories; those which are the result ofnormal network operation, and those which occur dueto abnormal network and/or host related events.

Normal events which may occur and which are handledautonomously by the PCnet-ISA II controller are basi-cally collisions within the slot time with automatic retry.The PCnet-ISA II controller will ensure that collisionswhich occur within 512 bit times from the start of trans-mission (including preamble) will be automaticallyretried with no host intervention. The transmit FIFO en-sures this by guaranteeing that data contained withinthe FIFO will not be overwritten until at least 64 bytes(512 bits) of data have been successfully transmittedonto the network.

If 16 total attempts (initial attempt plus 15 retries) fail,the PCnet-ISA II controller sets the RTRY bit in the cur-rent transmit TDTE in host memory (TMD2), gives upownership (sets the OWN bit to zero) for this packet,and processes the next packet in the transmit ring fortransmission.

ISO 8802-3 (IEEE/ANSI 802.3) Data Frame

Preamble 1010....1010

SYNC 10101011

Dest. ADDR

SRCE. ADDR.

LengthLLC Data

Pad FCS

56 Bits

8 Bits

6 Bytes

6 Bytes

2 Bytes

46-1500 Bytes

4 Bytes

19364A-16

Am79C961A 81


Abnormal network conditions include:

Loss of carrier

Late collision

SQE Test Error (Does not apply to 10BASE-T port.)

These should not occur on a correctly configured 802.3network, and will be reported if they do.

When an error occurs in the middle of a multi-bufferframe transmission, the error status will be written inthe current descriptor. The OWN bit(s) in the subse-quent descriptor(s) will be reset until the STP (the nextframe) is found.

Loss of Carrier

A loss of carrier condition will be reported if thePCnet-ISA II controller cannot observe receive activitywhile it is transmitting on the AUI port. After thePCnet-ISA II controller initiates a transmission, it willexpect to see data “looped back” on the DI± pair. Thiswill internally generate a “carrier sense,” indicating thatthe integrity of the data path to and from the MAU isintact, and that the MAU is operating correctly. This“carrier sense” signal must be asserted before the endof the transmission. If “carrier sense” does not becomeactive in response to the data transmission, orbecomes inactive before the end of transmission, theloss of carrier (LCAR) error bit will be set in TMD2 afterthe frame has been transmitted. The frame will not bere-tried on the basis of an LCAR error. In 10BASE-Tmode LCAR will indicate that Jabber or Link Fail statehas occurred.

Late Collision

A late collision will be reported if a collision conditionoccurs after one slot time (512 bit times) after the trans-mit process was initiated (first bit of preamble com-menced). The PCnet-ISA II controller will abandon thetransmit process for the particular frame, set Late Col-lision (LCOL) in the associated TMD3, and process thenext transmit frame in the ring. Frames experiencing alate collision will not be re-tried. Recovery from thiscondition must be performed by upper-layer software.

SQE Test Error

During the inter packet gap time following the comple-tion of a transmitted message, the AUI CI± pair isasserted by some transceivers as a self-test. The inte-gral Manchester Encoder/Decoder will expect the SQETest Message (nominal 10 MHz sequence) to bereturned via the CI± pair within a 40 network bit timeperiod after DI± pair goes inactive. If the CI± inputs arenot asserted within the 40 network bit time period fol-lowing the completion of transmission, then thePCnet-ISA II controller will set the CERR bit in CSR0.CERR will be asserted in 10BASE-T mode after trans-mit if T-MAU is in Link Fail state. CERR will never cause

INTR to be activated. It will, however, set the ERR bit inCSR0.

Host related transmit exception conditions includeBUFF and UFLO as described in the Transmit Descrip-tor section.

Receive OperationThe receive operation and features of the PCnet-ISA IIcontroller are controlled by programmable options.

Receive Function Programming

Automatic pad field stripping is enabled by setting theASTRP_RCV bit in CSR4; this can provide flexibility inthe reception of messages using the 802.3 frame format.

All receive frames can be accepted by setting thePROM bit in CSR15. When PROM is set, thePCnet-ISA II controller will attempt to receive all mes-sages, subject to minimum frame enforcement. Pro-miscuous mode overrides the effect of the DisableReceive Broadcast bit on receiving broadcast frames.

The point at which the BMU will start to transfer datafrom the receive FIFO to buffer memory is controlled bythe RCVFW bits in CSR80. The default establishedduring reset is 10b, which sets the threshold flag at 64bytes empty.

Automatic Pad Stripping

During reception of an 802.3 frame the pad field can bestripped automatically. ASTRP_RCV (bit 10 in CSR4) =1 enables the automatic pad stripping feature. The padfield will be stripped before the frame is passed to theFIFO, thus preserving FIFO space for additionalframes. The FCS field will also be stripped, since it iscomputed at the transmitting station based on the dataand pad field characters, and will be invalid for areceive frame that has had the pad characters stripped.

The number of bytes to be stripped is calculated fromthe embedded length field (as defined in the IEEE802.3 definition) contained in the frame. The lengthindicates the actual number of LLC data bytes con-tained in the message. Any received frame which con-tains a length field less than 46 bytes will have the padfield stripped (if ASTRP_RCV is set). Receive frameswhich have a length field of 46 bytes or greater will bepassed to the host unmodified.

Since any valid Ethernet Type field value will always begreater than a normal 802.3 Length field (≥46), thePCnet-ISA II controller will not attempt to strip validEthernet frames.

Note that for some network protocols the value passedin the Ethernet Type and/or 802.3 Length field is notcompliant with either standard and may cause problems.

The diagram below shows the byte/bit ordering of thereceived length field for an 802.3 compatible frameformat.

82 Am79C961A


IEEE/ANSI 802.3 Frame and Length Field Transmission Order

Receive FCS Checking

Reception and checking of the received FCS is per-formed automatically by the PCnet-ISA II controller.Note that if the Automatic Pad Stripping feature isenabled, the received FCS will be verified against thevalue computed for the incoming bit stream includingpad characters, but it will not be passed to the host. Ifa FCS error is detected, this will be reported by theCRC bit in RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into twodistinct categories; those which are the result of normalnetwork operation, and those which occur due toabnormal network and/or host related events.

Normal events which may occur and which are handledautonomously by the PCnet-ISA II controller are basi-cally collisions within the slot time and automatic runtpacket rejection. The PCnet-ISA II controller will ensurethat collisions which occur within 512 bit times from the

start of reception (excluding preamble) will be automat-ically deleted from the receive FIFO with no host inter-vention. The receive FIFO will delete any frame whichis composed of fewer than 64 bytes provided that theRunt Packet Accept (RPA bit in CSR124) feature hasnot been enabled. This criteria will be met regardless ofwhether the receive frame was the first (or only) framein the FIFO or if the receive frame was queued behinda previously received message.

Abnormal network conditions include:

FCS errors

Late collision

These should not occur on a correctly configured 802.3network and will be reported if they do.

Host related receive exception conditions includeMISS, BUFF, and OFLO. These are described in theReceive Descriptor section.

Preamble 1010....1010

SYNCH 10101011

Dest. ADDR.

Srce. ADDR.

Length LLC DATA

Pad FCS

56 Bits

8 Bits

6 Bytes

6 Bytes

2 Bytes

46–1500 Bytes

4 Bytes

Most Significant

Byte

Least Significant

Byte

Bit 0

Bit 7

Start of Packet at Time= 0

Increasing Time

Bit 7

Bit 0

45–0 Bytes

1–1500 Bytes

19364A-17

Am79C961A 83


MAGIC PACKET™ OPERATIONIn the Magic Packet mode, PCnet-ISA II completes anytransmit and receive operations in progress, suspendsnormal activity, and enters into a state where only aMagic Packet could be detected. A Magic Packet frameis a frame that contains a data sequence which repeatsthe Physical Address (PADR[47:00]) at least sixteentimes frame sequentially, with bit[00] received first. InMagic Packet suspend mode, the PCnet-ISA II remainspowered up. Slave accesses to the PCnet-ISA II arestill possible, the same as any other mode. All of thereceived packets are flushed from the receive FIFO. AnLED and/or interrupt pin could be activated, indicatingthe receive of a Magic Packet frame. This indicationcould be used for a variety of management tasks.

Magic Packet Mode Activation

This mode can be enabled by either software or exter-nal hardware means, but in either case, the MP_MODEbit (CSR5, bit 1) must be set first.

Hardware Activation. This is done by driving theSLEEP pin low. Deasserting the SLEEP pin will returnthe PCnet-ISA II to normal operation.

Software Activation. This is done by setting theMP_ENBL bit (CSR5, bit 2). Resetting this bit will returnthe PCnet-ISA II to normal operation.

Magic Packet Receive Indicators

The reception of a Magic Packet can be indicated eitherthrough one of the LEDs 1, 2 or 3, and/or the activationof the interrupt pin. MP_INT bit (CSR5, bit 4) will alsobe set upon the receive of the Magic Packet.

LED Indication. Either one of the LEDs 1, 2, or 3 couldbe activated by the receive of the Magic Packet. The“Magic Packet enable” bit (bit 9) in the ISACSR 5, 6 or7 should be set to enable this feature. Note that thepolarity of the LED2 could be controlled by theLEDXOR bit (ISACSR6, bit 14). The LED could bedeactivated by setting the STOP bit or resetting theMP_ENBL bit (CSR5, bit 2).

Interrupt Indication. Interrupt pin could be activatedby the receive of the Magic Packet. The MP_I_ENBL bit(CSR5, bit 3) and IENA bit (CSR0, bit 6) should be setto enable this feature.

Loopback OperationLoopback is a mode of operation intended for systemdiagnostics. In this mode, the transmitter and receiverare both operating at the same time so that thecontroller receives its own transmissions. The control-ler provides two types of internal loopback and threetypes of external loopback. In internal loopback mode,the transmitted data can be looped back to the receiverat one of two places inside the controller without actu-ally transmitting any data to the external network. Thereceiver will move the received data to the next receive

buffer, where it can be examined by software. Alterna-tively, external loopback causes transmissions to gooff-chip. For the AUI port, frame transmission occursnormally and assumes that an external MAU will loopthe frame back to the chip. For the 10BASE-T port, twoexternal loopback options are available, both of whichrequire a valid link pass state and both of which trans-mit data frames at the RJ45 interface. Selection ofthese modes is defined by the TMAU_LOOPE bit inISACSR2. One option loops the data frame back insidethe chip, and is compatible with a ‘live’ network. Theother option requires an external device (such as a‘loopback plug’) to loop the data back to the chip, afunction normally not available on a 10BASE-Tnetwork.

The PCnet-ISA II chip has two dedicated FCS genera-tors, eliminating the traditional LANCE limitations onloopback FCS operation. The receive FCS generationlogic is always enabled. The transmit FCS generationlogic can be disabled (to emulate LANCE type loop-back operation) by setting the DXMTFCS bit in theMode register (CSR15). In this configuration, softwaremust generate the FCS and append the four FCS bytesto the transmit frame data.

The loopback facilities of the MAC Engine allow fulloperation to be verified without disturbance to the net-work. Loopback operation is also affected by the stateof the Loopback Control bits (LOOP, MENDECL, andINTL) in CSR15. This affects whether the internalMENDEC is considered part of the internal or externalloop- backpath.

The receive FCS generation logic in the PCnet-ISA IIchip is used for multicast address detection. Since thisFCS logic is always enabled, there are no restrictionsto the use of multicast addressing while in loopbackmode.

When performing an internal loopback, no frame will betransmitted to the network. However, when thePCnet-ISA II controller is configured for internal loop-back the receiver will not be able to detect networktraffic. External loopback tests will transmit frames ontothe network if the AUI port is selected, and thePCnet-ISA II controller will receive network traffic whileconfigured for external loopback when the AUI port isselected. Runt Packet Accept is automatically enabledwhen any loopback mode is invoked.

Loopback mode can be performed with any frame size.Runt Packet Accept is internally enabled (RPA bit inCSR124 is not affected) when any loopback mode isinvoked. This is to be backwards compatible to theLANCE (Am7990) software.

LEDsThe PCnet-ISA II controller’s LED control logic allowsprogramming of the status signals, which are displayed

84 Am79C961A


on 3 LED outputs. One LED (LED0) is dedicated to dis-playing 10BASE-T Link Status. The status signalsavailable are Collision, Jabber, Receive, Receive Polar-ity, Transmit, Receive Address Match, and Full DuplexLink Status. If more than one status signal is enabled,they are ORed together. An optional pulse stretcher isavailable for each programmable output. This allowsemulation of the TPEX (Am79C98) and TPEX+

(Am79C100) LED outputs.

Each status signal is ANDed with its correspondingenable signal. The enabled status signals run to a com-mon OR gate:

The output from the OR gate is run through a pulsestretcher, which consists of a 3-bit shift register clockedat 38 Hz. The data input of the shift register is at logic0. The OR gate output asynchronously sets all threebits of the shift register when its output goes active. Theoutput of the shift register controls the associated LEDxpin. Thus, the pulse stretcher provides an LED outputof 52 ms to 78 ms.

Refer to the section “ISA Bus Configuration Registers”for information on LED control via the ISACSRs.

Signal Behavior

COL Active during collision activity on the network

FDLSActive when Full Duplex operation is enabled and functioning on the selected network port

JABActive when the PCnet-ISA II is jabbering on the network

LNKSTActive during Link OK Not active during Link Down

RCV Active while receiving data

RVPOLActive during receive polarity is OK Not active during reverse receive polarity

RCVADDM Active during Receive with Address Match

XMT Active while transmitting data

ANDFDLSFDLSE

ANDRCVMRCVM E

ANDXMTXMT E

ANDRVPOLRVPOL E

ANDRCVRCV E

ANDJABJAB E

ANDCOLCOL E

ORTo

PulseStretcher

ANDRCVADDMRCVADDE

19364A-18

LED Control Logic

Am79C961A 85


SWITCHING TEST CIRCUITS

KS000010

Must beSteady

MayChangefrom H to L

MayChangefrom L to H

Does Not Apply

Don’t Care,Any ChangePermitted

Will beSteady

Will beChangingfrom H to L

Will be Changing from L to H

Changing,StateUnknown

Center Line is High-Impedance“Off” State

WAVEFORM INPUTS OUTPUTS

Am79C961A 139



19364A-29

CL

VTHRESHOLD

IOL

IOH

Normal and Three-State Outputs

Sense Point

19364A-30

AVDD

DO+

154 Ω100 pF

DO–

AVSS

52.3 Ω

Test Point

AUI DO Switching Test Circuit

140 Am79C961A



TXD Switching Test Circuit

DVDD

TXD+

294 Ω100 pF

TXD–

DVSS

294 Ω

Test Point

19364A-31

Includes Test Jig Capacitance

TXD Outputs Test Circuit

DVDD

TXP+

715 Ω100 pF

TXP–

DVSS

715 Ω

Test Point

Includes TestJig Capacitance

19364A-32

Am79C961A 141


SWITCHING WAVEFORMS: BUS MASTER MODE

I/O Write without Wait States

19364A-33

AEN, SBHE,SA0–9

IOW

SD

tIOW5 tIOW6

tIOW4

tIOW1 tIOW3tIOW2

Stable

AEN, SBHE,SA0–9

IOW

SD

tIOW5 tIOW6

tIOW4

tIOW1 tIOW2

Stable

IOCHRDY

tIOW7tIOW8 tIOW9

19364A-34

I/O Write with Wait States

142 Am79C961A



Serial Shift EEPROM Interface Read Timing19364A-35

EESK(PRDB0)

EECS

EEDI(PRDB1)

EEDO(PRDB2)

SHFBUSY

0 1 1 A7 A6 A5 A4 A3 A2 A1 A0

D0 D1 D2 D14 D15

Falling transition at 26th Word, if checksum is 0xFF.

0

19364A-36

Serial EEPROM Control Timing

EESK(PRDB0)

EECS

EEDI(PRDB1)

SHFBSY

EED0(PRDB2)

tSR1 tSR2

tSR3 tSR4 tSR5

Stable

tSR6 tSR7

Am79C961A 143



Slave Serial EEPROM Latency Timing 19364A-37

tSL1

tSL2

tSL3

EED0(PRDB2)

IOR

IOCHRDY

IOW

EESK, EEDI,EECS,

SHFBUSY

19364A-38

I/O Read without Wait States

AEN, SBHE,SA0–9

IOR

SD

tIOR5

tIOR4

tIOR3

tIOR1 tIOR2

Stable

Stable

144 Am79C961A



I/O Read with Wait States19364A-39

AEN, SBHE,SA0–9

IOR

SD

tIOR8 tIOR4

tIOR3

tIOR1 tIOR2

Stable

IOCHRDY

tIOR6 tIOR7

Stable

19364A-40I/O to Memory Command Inactive Time

IOW, MEMW

MEMR, IOR

tIOM1 tIOM2

Am79C961A 145



IOCS16 Timings

19364A-41

AEN, SBHE,SA0–9

IOCS16

tIOCS1 tIOCS2

19364A-42Bus Acquisition

tMMA1

tMMA2

tMMA3

tMMA4

tMMA5

REF

DRQ

DACK

MASTER

MEMR/MEMW

SBHE,SA0–19,LA17–23

146 Am79C961A



Bus Release19364A-43

tMMBR1

tMMBR4

DRQ

DACK

MASTER

MEMR/MEMW

tMMBR2

tMMBR3

SBHE, SA0–19,LA17–23

19364A-44Write Cycles

tMMW1tMMW2 tMMW3

tMMW4

tMMW7 tMMW8 tMMW9

tMMW5 tMMW6


MEMW

IOCHRDY

SD0–15

(Non Wait) (Wait States Added)

tMMW11tMMW10

Am79C961A 147



tMMR1tMMR2 tMMR3

tMMR4

tMMR7 tMMR8 tMMR9

tMMR10 tMMR11tMMR10 tMMR11

Stable Stable

Stable Stable

tMMR5 tMMR6


MEMR

IOCHRDY

SD0–15

19364A-45


Read Cycles

Stable

Stable

tIOR1 tIOR2

tIOR3

tMA5

tIOR6

tMA1tMA2

tMA3 tMA4

tMA6 tIOR4

AEN, SBHE,SA0–9

IOR

IOCHRDY

APCS(IRQ15)

PRDB0–7

SD0–7

19364A-46External Address PROM Read Cycle

148 Am79C961A



Stable

Stable

tMB1 tMB2

tMB4tMB7

tMB3

tMB5tMB6

tMB8 tMB9

tMB10 tMB11

REF, SBHE,SA0–19

MEMR

IOCHRDY

BPCS

PRDB0–7

SD0–7

19634A-47

BALE

StableLA20–23

tMB12

tMB13

tMB14

Boot PROM Read Cycle

Am79C961A 149



Stable

Stable

tMFR1 tMFR2

tMFR4tMFR7

tMFR3

tMFR5tMFR6

tMFR8 tMFR9

tMFR10 tMFR11

REF, SBHE,SA0–19

MEMR

IOCHRDY

BPCS

PRDB0–7

SD0–7

19364A-48

BALE

StableLA20–23

tMFR12

tMFR13

tMFR14

Flash Read Cycle

150 Am79C961A



tMFW5

Stable

tMFW1 tMFW2

tMFR4tMFW3

tMFW7

SBHE,SA0–19

MEMW

IOCHRDY

SD0-7

BALE

StableLA20–23

tMFW13

tMFW14

tMFW15 tMFW6

tMFW8

FL_WE (IRQ12)

tMFW11tMFW10

tMFW12

Stable

StablePRDB0-7

19364A-49

tMFW9

Flash Write Cycle

Am79C961A 151


SWITCHING WAVEFORMS: SHARED MEMORY MODE

StableAEN, SBHE,SA0–9

IOW

SD

tIOW6tIOW5

19364A-50

tIOW2tIOW1

tIOW3

tIOW4


StableAEN, SBHE,

SA0–9

IOW

SD

tIOW6tIOW5

19664A-51

IOCHRDY

tIOW1 tIOW2

tIOW7 tIOW8tIOW9

tIOW4


152 Am79C961A



tIOR1


IOR

SD

tIOR4tIOR5

Stable

tIOR2

tIOR3

19364A-52I/O Write without Wait States


IOR

tIOR2

IOCHRDY

SD

tIOR4

Stable

tIOR3tIOR6 tIOR7

tIOR1

tIOR8

19364A-53I/O Read with Wait States

Am79C961A 153



StableSA0–15,SBHE

SMAM

SD

tMW2

tMW6tMW5

MEMWtMW4

tMW1tMW3

19364A-54Memory Write without Wait States

StableSA0–15,

SBHE

SMAM

SD

tMW4

tMW6tMW5

MEMW

tMW7tMW8 tMW9

IOCHRDY

tMW2tMW1

19364A-55Memory Write with Wait States

154 Am79C961A



Stable

Stable

tMR1 tMR2

tMR5tMR4

tMR3

SA0–15,SBHE

SMAM

MEMR

SD

19364A-56Memory Read without Wait States

Stable

Stable

tMR1 tMR2

tMR6tMR3

SA0–15,SBHE

SMAM/BPAM

MEMR

SD

tMR7

tMR8 tMR4

IOCHRDY


Am79C961A 155



tIOM2

IOW, MEMW

MEMR, IOR

tIOM1

I/O to Memory Command Inactive Time 19364A-58

AEN, SBHE,SA0–9

IOCS16

tIOCS1 tIOCS2

IOCS16 Timings 19364A-59

156 Am79C961A



tSFW5

Stable

tSFW1 tSFW2

tSFR4tSFW3

tSFW7

SBHE,SA0–15,

BPAM

MEMW

IOCHRDY

SD0-7

tSFW6

tSFW8

SRWE

tSFW11tSFW10

tSFW12

Stable

StablePRDB0-7

tSFW9BPCS

Flash Write Cycle 19364A-60

Am79C961A 157



tSFR7

Stable

tSFR1 tSFR2

tSFR4tSFR3

REF,SBHE

SA0-15

MEMR

IOCHRDY

SROE

BPCS

Stable

tSFR8 tSFR9

tSFR10 tSFR11

PRDB0–7

SD0–7

tSFR5

tSFR6

Flash Read Cycle 19364A-61

158 Am79C961A



tPR13 tPR13

tPR15 tPR15

tPR14 tPR14

PRAB

SRWE

PRDB

SRCS(IRQ12)

SRAM Write on Private Bus (When FL_Sel is Enabled) 19364A-62

tPR4 tPR4

PRAB

SROE

PRDB

tPR6tPR5 tPR6 tPR5

SRCS(IRQ12)

SRAM Read on Private Bus (When FL_Sel is Enabled) 19364A-63

Am79C961A 159



tPR10 tPR10

PRAB

BPCS

PRDB

tPR12tPR11 tPR12 tPR11

Boot PROM Read on Private Bus 19364A-64

PRAB0–9

APCS(IRQ15)

PRDB

tPR9

Address PROM Read on Private Bus 19364A-65

tPR8

tPR7

160 Am79C961A



tPR17 tPR17

tPR14 tPR14

tPR18 tPR18

PRAB0

SRWE

PRDB

FLCS

Flash Write on Private Bus 19364A-66

tPR16 tPR16

PRAB0

PRDB

FLOE

FLCS

tPR12tPR11 tPR12tPR11

19364A-67Flash Read on Private Bus

Am79C961A 161


SWITCHING WAVEFORMS: GPSI

Notes:1. RXCRS is not present during transmission, LCAR bit in TMD3 will be set.

2. CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.

Transmit Clock

(STDCLK)

Transmit Data

(TXDAT)

Transmit Enable (TXEN)

Carrier Present

(RXCRS)(Note 1)

Collision(CLSN)

(Note 2)

(First Bit Preamble)

tGPT2

tGPT3

tGPT3 tGPT3

tGPT5

(Last Bit)

19364A-68Transmit Timing

tGPT1

tGPT9 tGPT6

tGPT7 tGPT8

tGPT4

Receive Clock

(SRDCLK)

(First Bit Preamble)(Address Type Designation Bit) (Last Bit)

tGPR2 tGPR3

tGPR4 tGPR5 tGPR5

tGPR6

tGPR8 tGPR9

tGPR11 tGPR12

Receive Data

(RXDAT)

Carrier Present

(RXCRS)

Collision (CLSN),

Active

Collision (CLSN),Inactive

tGPR4

Receive Timing 19364A-69

tGPR1

tGPR7tGPR10

(No Collision)

162 Am79C961A


SWITCHING WAVEFORMS: EADI

SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE

EAR (MAUSEL)

SRDCLK (LED3)

SRD (LED2)

SF/BD (LED1)tEAD4

tEAD1 tEAD2

One Zero One SFD Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 8 Bit 0 Bit 7 Bit 8

tEAD3 tEAD3

tEAD5tEAD6

Preamble Data Field

Reject

Accept

EADI Reject Timing 19364A-70

TCK

tJTG3 tJTG4tJTG2

tJTG5

TDI

TMS

TDO

tJTG6 tJTG7 tJTG8

Test Access Port Timing

tJTG1

19364A-71

Am79C961A 163


SWITCHING WAVEFORMS: AUI

Note:1. Internal signal and is shown for clarification only.

tXI

tDOTR tDOTF

tX1H

tX1L tX1F tX1R

1 1

0

1

XTAL1

ISTDCLK(Note 1)

ITXDAT+(Note 1)

DO+

DO–

DO±

0

1

1

ITXEN(Note 1)

19364A-72

Transmit Timing—Start of Packet

164 Am79C961A




Typical > 200 ns

tDOETD

XTAL1

ISTDCLK(Note 1)

ITXEN(Note 1)

ITXDAT+(Note 1)

DO+

DO–

DO±

0

1

0

01 0

Bit (n–2) Bit (n–1) Bit (n)

1

19364A-73

Transmit Timing—End of Packet (Last Bit = 0)

Am79C961A 165



Note: 1. Internal signal and is shown for clarification only.

Typical > 250 ns

XTAL1

ITXEN(Note 1)

ITXDAT+(Note 1)

DO+

DO–

DO±

0

1 1

01


1

ISTDCLK(Note 1)


tDOETD

19364A-74

166 Am79C961A



DI+/–

VASQ

tPWODI

tPWKDI

tPWKDI

Receive Timing Diagram 19364A-75

CI+/–

VASQ

tPWOCItPWKCI

tPWKCI

Collision Timing Diagram 19364A-76

tDOETD

DO+/–40 mV

100 mV max.0 V

Port DO ETD Waveform A19364-77

80 Bit Times

Am79C961A 167


SWITCHING WAVEFORMS: 10BASE-T INTERFACE


tTR tTF

tTETDTXD+

TXP+

TXD–

TXP–

XMT(Note 1)

Transmit Timing 19364A-78

TXD+

tPERLPtPWLP

tPWPLP

TXP+

TXD–

TXP–

Idle Link Test Pulse 19364A-79

168 Am79C961A



RXD±

VTSQ+

VTSQ–

VTHS–

VTHS+

Receive Thresholds (LRT = 0 in CSR15 bit 9) 19364A-80

RXD±

VLTSQ+

VLTSQ–

VLTHS–

VLTHS+

Receive Thresholds (LRT = 1 in CSR15 bit 9)19364A-81

Am79C961A 169


PHYSICAL DIMENSIONS*

PQB132Plastic Quad Flat Pack Trimmed and Formed (measured in inches)

Pin 132

Pin 99

Pin 66

Pin 1 I.D.

16-038-PQB PQB132 DB87 7-26-94 ae

TOP VIEW

1.097 1.103

0.947 0.953

1.075 1.085

1.097 1.103

0.008 0.012

Pin 33

1.075 1.085 0.947

0.953

0.025 BASIC

0.160 0.180

0.80 REF

BOTTOM VIEW

0.130 0.150

0.020 0.040

SEATING PLANE

170 Am79C961A


PHYSICAL DIMENSIONS*PQB132Molded Carrier Ring Plastic Quad Flat Pack (measured in inches, Ring measured in millimeters)

Trademarks

Copyright © 1996 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, MAGIC Packet and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

16-0000038-PQB-1 PQB132 (Molded) DA84 6-14-94 ae

45.87 46.1345.50

45.9041.37 41.6337.87

38.1335.15 35.25 32.15

32.251.097 1.103.944

.952

.944

.952

1.097 1.103

32.15 32.25

35.15 35.25

37.87 38.13

41.37 41.63

45.50 45.90

45.87 46.13

.750 NOM.

Pin 132

Pin 1

4.802.00

256 NOM.

SIDE VIEW

1.50 DIA.

1.80

Pin 99

Pin 66

Z1 1.50 DIA.

Pin 33

Z2 1.50 DIA.

Am79C961A 171



KS000010

Must beSteady

MayChangefrom H to L

MayChangefrom L to H

Does Not Apply

Don’t Care,Any ChangePermitted

Will beSteady

Will beChangingfrom H to L

Will be Changing from L to H

Changing,StateUnknown

Center Line is High-Impedance“Off” State

WAVEFORM INPUTS OUTPUTS

Am79C961A 139



19364A-29

CL

VTHRESHOLD

IOL

IOH

Normal and Three-State Outputs

Sense Point

19364A-30

AVDD

DO+

154 Ω100 pF

DO–

AVSS

52.3 Ω

Test Point

AUI DO Switching Test Circuit

140 Am79C961A



TXD Switching Test Circuit

DVDD

TXD+

294 Ω100 pF

TXD–

DVSS

294 Ω

Test Point

19364A-31

Includes Test Jig Capacitance

TXD Outputs Test Circuit

DVDD

TXP+

715 Ω100 pF

TXP–

DVSS

715 Ω

Test Point

Includes TestJig Capacitance

19364A-32

Am79C961A 141




19364A-33

AEN, SBHE,SA0–9

IOW

SD

tIOW5 tIOW6

tIOW4

tIOW1 tIOW3tIOW2

Stable

AEN, SBHE,SA0–9

IOW

SD

tIOW5 tIOW6

tIOW4

tIOW1 tIOW2

Stable

IOCHRDY

tIOW7tIOW8 tIOW9

19364A-34


142 Am79C961A



Serial Shift EEPROM Interface Read Timing19364A-35

EESK(PRDB0)

EECS

EEDI(PRDB1)

EEDO(PRDB2)

SHFBUSY

0 1 1 A7 A6 A5 A4 A3 A2 A1 A0

D0 D1 D2 D14 D15

Falling transition at 26th Word, if checksum is 0xFF.

0

19364A-36

Serial EEPROM Control Timing

EESK(PRDB0)

EECS

EEDI(PRDB1)

SHFBSY

EED0(PRDB2)

tSR1 tSR2

tSR3 tSR4 tSR5

Stable

tSR6 tSR7

Am79C961A 143



Slave Serial EEPROM Latency Timing 19364A-37

tSL1

tSL2

tSL3

EED0(PRDB2)

IOR

IOCHRDY

IOW

EESK, EEDI,EECS,

SHFBUSY

19364A-38

I/O Read without Wait States

AEN, SBHE,SA0–9

IOR

SD

tIOR5

tIOR4

tIOR3

tIOR1 tIOR2

Stable

Stable

144 Am79C961A



I/O Read with Wait States19364A-39

AEN, SBHE,SA0–9

IOR

SD

tIOR8 tIOR4

tIOR3

tIOR1 tIOR2

Stable

IOCHRDY

tIOR6 tIOR7

Stable

19364A-40I/O to Memory Command Inactive Time

IOW, MEMW

MEMR, IOR

tIOM1 tIOM2

Am79C961A 145



IOCS16 Timings

19364A-41

AEN, SBHE,SA0–9

IOCS16

tIOCS1 tIOCS2

19364A-42Bus Acquisition

tMMA1

tMMA2

tMMA3

tMMA4

tMMA5

REF

DRQ

DACK

MASTER

MEMR/MEMW

SBHE,SA0–19,LA17–23

146 Am79C961A



Bus Release19364A-43

tMMBR1

tMMBR4

DRQ

DACK

MASTER

MEMR/MEMW

tMMBR2

tMMBR3


19364A-44Write Cycles

tMMW1tMMW2 tMMW3

tMMW4

tMMW7 tMMW8 tMMW9

tMMW5 tMMW6


MEMW

IOCHRDY

SD0–15


tMMW11tMMW10

Am79C961A 147



tMMR1tMMR2 tMMR3

tMMR4

tMMR7 tMMR8 tMMR9

tMMR10 tMMR11tMMR10 tMMR11

Stable Stable

Stable Stable

tMMR5 tMMR6


MEMR

IOCHRDY

SD0–15

19364A-45


Read Cycles

Stable

Stable

tIOR1 tIOR2

tIOR3

tMA5

tIOR6

tMA1tMA2

tMA3 tMA4

tMA6 tIOR4

AEN, SBHE,SA0–9

IOR

IOCHRDY

APCS(IRQ15)

PRDB0–7

SD0–7

19364A-46External Address PROM Read Cycle

148 Am79C961A



Stable

Stable

tMB1 tMB2

tMB4tMB7

tMB3

tMB5tMB6

tMB8 tMB9

tMB10 tMB11

REF, SBHE,SA0–19

MEMR

IOCHRDY

BPCS

PRDB0–7

SD0–7

19634A-47

BALE

StableLA20–23

tMB12

tMB13

tMB14

Boot PROM Read Cycle

Am79C961A 149



Stable

Stable

tMFR1 tMFR2

tMFR4tMFR7

tMFR3

tMFR5tMFR6

tMFR8 tMFR9

tMFR10 tMFR11

REF, SBHE,SA0–19

MEMR

IOCHRDY

BPCS

PRDB0–7

SD0–7

19364A-48

BALE

StableLA20–23

tMFR12

tMFR13

tMFR14

Flash Read Cycle

150 Am79C961A



tMFW5

Stable

tMFW1 tMFW2

tMFR4tMFW3

tMFW7

SBHE,SA0–19

MEMW

IOCHRDY

SD0-7

BALE

StableLA20–23

tMFW13

tMFW14

tMFW15 tMFW6

tMFW8

FL_WE (IRQ12)

tMFW11tMFW10

tMFW12

Stable

StablePRDB0-7

19364A-49

tMFW9

Flash Write Cycle

Am79C961A 151




IOW

SD

tIOW6tIOW5

19364A-50

tIOW2tIOW1

tIOW3

tIOW4


StableAEN, SBHE,

SA0–9

IOW

SD

tIOW6tIOW5

19664A-51

IOCHRDY

tIOW1 tIOW2

tIOW7 tIOW8tIOW9

tIOW4


152 Am79C961A



tIOR1


IOR

SD

tIOR4tIOR5

Stable

tIOR2

tIOR3

19364A-52I/O Write without Wait States


IOR

tIOR2

IOCHRDY

SD

tIOR4

Stable

tIOR3tIOR6 tIOR7

tIOR1

tIOR8

19364A-53I/O Read with Wait States

Am79C961A 153



StableSA0–15,SBHE

SMAM

SD

tMW2

tMW6tMW5

MEMWtMW4

tMW1tMW3

19364A-54Memory Write without Wait States

StableSA0–15,

SBHE

SMAM

SD

tMW4

tMW6tMW5

MEMW

tMW7tMW8 tMW9

IOCHRDY

tMW2tMW1


154 Am79C961A