DESIGNREVIEW

fig.2 Designing the anti-aliasing filter: Cut-off and Roll-off

Signal Power

Signal Power

Lower Order, shallow roll-off LPF required

High Order, steep roll-off LPF required

Sampling rate mUCh greater than Nyquist

Sampling rate JUST greater than Nyquist

fig.1 aliasing

Signal Power Signal Power

Aliased Frequencies

fS < 2f

max: aliasingf

S > 2f

max: No aliasing

DESIGNREVIEW

fig. 3 frequency response of digitally-controlled fi lters on aN0 and aN1

f Hz1000000100000100001000100

dB

0

-20

-40

-60

2-Pole Filters, AN0 or AN1Roll-off = -40dB/decade

4-Pole Filter, AN0 + AN1Roll-off = -80dB/decade

Filter cut-off range AN0 or AN1

listing 1. C code for calculating the aN0 fi lter resistance values

Rf = 6772556u/Fcut_off; /* Calculate filter R2 resistor value */

R2_Pot = 12000u*Rf/(12000u-Rf); /* Digital pot in parallel with 12k resistor */

R1_Pot = R2_Pot/2u; /* R1 resistor value = R2/2 */

Set_resistance(1u,R1_Pot); /* Call AN16 driver and set Pot channel 1 */

Set_resistance(2u,R2_Pot); /* Call AN16 driver and set Pot channel 2 */

24 eTech - ISSUE 6

CONNECTING ThE aNalOGUE WORlD TO RS EDPanalogue Input module: Setting up the anti-aliasing filter

Get the Specifi cationBefore the considering the analogue input to a digital system, the designer must have available a certain amount of numerical data:

• The maximum frequency component of the analogue signal

• The Dynamic Range of the analogue signal (ratio of the maximum to the minimum input signal level)

• The required Signal-to-Noise ratio of the digitized signal

The fi rst point is what concerns us here when deciding on the cut-off frequency of the input analogue low-pass-fi lter.

Decide on the sampling rateThe sampling rate is set according to the Nyquist criterion which states that it must be at least twice that of the maximum frequency component present in the analogue signal. This ensures accurate reproduction of the signal, but a much higher rate will ease the design of a vital circuit that precedes the ADC: the Anti-Aliasing fi lter.

eTech - ISSUE 6 25

Design considerations for the anti-aliasing filter

The frequency plots in Fig.1 provide a graphical representation of aliasing. In this example we are going to sample a signal which has a maximum frequency component of fmax (the band in green) using a sampling frequency of fs. The plot on the left shows all the new frequencies present in the non-aliased sampled signal. Note that we now have new bands of frequencies (in blue) each with a width of 2 x fmax and centred on the sampling frequency ƒs and its harmonics. This is a correctly sampled signal because fs > 2 x fmax. By contrast the plot on the right shows extensive aliasing where the various bands overlap leading to the production of erroneous frequencies in the green baseband.

The practical problem is that few ‘raw’ signals have a nice, clean fmax. In order to avoid aliased components being produced, a low-pass anti-aliasing fi lter needs to be placed in circuit before the ADC.

Fig.2 shows the trade-off between sampling rate and the order of the low-pass fi lter. The designer can massively over-sample and then use a simple low-order fi lter or select a lower rate and then be faced with the need for a complex multi-pole type. However the ability of the DSP device to process the algorithm between consecutive samples must be considered before the sampling rate is set. It can save a lot of trouble later if the DSP program is tested and timed on a suitable development system before the sampling rate is fi xed and the fi lter designed.

anti-aliasing filters on the analogue Input module (EDP-am-aN16)Sallen-Key fi lters are used on the Analogue Input module which provides fi lter circuits for up to 16 input channels. Eight have simple passive 1-pole fi lters, six have fi xed cut-off (12kHz) 2-pole Sallen-Key fi lters with a roll-off of -40dB/decade and two have 2-pole fi lters whose cut-off frequency can be set by digital potentiometers. These two fi lters on channels AN0 and AN1 can be cascaded by means of a solder-link to provide a single 4-pole fi lter on AN0 with -80dB/decade roll-off.

Programming the Digital PotentiometersThe potentiometers are programmed from an I2C serial bus with two allocated to each fi lter controlling the resistive components which set the cut-off frequency. [1] Advantage is taken of a simplifi cation of the Sallen-Key fi lter which occurs when the two resistances and two capacitances are in the ratio 2 to 1. [2]

Resources[1] Software drivers for the AN16 module together with full code listings of sample programs can be downloaded from the EDP Design Centre on the DesignSpark website at: http://www.designspark.com/design-centre.

[2] Analysis of the Sallen-Key Architecture, TI Application Report, SLOA024B.

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