error detection correction

5/20/2018 Error Detection Correction

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Chapter 7

Types of error

Detection Correction

Error Detectionand Correction


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7.1 Types of Errors

Single bit error

only one bit is changed from 1 to 0or from 0 to 1.

Burst error two or more bits in the data unit havechanged.


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7.2 Detection

Error detection uses the concepts of redundancy,which means adding extra bits detecting errors atthe destination.


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(normally implemented in link layer)

(usedprimarily byupper layers)

3 common error detection techniques

Parity Check

Cyclic Redundancy Check (CRC)

Checksum

(most basic)


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Parity check: 2 method

VRC Vertical Redundancy Check

LRC Longitudanal Redundancy Check

Redundancy ????


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Parity : 2 type

Odd parity

Even parity


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Parity Check

Simplest technique.

A redundant bit (parity bit), is appended to every dataunit.

Even parity - the total number of 1's in the data plusparity bit must be an even number.


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Data 1's in data P Total 1's (data and P)

0110110 4 (Even) 0 4 (Even)

0011111 5 (Odd) 1 6 (Even)0000000 0 (Even) 0 0 (Even)

1010100 3 (Odd) 1 4 (Even)

1111111 7 (Odd) 1 8 (Even)

Even Parity Generator


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example

Vertical Redundancy Check (VRC)


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Example 1

Even Parity

Suppose the sender wants to send the word world. In

ASCII the five characters are coded as1110111 1101111 1110010 1101100 1100100

The following shows the actual bits sent

11101110 11011110 11100100 11011000 11001001


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Example 2

Even Parity

Now suppose the word world in Example 1 is received by

the receiver without being corrupted in transmission.11101110 11011110 11100100 11011000 11001001

The receiver counts the 1s in each character and comes up

with even numbers (6, 6, 4, 4, 4). The data are accepted.


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Example 3

Even Parity

Now suppose the word world in Example 1 is corrupted

during transmission.11111110 11011110 11101100 11011000 11001001

The receiver counts the 1s in each character and comes up

with even and odd numbers (7, 6, 5, 4, 4). The receiverknows that the data are corrupted, discards them, and asks

for retransmission.


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VRC Performance

VRC can detect all single-bit errors. It can also detect burst errorsas long as the total number of bits changed is odd (1,3,5etc)

How bout if the total number of bit changed is even ??? Yea.. Thereis problem !!!

In short VRC can detect all single-bit errors. It can detect bursterrors only if the total number of errors in each data unit is odd.


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LONGITUDINAL REDUNDANCY CHECK

(LRC)

IN longitudinal redundancy check LRC, a block of bits is

divided into rows and a redundant row of bits is added to

the whole block


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Original data

11100111 11011101 00111001 10101001

1 1 1 0 0 1 1 1

1 1 0 1 1 1 0 1

0 0 1 1 1 0 0 1

1 0 1 0 1 0 0 1

-----------------

1 0 1 0 1 0 1 0 LRC

11100111 11011101 00111001 10101001 10101010

The above is the original data plus LRC


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e.g. problem in LRCSuppose the following block is sent

10101001 00111001 11011101 11100111 10101010

(LRC)

However, it is hit by a burst noise of length eight and some bits are corrupted.

10100011 10001001 11011101 11100111 10101010(LRC)

When the receiver checks the LRC, some of the bits do not follow the even-

parity rule and the whole block is discarded (the nonmatching bits are shown in

blue)

10100011 10001001 11011101 11100111 10101010

(LRC)


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Performance of LRC

LRC increases the likelihood of detecting burst errors. As weshowed in the previous e.g. an LRC of n bits can easily detect aburst error of n bits.

A burst error of more than n bits is also detected by LRC with a veryhigh probability.

-note for Jabatan Tanah daerah TemerlohMr. Hakim (2004co)


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7.5 CRC

The most powerful of the redundancy checkingtechnique.

Based on binary division.

The redundancy bits used by CRC are derived bydividing the data unit by a predetermined divisor;the remainder is the CRC.

A CRC must:

have exactly one less bit than the divisor appending it to the end of the data string must

make the resulting bit sequence exactly divisibleby the divisor.


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7.9 CRC generator and checker

1. Get the raw frame.

2. Left shift the raw frame by n bitsand divide it by divisor.

3. The remainder is the CRC bit.

4. Append the CRC bit to the frame

and transmit.

1. Receive the frame.

2. Divide it by divisor.3. Check the reminder.


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Figure 10.15 Division in CRC encoder


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Figure 10.16 Division in the CRC decoder for two cases


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7.5 CRC

CRC generator at the sending node.

CRC checker at the receiving node.

Polynomial:

The CRC generator (the divisor) is most oftenrepresented as an algebraic polynomial.

e.g.


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7.13 A polynomial representing a divisor


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Table 7.2 Standard polynomials

Name Polynomial Application

CRC-8 x8 +x2 +x+1 ATM header

CRC-10 x10

+x9

+x5

+x4

+x2

+1 ATM AALITU-16 x16+x12+x5 + 1 HDLC

ITU-32x32+x26 +x23+x22+x16+x12+x11+x10

+x8+x7+x5+x4+x2+x +1LANs


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7.6 Checksum

The error detection used by the higher-layerprotocols.

Check generator

in the sending node Checksum checker at receiving node

Ethernet frame


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Checksum generator

In the sender, the checksum generator subdivides thedata unit into equal segments of n bits (usually 16).

These segments are added together using onescomplement arithmetic in such a way that the total is

also n bits long. The total(sum) is then complemented and appended to

the end of the original data unit as redundancy bits,called checksum field.

The extended data unit is transmitted across thenetwork.

So if the sum of the data segment is T, the checksumwill be -T

7 15 D i d h k


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7.15 Data uni t and checksum


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Checksum checker

The receiver subdivides the data unit as above and addsall segments together and complements the result.

If the extended data unit is intact, the total value foundby adding the data segments and the checksum field

shud be zero.

If the result is not zero, the packet contains an error andthe receiver rejects it.


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The sender follows these steps:

The unit is divided into k sections, each ofn bits

All sections are added together usingones complement to get the sum.

The sum is complemented and becomesthe checksum.

The checksum is sent with the data.


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The receiver follows these steps

The unit is divided into k sections, each ofn bits.

All sections are added together usingones complement to get the sum.

The sum is complemented.

If the result is zero, the data are accepted.Otherwise, they are rejected.


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Example 6

Suppose the following block of 16 bits is to be sent using a

checksum of 8 bits.

10101001 00111001

The numbers are added using ones complement

10101001

00111001

------------

Sum 11100010

Checksum 00011101

The pattern sent is 10101001 00111001 00011101


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Example 7

Now suppose the receiver receives the pattern sent in Example 6

and there is no error.

10101001 00111001 00011101

When the receiver adds the three sections, it will get all 1s, which,

after complementing, is all 0s and shows that there is no error.10101001

00111001

00011101

------------

Sum 11111111

Complement 00000000 means that the pattern is OK.


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Example 8

Now suppose there is a burst error of length 5 that affects 4 bits.

Original data 10101001 00111001 00011101

Corrupted data 10101111 11111001 00011101

When the receiver adds the three sections, it gets

10101111

11111001

00011101

Partial Sum 111000101

Carry 1

Sum 11000110

Complement 00111001 the pattern is corrupted.


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7.7 Error Correction

Hamming Code

Focus on a simple case: Single-Bit ErrorCorrection

Use the relationship between data andredundancy bits

Developed by Richard Hamming


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Data and redundancy bits

Number of

data bits

m

Number of

redundancy bits

r

Total

bits

m + r

1 2 3

2 3 5

3 3 6

4 3 7

5 4 9

6 4 10

7 4 11

To calculate the no. of redundancy bits use : 2r m + r + 1


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Positions of redundancy bits in Hamming code (11,7)

* Check bits occupy positions that are powers of 2

In the Hamming code, each r bit is the VRC bit for one combination of data bits:

r1is the VRC bit for one combination of data bits, r2is the VRC bit for another

combination of data bits, and so on. The combinations used to calculate each of the

four r values for a seven-bit data sequence are as follows:r1: bits 1, 3, 5, 7, 9, 11

r2: bits 2, 3, 6, 7, 10, 11

r4: bits 4, 5, 6, 7

r5: bits 8, 9, 10, 11


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All bit positions that are powers of 2 are used as parity bits. (positions 1, 2, 4,8)

All other bit positions are for the data to be encoded. (positions 3, 5, 6, 7, 9,10, 11)

Each parity bit calculates the parity for some of the bits in the code word. Theposition of the parity bit determines the sequence of bits that it alternatelychecks and skips.

General rule for position n: skip n1 bits, check nbits, skip nbits, check nbits...

Position 1 (n=1): skip 0 bit (0=n1), check 1 bit (n), skip 1 bit (n), check 1 bit(n), skip 1 bit (n), etc. (1,3,5,7,9,11...)

Position 2 (n=2): skip 1 bit (1=n1), check 2 bits (n), skip 2 bits (n), check 2bits (n), skip 2 bits (n), etc. (2,3,6,7,10,11...)

Position 4 (n=4): skip 3 bits (3=n1), check 4 bits (n), skip 4 bits (n), check 4bits (n), skip 4 bits (n), etc. (4,5,6,7,12...)

Position 8 (n=8): skip 7 bits (7=n1), check 8 bits (n), skip 8 bits (n), check 8bits (n), skip 8 bits (n), etc. (8-15,24-31,40-47,...)

7 18 Redundancy bits calculation


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7.18 Redundancy bits calculation


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r1will take care of these

bits

d d d d d dd r1r2r4r8

000101011011 0111 00111001

11 9 7 5 3 1


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r2will take care of these bits


001000110110011110101011

11 10 7 6 3 2


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01100111 0101 0100

7 6 45


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1000100110101011

11 10 9 8

7.19 Example of redundancy bit calculation


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7.19 Example of redundancy bit calculation

7.20 Single-Bi t Err or


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g

7.21b Er ror detection using Hamming code


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Error

Detection

g g


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Example Question

The data is 1011011

Add the parity bit.???????????????

Consider the transmitted data to be 00101010111.

Show how the error bit position is determined

???????????????


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answer

The data is 1011011

1. Add the parity bit.

2. Consider the transmitted data to be 00101010111.

Show how the error bit position is determined.

10101010111

1011 = 11


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THANK YOU

Hakim for Jab parit dan Saliran daerah Temerloh

error detection correction

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