EP93XXARM 9 Embedded Processor Family

EP93xxUse r s Gu id e

Copyright 2007 Cirrus Logic, Inc.http://www.cirrus.com

SEP 2007 DS785UM1

EP93xx Users Guide

Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.comCirrus Logic, Inc. and its subsidiaries (Cirrus) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided AS IS without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Microsoft, Windows, and Windows CE are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola is a registered trademark of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds. ARM and Thumb are registered trademarks of ARM Limited Intel is a registered trademark of Intel Corporation Hewlett-Packard is a registered trademark of Hewlett-Packard Corporation. Compaq is a registered trademark of BV, a private Limited Liability Company in the Netherlands.

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ContentsChapter Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiv Chapter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

Preface................................................................................................................... P-1P.1 About the EP93xx Users Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P.2 Related Documents from Cirrus Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P.3 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P.4 Notational Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P.5 Register Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-1 P-3 P-3 P-3 P-4

Chapter 1. Introduction ......................................................................................... 1-11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 1.2 EP93xx Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 1.3 EP93xx Processor Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7 1.4 EP93xx Processor Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7 1.4.1 High-Performance ARM920T Core .................................................................................1-7 1.4.2 MaverickCrunch Co-processor for Ultra-Fast Math Processing....................................1-7 1.4.3 MaverickKey Unique ID Secures Digital Content in OEM Designs ..............................1-8 1.4.4 Integrated Multi-Port USB 2.0 Full Speed Hosts with Transceivers ................................1-8 1.4.5 Integrated Ethernet MAC Reduces BOM Costs ..............................................................1-9 1.4.6 8x8 Keypad Interface Reduces BOM Costs ....................................................................1-9 1.4.7 Multiple Booting Mechanisms Increase Flexibility ...........................................................1-9 1.4.8 Abundant General Purpose I/Os Build Flexible Systems ................................................1-9 1.4.9 General-Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ...........................1-9 1.4.10 12-Bit Analog-to-Digital Converter (ADC) Provides an Integrated Touch-Screen Interface or General ADC Functionality ..........................................................1-10 1.4.11 Raster Analog / LCD Controller ...................................................................................1-10 1.4.12 Graphics Accelerator ...................................................................................................1-10 1.4.13 PCMCIA Interface........................................................................................................1-10

Chapter 2. ARM920T Core and Advanced High-Speed Bus (AHB)................... 2-12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.2 Overview: ARM920T Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.2.1 Features ..........................................................................................................................2-1 2.2.2 Block Diagram .................................................................................................................2-2 2.2.3 Operations .......................................................................................................................2-2 2.2.3.1 ARM9TDMI Core ...........................................................................................2-3 2.2.3.2 Memory Management Unit ............................................................................2-4 2.2.3.3 Cache and Write Buffer .................................................................................2-5 2.2.4 Co-processor Interface ....................................................................................................2-6 2.2.5 AMBA AHB Bus Interface Overview................................................................................2-6 2.2.6 AHB Implementation Details............................................................................................2-7 2.2.7 Memory and Bus Access Errors ......................................................................................2-9 2.2.8 Bus Arbitration .................................................................................................................2-9 2.2.8.1 Main AHB Bus Arbiter..................................................................................2-10 2.2.8.2 SDRAM Slave Arbiter ..................................................................................2-11 2.2.8.3 EBI Bus Arbiter ............................................................................................2-11 2.3 AHB Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.3.1 AHB Slave .....................................................................................................................2-11DS785UM1

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2.3.2 AHB-to-APB Bridge .......................................................................................................2-12 2.3.2.1 Function and Operation of the AHB-to-APB Bridge.....................................2-12 2.3.3 APB Slave .....................................................................................................................2-13 2.3.4 Register Definitions .......................................................................................................2-13 2.3.5 Memory Map..................................................................................................................2-16 2.3.6 Internal Register Map ....................................................................................................2-17 2.3.6.1 Memory Access Rules .................................................................................2-17

Chapter 3. MaverickCrunch Co-Processor ......................................................... 3-13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.1.1 Features ..........................................................................................................................3-1 3.1.2 Operational Overview ......................................................................................................3-1 3.1.3 Pipelines and Latency .....................................................................................................3-3 3.1.4 Data Registers.................................................................................................................3-3 3.1.5 Integer Saturation Arithmetic ...........................................................................................3-4 3.1.6 Comparisons ...................................................................................................................3-6 3.2 Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 3.2.1 Example 1........................................................................................................................3-8 3.2.1.1 Setup Code....................................................................................................3-8 3.2.1.2 C Code...........................................................................................................3-8 3.2.1.3 Accessing MaverickCrunch with ARM Co-Processor Instructions.................3-8 3.2.1.4 MaverickCrunch Assembly Language Instructions ........................................3-8 3.2.2 Example 2........................................................................................................................3-9 3.2.2.1 C Code...........................................................................................................3-9 3.2.2.2 MaverickCrunch Assembly Language Instructions ........................................3-9 3.3 DSPSC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10 3.4 ARM Co-Processor Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14 3.5 Instruction Set for the MaverickCrunch Co-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 3.5.1 Load and Store Instructions...........................................................................................3-21 3.5.2 Move Instructions ..........................................................................................................3-24 3.5.3 Accumulator and DSPSC Move Instructions .................................................................3-27 3.5.4 Copy and Conversion Instructions.................................................................................3-31 3.5.5 Shift Instructions ............................................................................................................3-35 3.5.6 Compare Instructions ....................................................................................................3-36 3.5.7 Floating Point Arithmetic Instructions ............................................................................3-38 3.5.8 Integer Arithmetic Instructions .......................................................................................3-41 3.5.9 Accumulator Arithmetic Instructions ..............................................................................3-45

Chapter 4. Boot ROM ............................................................................................ 4-14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.1.1 Boot ROM Hardware Operational Overview....................................................................4-1 4.1.1.1 Memory Map..................................................................................................4-1 4.1.2 Boot ROM Software Operational Overview .....................................................................4-1 4.1.2.1 Image Header ................................................................................................4-2 4.1.2.2 Boot Algorithm ...............................................................................................4-2 4.1.2.3 Flowchart .......................................................................................................4-3 4.2 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 4.2.1 UART Boot ......................................................................................................................4-6 4.2.2 SPI Boot ..........................................................................................................................4-6 4.2.3 FLASH Boot.....................................................................................................................4-6 4.2.4 SDRAM or SyncFLASH Boot ..........................................................................................4-7 Copyright 2007 Cirrus Logic, Inc.

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4.2.5 Synchronous Memory Operation.....................................................................................4-7

Chapter 5. System Controller ............................................................................... 5-15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.1.1 System Startup ................................................................................................................5-1 5.1.2 System Reset ..................................................................................................................5-1 5.1.3 Hardware Configuration Control ......................................................................................5-2 5.1.4 Software System Configuration Options..........................................................................5-4 5.1.5 Clock Control ...................................................................................................................5-4 5.1.5.1 Oscillators and Programmable PLLs .............................................................5-4 5.1.5.2 Bus and Peripheral Clock Generation ...........................................................5-5 5.1.5.3 Steps for Clock Configuration ........................................................................5-9 5.1.6 Power Management ........................................................................................................5-9 5.1.6.1 Clock Gatings ................................................................................................5-9 5.1.6.2 System Power States ..................................................................................5-10 5.1.7 Interrupt Generation ......................................................................................................5-12 5.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

Chapter 6. Vectored Interrupt Controller............................................................. 6-16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 6.1.1 Interrupt Priority ...............................................................................................................6-2 6.1.2 Interrupt Configuration.....................................................................................................6-3 6.1.3 Interrupt Details ...............................................................................................................6-4 6.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

Chapter 7. Raster Engine With Analog/LCD Integrated Timing and Interface ............................................................................................ 7-17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 7.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.3 Raster Engine Features Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3 7.3.1 Hardware Blinking ...........................................................................................................7-3 7.3.2 Color Look-Up Tables......................................................................................................7-4 7.3.3 Grayscale/Color Generation for Monochrome/Passive Low Color Displays ...................7-4 7.3.4 Frame Buffer Organization ..............................................................................................7-4 7.3.5 Frame Buffer Memory Size..............................................................................................7-6 7.3.6 Pulse Width Modulated Brightness..................................................................................7-6 7.3.7 Hardware Cursor .............................................................................................................7-7 7.4 Functional Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7 7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer Interface) ..........................7-8 7.4.2 Video FIFO ......................................................................................................................7-9 7.4.3 Video Pixel MUX............................................................................................................7-10 7.4.4 Blink Function ................................................................................................................7-10 7.4.5 Color Look-Up-Tables ...................................................................................................7-11 7.4.6 Color RGB Mux .............................................................................................................7-11 7.4.7 Pixel Shift Logic .............................................................................................................7-12 7.4.8 Grayscale/Color Generator for Monochrome/Passive Low Color Displays ...................7-15 7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters ........................................................7-16 7.4.8.2 VERT_CNT3, VERT_CNT4 Counters .........................................................7-16 7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters ...................................................7-16 7.4.8.4 HORZ_CNTx (pixel) timing ..........................................................................7-16 7.4.8.5 VERT_CNTx (line) timing ............................................................................7-16DS785UM1

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7.4.8.6 FRAME_CNTx timing ..................................................................................7-16 7.4.8.7 Grayscale Look-Up Table (GrySclLUT) .......................................................7-17 7.4.8.8 GrySclLUT Timing Diagram .........................................................................7-18 7.4.9 Hardware Cursor ...........................................................................................................7-24 7.4.9.1 Registers Used for Cursor ...........................................................................7-26 7.4.10 Video Timing................................................................................................................7-28 7.4.10.1 Setting the Video Memory Parameters......................................................7-31 7.4.10.2 PixelMode ..................................................................................................7-32 7.4.11 Blink Logic ...................................................................................................................7-32 7.4.11.1 BlinkRate ...................................................................................................7-32 7.4.11.2 Defining Blink Pixels ..................................................................................7-32 7.4.11.3 Types of Blinking .......................................................................................7-33 7.4.12 Color Mode Definition ..................................................................................................7-35 7.4.12.1 Pixel Look-up Table Mode .........................................................................7-35 7.4.12.2 Triple 8-bit Color Definition Mode ..............................................................7-35 7.4.12.3 16-bit 565 Color Definition Mode ...............................................................7-35 7.4.12.4 16-bit 555 Color Definition Mode ...............................................................7-35 7.5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-36

Chapter 8. Graphics Accelerator.......................................................................... 8-18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 8.2 Block Processing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 8.2.1 Copy ................................................................................................................................8-2 8.2.1.1 Transparency.................................................................................................8-2 8.2.1.2 Logical Mask..................................................................................................8-2 8.2.1.3 Logical Destination ........................................................................................8-2 8.2.1.4 Operation Precedence...................................................................................8-2 8.2.2 Remapping ......................................................................................................................8-3 8.2.3 Block Fills ........................................................................................................................8-3 8.2.4 Packed Memory Transfer ................................................................................................8-3 8.3 Line Draws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 8.3.1 Breshenham Line Draws .................................................................................................8-4 8.3.2 Pixel Step Line Draws .....................................................................................................8-4 8.4 Memory Organization for Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 8.4.1 Memory Organization for 1 Bit Per Pixel (bpp) ...............................................................8-5 8.4.2 Memory Organization for 4-Bits Per Pixel .......................................................................8-5 8.4.3 Memory Organization for 8-Bits Per Pixel .......................................................................8-5 8.4.4 Memory Organization for 16-Bits Per Pixel .....................................................................8-6 8.4.5 Memory Organization for 24-Bits Per Pixel .....................................................................8-7 8.4.6 Memory Map Access .......................................................................................................8-8 8.5 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8 8.5.1 Word Count .....................................................................................................................8-8 8.5.1.1 Example: 8 BPP mode...................................................................................8-8 8.5.1.2 Example: 24 BPP (packed) mode..................................................................8-9 8.5.2 Pixel End and Start..........................................................................................................8-9 8.5.2.1 4 BPP Word Layout .....................................................................................8-10 8.5.2.2 8 BPP Word Layout .....................................................................................8-11 8.5.2.3 16 BPP WORD Layout ................................................................................8-11 8.5.2.4 24 BPP mode...............................................................................................8-12 8.6 Register Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13 8.6.1 Breshenhams Algorithm Line Draw ..............................................................................8-13 8.6.2 Example of Breshenhams Algorithm Line Draw ...........................................................8-15 8.6.3 Block Fill Function .........................................................................................................8-16vi

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8.6.4 Block Copy Function......................................................................................................8-18 8.6.4.1 Example of Block Copy................................................................................8-21 8.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22

Chapter 9. 1/10/100 Mbps Ethernet LAN Controller ........................................... 9-19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 9.1.1 Detailed Description ........................................................................................................9-1 9.1.1.1 Host Interface and Descriptor Processor .......................................................9-1 9.1.1.2 Reset and Initialization...................................................................................9-2 9.1.1.3 Power-down Modes .......................................................................................9-2 9.1.1.4 Address Space ..............................................................................................9-2 9.1.2 MAC Engine ....................................................................................................................9-3 9.1.2.1 Data Encapsulation........................................................................................9-3 9.1.3 Packet Transmission Process .........................................................................................9-5 9.1.3.1 Carrier Deference ..........................................................................................9-5 9.1.4 Transmit Back-Off............................................................................................................9-7 9.1.4.1 Transmission .................................................................................................9-7 9.1.4.2 The FCS Field................................................................................................9-7 9.1.4.3 Bit Order ........................................................................................................9-8 9.1.4.4 Destination Address (DA) Filter .....................................................................9-8 9.1.4.5 Perfect Address Filtering ...............................................................................9-8 9.1.4.6 Hash Filter .....................................................................................................9-9 9.1.4.7 Flow Control.................................................................................................9-10 9.1.4.8 Receive Flow Control...................................................................................9-10 9.1.4.9 Transmit Flow Control..................................................................................9-10 9.1.4.10 Rx Missed and Tx Collision Counters ........................................................9-11 9.1.4.11 Accessing the MII ......................................................................................9-11 9.2 Descriptor Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13 9.2.1 Receive Descriptor Processor Queues .........................................................................9-13 9.2.2 Receive Descriptor Queue ............................................................................................9-13 9.2.3 Receive Status Queue...................................................................................................9-16 9.2.3.1 Receive Status Format ................................................................................9-18 9.2.3.2 Receive Flow ...............................................................................................9-21 9.2.3.3 Receive Errors .............................................................................................9-22 9.2.3.4 Receive Descriptor Data/Status Flow ..........................................................9-23 9.2.3.5 Receive Descriptor Example .......................................................................9-24 9.2.3.6 Receive Frame Pre-Processing...................................................................9-25 9.2.3.7 Transmit Descriptor Processor Queues.......................................................9-26 9.2.3.8 Transmit Descriptor Queue..........................................................................9-26 9.2.3.9 Transmit Descriptor Format .........................................................................9-28 9.2.3.10 Transmit Status Queue..............................................................................9-30 9.2.3.11 Transmit Status Format .............................................................................9-32 9.2.3.12 Transmit Flow ............................................................................................9-34 9.2.3.13 Transmit Errors ..........................................................................................9-35 9.2.3.14 Transmit Descriptor Data/Status Flow .......................................................9-36 9.2.4 Interrupts .......................................................................................................................9-37 9.2.4.1 Interrupt Processing.....................................................................................9-37 9.2.5 Initialization....................................................................................................................9-37 9.2.5.1 Interrupt Processing.....................................................................................9-38 9.2.5.2 Receive Queue Processing .........................................................................9-38 9.2.5.3 Transmit Queue Processing ........................................................................9-38 9.2.5.4 Other Processing .........................................................................................9-38 9.2.5.5 Transmit Restart Process ............................................................................9-39 9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-40DS785UM1

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Chapter 10. DMA Controller................................................................................ 10-110.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 10.1.1 DMA Features List.......................................................................................................10-1 10.1.2 Managing Data Transfers Using a DMA Channel .......................................................10-2 10.1.3 DMA Operations ..........................................................................................................10-3 10.1.3.1 Memory-to-Memory Channels ...................................................................10-3 10.1.3.2 Memory-to-Peripheral Channels ................................................................10-4 10.1.4 Internal M2P or P2M AHB Master Interface Functional Description............................10-4 10.1.5 M2M AHB Master Interface Functional Description.....................................................10-5 10.1.5.1 Software Trigger Mode ..............................................................................10-5 10.1.5.2 Hardware Trigger Mode for Internal Peripherals (SSP and IDE) and for External Peripherals without Handshaking Signals ...........................................10-6 10.1.5.3 Hardware Trigger Mode for External Peripherals with Handshaking Signals ................................................................................................10-6 10.1.6 AHB Slave Interface Limitations ..................................................................................10-6 10.1.7 Interrupt Interface ........................................................................................................10-6 10.1.8 Internal M2P/P2M Data Unpacker/Packer Functional Description ..............................10-6 10.1.9 Internal M2P/P2M DMA Functional Description ..........................................................10-7 10.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine ....................10-7 10.1.9.2 Data Transfer Initiation and Termination ...................................................10-9 10.1.10 M2M DMA Functional Description ...........................................................................10-10 10.1.10.1 M2M DMA Control Finite State Machine ...............................................10-10 10.1.10.2 M2M Buffer Control Finite State Machine..............................................10-12 10.1.10.3 Data Transfer Initiation ..........................................................................10-13 10.1.10.4 Data Transfer Termination.....................................................................10-15 10.1.10.5 Memory Block Transfer..........................................................................10-16 10.1.10.6 Bandwidth Control .................................................................................10-16 10.1.10.7 External DMA Request (DREQ) Mode ..................................................10-16 10.1.11 DMA Data Transfer Size Determination ..................................................................10-17 10.1.11.1 Software Initiated M2M and M2P/P2M Transfers ..................................10-17 10.1.11.2 Hardware-Initiated M2M Transfers ........................................................10-18 10.1.12 Buffer Descriptors....................................................................................................10-18 10.1.12.1 Internal M2P/P2M Channel Rx Buffer Descriptors ................................10-19 10.1.12.2 Internal M2P/P2M Channel Tx Buffer Descriptors.................................10-19 10.1.12.3 M2M Channel Buffer Descriptors...........................................................10-19 10.1.13 Bus Arbitration .........................................................................................................10-19 10.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20 10.2.1 DMA Controller Memory Map ....................................................................................10-20 10.2.2 Internal M2P/P2M Channel Register Map .................................................................10-21

Chapter 11. Universal Serial Bus Host Controller ............................................ 11-111.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 11.1.1 Features ......................................................................................................................11-1 11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 11.2.1 Data Transfer Types....................................................................................................11-2 11.2.2 Host Controller Interface..............................................................................................11-3 11.2.2.1 Communication Channels..........................................................................11-3 11.2.2.2 Data Structures..........................................................................................11-4 11.2.3 Host Controller Driver Responsibilities ........................................................................11-6 11.2.3.1 Host Controller Management.....................................................................11-6 11.2.3.2 Bandwidth Allocation .................................................................................11-6 11.2.3.3 List Management .......................................................................................11-7 11.2.3.4 Root Hub....................................................................................................11-7viii

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11.2.4 Host Controller Responsibilities...................................................................................11-8 11.2.4.1 USB States ................................................................................................11-8 11.2.4.2 Frame Management ..................................................................................11-8 11.2.4.3 List Processing ..........................................................................................11-8 11.2.5 USB Host Controller Blocks.........................................................................................11-9 11.2.5.1 AHB Slave .................................................................................................11-9 11.2.5.2 AHB Master ...............................................................................................11-9 11.2.5.3 HCI Slave Block.........................................................................................11-9 11.2.5.4 HCI Master Block.....................................................................................11-10 11.2.5.5 USB State Control ...................................................................................11-10 11.2.5.6 Data FIFO ................................................................................................11-10 11.2.5.7 List Processor ..........................................................................................11-10 11.2.5.8 Root Hub and Host SIE ...........................................................................11-10 11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11

Chapter 12. Static Memory Controller ............................................................... 12-112.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 12.2 Static Memory Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2 12.3 PCMCIA Interface (EP9315 Processor Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5 12.4 PC Card Memory-Mode Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8 12.5 PC Card Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8 12.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10 12.6.1 Bank Configuration Registers....................................................................................12-10 12.6.2 PCMCIA Configuration Registers (EP9315 Processor Only) ....................................12-13

Chapter 13. SDRAM, SyncROM, and SyncFLASH Controller.......................... 13-113.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 13.2 Booting from SyncROM or SyncFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 13.3 Address Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.4 SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4 13.5 Programming Mode Register: SDRAM Or SyncROM Device. . . . . . . . . . . . . . . . . . . . . . .13-6 13.6 SDRAM Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8 13.6.1 Entering Self Refresh Mode ........................................................................................13-8 13.6.2 Exiting Self Refresh Mode ...........................................................................................13-8 13.7 Programming Registers: SyncFLASH Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8 13.8 External Synchronous Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9 13.8.1 Chip Select SDCSN[3:0] Decoding .............................................................................13-9 13.8.2 Address/Data/Control Required by Memory System.................................................13-10 13.9 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17

Chapter 14. UART1 With HDLC and Modem Control Signals.......................... 14-114.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 14.2 UART Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 14.2.1 UART Functional Description ......................................................................................14-2 14.2.1.1 AMBA APB Interface .................................................................................14-2 14.2.1.2 DMA Block .................................................................................................14-2 14.2.1.3 Register Block............................................................................................14-2 14.2.1.4 Baud Rate Generator.................................................................................14-4 14.2.1.5 Transmit FIFO............................................................................................14-4 14.2.1.6 Receive FIFO.............................................................................................14-4 14.2.1.7 Transmit Logic ...........................................................................................14-4 14.2.1.8 Receive Logic ............................................................................................14-4DS785UM1

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14.2.1.9 Interrupt Generation Logic .........................................................................14-4 14.2.1.10 Synchronizing Registers and Logic .........................................................14-5 14.2.2 UART Operation ..........................................................................................................14-5 14.2.2.1 Error Bits....................................................................................................14-6 14.2.2.2 Disabling the FIFOs ...................................................................................14-6 14.2.2.3 System/diagnostic Loopback Testing ........................................................14-6 14.2.2.4 UART Character Frame.............................................................................14-6 14.2.3 Interrupts .....................................................................................................................14-7 14.2.3.1 UARTMSINTR ...........................................................................................14-7 14.2.3.2 UARTRXINTR............................................................................................14-7 14.2.3.3 UARTTXINTR ............................................................................................14-7 14.2.3.4 UARTRTINTR............................................................................................14-8 14.2.3.5 UARTINTR.................................................................................................14-8 14.3 Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8 14.4 HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8 14.4.1 Overview of HDLC Modes ...........................................................................................14-9 14.4.2 Selecting HDLC Modes ...............................................................................................14-9 14.4.3 HDLC Transmit..........................................................................................................14-11 14.4.4 HDLC Receive...........................................................................................................14-11 14.4.5 CRCs .........................................................................................................................14-12 14.4.6 Address Matching......................................................................................................14-12 14.4.7 Aborts ........................................................................................................................14-13 14.4.8 DMA...........................................................................................................................14-14 14.4.9 Writing Configuration Registers.................................................................................14-14 14.5 UART1 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14 14.5.1 Clocking Requirements .............................................................................................14-15 14.5.2 Bus Bandwidth Requirements ...................................................................................14-16 14.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-17

Chapter 15. UART2 .............................................................................................. 15-115.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1 15.2 IrDA SIR Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1 15.2.1 IrDA SIR Encoder/decoder Functional Description .....................................................15-1 15.2.1.1 IrDA SIR Transmit Encoder .......................................................................15-2 15.2.1.2 IrDA SIR Receive Decoder ........................................................................15-2 15.2.2 IrDA SIR Operation......................................................................................................15-3 15.2.2.1 System/diagnostic Loopback Testing ........................................................15-4 15.2.3 IrDA Data Modulation ..................................................................................................15-4 15.2.4 Enabling Infrared (Ir) Modes........................................................................................15-5 15.3 UART2 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-5 15.3.1 Clocking Requirements ...............................................................................................15-5 15.3.2 Bus Bandwidth Requirements .....................................................................................15-6 15.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7

Chapter 16. UART3 With HDLC Encoder........................................................... 16-116.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 16.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 16.2.1 UART3 Package Dependency.....................................................................................16-1 16.2.2 Clocking Requirements ...............................................................................................16-2 16.2.3 Bus Bandwidth Requirements .....................................................................................16-2 16.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3 Copyright 2007 Cirrus Logic, Inc.

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Chapter 17. IrDA .................................................................................................. 17-117.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 17.2 IrDA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 17.3 Shared IrDA Interface Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2 17.3.1 Overview......................................................................................................................17-2 17.3.2 Functional Description .................................................................................................17-2 17.3.2.1 General Configuration................................................................................17-3 17.3.2.2 Transmitting Data ......................................................................................17-3 17.3.2.3 Receiving Data ..........................................................................................17-5 17.3.2.4 Special Conditions .....................................................................................17-7 17.3.3 Control Information Buffering.......................................................................................17-8 17.4 Medium IrDA Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-8 17.4.1 Introduction..................................................................................................................17-8 17.4.1.1 Bit Encoding...............................................................................................17-8 17.4.1.2 Frame Format ............................................................................................17-9 17.4.2 Functional Description ...............................................................................................17-11 17.4.2.1 Baud Rate Generation .............................................................................17-11 17.4.2.2 Receive Operation ...................................................................................17-11 17.4.2.3 Transmit Operation ..................................................................................17-13 17.5 Fast IrDA Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-13 17.5.1 Introduction................................................................................................................17-14 17.5.1.1 4PPM Modulation ....................................................................................17-14 17.5.1.2 4.0 Mbps FIR Frame Format ...................................................................17-15 17.5.2 Functional Description ...............................................................................................17-17 17.5.2.1 Baud Rate Generation .............................................................................17-17 17.5.2.2 Receive Operation ...................................................................................17-18 17.5.2.3 Transmit Operation ..................................................................................17-19 17.5.3 IrDA Connectivity.......................................................................................................17-20 17.5.4 IrDA Integration Information ......................................................................................17-21 17.5.4.1 Enabling Infrared Modes..........................................................................17-21 17.5.4.2 Clocking Requirements............................................................................17-21 17.5.4.3 Bus Bandwidth Requirements .................................................................17-22 17.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-23

Chapter 18. Timers .............................................................................................. 18-118.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1 18.1.1 Features ......................................................................................................................18-1 18.1.2 16 and 32-bit Timer Operation.....................................................................................18-1 18.1.2.1 Free Running Mode ...................................................................................18-2 18.1.2.2 Pre-load Mode ...........................................................................................18-2 18.1.3 40-bit Timer Operation.................................................................................................18-2 18.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2

Chapter 19. Watchdog Timer.............................................................................. 19-119.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 19.1.1 Watchdog Activation....................................................................................................19-2 19.1.2 Clocking Requirements ...............................................................................................19-2 19.1.3 Reset Requirements....................................................................................................19-2 19.1.4 Watchdog Status .........................................................................................................19-2 19.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3

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Chapter 20. Real Time Clock With Software Trim ............................................ 20-120.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1 20.1.1 Software Trim ..............................................................................................................20-1 20.1.1.1 Software Compensation ............................................................................20-2 20.1.1.2 Oscillator Frequency Calibration................................................................20-2 20.1.1.3 RTCSWComp Value Determination ..........................................................20-2 20.1.1.4 Example - Measured Value Split Into Integer and Fractional Component .20-3 20.1.1.5 Maximum Error Calculation vs. Real Time Clock Accuracy.......................20-3 20.1.1.6 Real-Time Interrupt....................................................................................20-3 20.1.2 Reset Control...............................................................................................................20-4 20.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-4

Chapter 21. I2S Controller................................................................................... 21-121.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1 21.2 I2S Transmitter Channel Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-2 21.3 I2S Receiver Channel Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-5 21.3.1 Receiver FIFOs...........................................................................................................21-6 21.4 I2S Master Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-7 21.5 I2S Bit Clock Rate Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9 21.5.1 Example of the Bit Clock Generation...........................................................................21-9 21.5.2 Example of Right Justified LRCK format ...................................................................21-10 21.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-10 21.7 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-12 21.7.1 I2S TX Registers........................................................................................................21-12 21.7.2 I2S RX Registers .......................................................................................................21-19 21.7.3 I2S Configuration and Status Registers.....................................................................21-25 21.7.4 I2S Global Status Registers.......................................................................................21-29

Chapter 22. AC97 Controller.............................................................................. 22-122.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1 22.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-3 22.2.1 Channel Interrupts .......................................................................................................22-3 22.2.1.1 RIS.............................................................................................................22-3 22.2.1.2 TIS .............................................................................................................22-3 22.2.1.3 RTIS...........................................................................................................22-4 22.2.1.4 TCIS...........................................................................................................22-4 22.2.2 Global Interrupts ..........................................................................................................22-4 22.2.2.1 CODECREADY .........................................................................................22-4 22.2.2.2 WINT..........................................................................................................22-4 22.2.2.3 GPIOINT ....................................................................................................22-4 22.2.2.4 GPIOTXCOMPLETE .................................................................................22-5 22.2.2.5 SLOT2INT..................................................................................................22-5 22.2.2.6 SLOT1TXCOMPLETE ...............................................................................22-5 22.2.2.7 SLOT2TXCOMPLETE ...............................................................................22-5 22.3 System Loopback Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5 22.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-5

Chapter 23. Synchronous Serial Port ................................................................ 23-123.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1 23.3 SSP Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2 23.4 SSP Pin Multiplex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2xii

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23.5 Configuring the SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2 23.5.1 Enabling SSP Operation..............................................................................................23-2 23.5.2 Master/Slave Mode......................................................................................................23-3 23.5.3 Serial Bit Rate Generation...........................................................................................23-3 23.5.4 Frame Format.............................................................................................................23-3 23.5.5 Texas Instruments Synchronous Serial Frame Format .............................................23-4 23.5.6 Motorola SPI Frame Format ......................................................................................23-5 23.5.6.1 SPO Clock Polarity ....................................................................................23-5 23.5.6.2 SPH Clock Phase ......................................................................................23-5 23.5.7 Motorola SPI Format with SPO=0, SPH=0..................................................................23-5 23.5.8 Motorola SPI Format with SPO=0, SPH=1.................................................................23-7 23.5.9 Motorola SPI Format with SPO=1, SPH=0..................................................................23-8 23.5.10 Motorola SPI Format with SPO=1, SPH=1................................................................23-9 23.5.11 National Semiconductor Microwire Frame Format .............................................23-10 23.5.11.1 Setup and Hold Time Requirements on SFRMIN with Respect to SCLKIN in Microwire Mode ..................................................................23-12 23.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-13

Chapter 24. Pulse Width Modulator ................................................................... 24-124.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1 24.2 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1 24.2.1 PWM Programming Examples ....................................................................................24-2 24.2.1.1 Example.....................................................................................................24-2 24.2.1.2 Static Programming (PWM is Not Running) Example ...............................24-2 24.2.1.3 Dynamic Programming (PWM is Running) Example .................................24-3 24.2.2 Programming Rules.....................................................................................................24-3 24.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-3

Chapter 25. Analog Touch Screen Interface ..................................................... 25-125.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1 25.2 Touch Screen Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-1 25.2.1 Touch Screen Scanning: Four-wire and Eight-wire Operation ....................................25-4 25.2.2 Five-wire and Seven-wire Operation .........................................................................25-10 25.2.3 Direct Operation ........................................................................................................25-12 25.2.4 Measuring Analog Input with the Touch Screen Controls Disabled ..........................25-13 25.2.5 Measuring Touch Screen Resistance........................................................................25-15 25.2.6 Polled and Interrupt-Driven Modes............................................................................25-16 25.2.7 Touch Screen Package Dependency ........................................................................25-16 25.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25-17

Chapter 26. Keypad Interface ............................................................................. 26-126.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-1 26.2 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-2 26.2.1 Apparent Key Detection...............................................................................................26-3 26.2.2 Scan and Debounce ....................................................................................................26-5 26.2.3 Interrupt Generation ....................................................................................................26-5 26.2.4 Low Power Mode.........................................................................................................26-6 26.2.5 Three-key Reset ..........................................................................................................26-6 26.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26-6

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Chapter 27. IDE Interface .................................................................................... 27-127.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1 27.2 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1 27.2.1 Diagrams and State Machines ....................................................................................27-2 27.2.2 PIO Operations............................................................................................................27-3 27.2.3 MDMA Operations .......................................................................................................27-4 27.2.4 UDMA Operations .......................................................................................................27-5 27.2.5 Performance Considerations .......................................................................................27-5 27.2.6 UDMA Example ...........................................................................................................27-6 27.2.7 DMA Request Latency.................................................................................................27-7 27.2.7.1 DMA Request Deassertion ........................................................................27-7 27.2.7.2 DMA Request Latency Overview...............................................................27-7 27.2.7.3 IDE DMA Programming Considerations ....................................................27-8 27.2.8 IDE Package Dependency ..........................................................................................27-9 27.2.8.1 System Configuration Constraints .............................................................27-9 27.2.8.2 Bus Bandwidth Requirements ...................................................................27-9 27.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-10

Chapter 28. GPIO Interface ................................................................................. 28-128.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-1 28.1.1 Memory Map................................................................................................................28-3 28.1.2 Functional Description .................................................................................................28-3 28.1.3 Reset ...........................................................................................................................28-5 28.1.4 GPIO Pin Map .............................................................................................................28-6 28.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-9

Chapter 29. Security............................................................................................ 29-129.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-1 29.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-1 29.3 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-1 29.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29-2

Chapter 30. Glossary........................................................................................... 30-1 Chapter 31. EP93XX Register List...................................................................... 31-1

FiguresFigure 1-1. EP9301 Block Diagram ...............................................................................................................1-2 Figure 1-2. EP9302 Block Diagram ..............................................................................................................1-3 Figure 1-3. EP9307 Block Diagram ...............................................................................................................1-3 Figure 1-4. EP9312 Block Diagram ...............................................................................................................1-4 Figure 1-5. EP9315 Block Diagram ...............................................................................................................1-4 Figure 2-1. ARM920T Block Diagram ...........................................................................................................2-2 Figure 2-2. Typical AMBA AHB System ........................................................................................................2-7 Figure 2-3. Main Data Paths .........................................................................................................................2-8 Copyright 2007 Cirrus Logic, Inc.

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Figure 4-1. Flow Chart of Boot ROM Software..............................................................................................4-4 Figure 4-2. Flow chart of Boot Sequence for 16-bit SDRAM Devices ...........................................................4-7 Figure 5-1. Phase Locked Loop (PLL) Structure ...........................................................................................5-4 Figure 5-2. Clock Generation System ...........................................................................................................5-6 Figure 5-3. Bus Clock Generation .................................................................................................................5-7 Figure 5-4. Power States and Transitions ...................................................................................................5-11 Figure 6-1. Vectored Interrupt Controller Block Diagram ..............................................................................6-2 Figure 7-1. Raster Engine Block Diagram .....................................................................................................7-8 Figure 7-2. Video Buffer Diagram..................................................................................................................7-9 Figure 7-3. Graphics Matrix for 50% Duty Cycle .........................................................................................7-20 Figure 7-4. Sample Matrix Causing Flickering ............................................................................................7-21 Figure 7-5.. Sample Matrix That Avoids Flickering......................................................................................7-21 Figure 7-6. Programming for One-third Luminous Intensity ........................................................................7-22 Figure 7-7. Creating Bit Patterns that Move to the Right.............................................................................7-23 Figure 7-8. Three and Four Count Axis .......................................................................................................7-24 Figure 7-9. Progressive/Dual Scan Video Signals ......................................................................................7-29 Figure 7-10. Interlaced Video Signals .........................................................................................................7-30 Figure 9-1. 1/10/100 Mbps Ethernet LAN Controller Block Diagram.............................................................9-1 Figure 9-2. Ethernet Frame / Packet Format (Type II only)...........................................................................9-4 Figure 9-3. Packet Transmission Process.....................................................................................................9-5 Figure 9-4. Carrier Deference State Diagram ...............................................................................................9-6 Figure 9-5. Data Bit Transmission Order.......................................................................................................9-8 Figure 9-6. CRC Logic...................................................................................................................................9-9 Figure 9-7. Receive Descriptor Format and Data Fragments .....................................................................9-14 Figure 9-8. Receive Status Queue ..............................................................................................................9-17 Figure 9-9. Receive Flow Diagram ............................................................................................................9-21 Figure 9-10. Receive Descriptor Data/Status Flow .....................................................................................9-23 Figure 9-11. Receive Descriptor Example...................................................................................................9-24 Figure 9-12. Receive Frame Pre-processing ..............................................................................................9-25 Figure 9-13. Transmit Descriptor Format and Data Fragments ..................................................................9-27 Figure 9-14. Multiple Fragments Per Transmit Frame ................................................................................9-28 Figure 9-15. Transmit Status Queue ...........................................................................................................9-31 Figure 9-16. Transmit Flow Diagram ...........................................................................................................9-34 Figure 9-17. Transmit Descriptor Data/Status Flow ....................................................................................9-36 Figure 10-1. DMA M2P/P2M Finite State Machine .....................................................................................10-7 Figure 10-2. M2M DMA Control Finite State Machine...............................................................................10-10 Figure 10-3. M2M DMA Buffer Finite State Machine.................................................................................10-12DS785UM1

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Figure 10-4. Edge-triggered DREQ Mode .................................................................................................10-17 Figure 11-1. USB Focus Areas ...................................................................................................................11-2 Figure 11-2. Communication Channels .......................................................................................................11-3 Figure 11-3. Typical List Structure ..............................................................................................................11-4 Figure 11-4. Interrupt Endpoint Descriptor Structure ..................................................................................11-5 Figure 11-5. Sample Interrupt Endpoint Schedule ......................................................................................11-6 Figure 11-6. USB Host Controller Block Diagram .......................................................................................11-9 Figure 12-1. 32-bit Read, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive.................................12-3 Figure 12-2. 32-bit Write, 32-bit Memory, 0 Wait Cycles, RBLE = 1, WAITn Inactive.................................12-3 Figure 12-3. 16-bit Read, 16-bit Memory, RBLE = 1, WAITn Active ...........................................................12-4 Figure 12-4. 16-bit Write, 16-bit Memory, RBLE = 1, WAITn Active ...........................................................12-4 Figure 12-5. Single PC Card Interface ........................................................................................................12-7 Figure 14-1. UART Block Diagram ..............................................................................................................14-3 Figure 14-2. UART Character Frame .........................................................................................................14-6 Figure 14-3. UART Character Frame ..........................................................................................................14-6 Figure 15-1. IrDA SIR Encoder/decoder Block Diagram .............................................................................15-2 Figure 15-2. IrDA Data Modulation (3/16) ...................................................................................................15-4 Figure 17-1. RZ1/NRZ Bit Encoding Example.............................................................................................17-9 Figure 17-2. 4PPM Modulation Encoding..................................................................................................17-14 Figure 17-3. 4PPM Modulation Example...................................................................................................17-15 Figure 17-4. IrDA (4.0 Mbps) Transmission Format ..................................................................................17-15 Figure 21-1. Architectural Overview of the I2S Controller ...........................................................................21-1 Figure 21-2. Bit Clock Generation Example ...........................................................................................21-10 Figure 21-3. Frame Format for Right Justified Data ..................................................................................21-10 Figure 23-1. Texas Instruments Synchronous Serial Frame Format (Single Transfer)...............................23-4 Figure 23-2. TI Synchronous Serial Frame Format (Continuous Transfer) .................................................23-4 Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0 ................................23-5 Figure 23-4. Motorola SPI Frame Format (Continuous Transfer) with SPO=0 and SPH=0 ..............................................................................................................................23-6 Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1 ............................................................23-7 Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ................................23-8 Figure 23-7. Motorola SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ..............................................................................................................................23-8 Figure 23-8. Motorola SPI Frame Format with SPO=1 and SPH=1 ............................................................23-9 Figure 23-9. Microwire Frame Format (Single Transfer) ...........................................................................23-10 Figure 23-10. Microwire Frame Format (Continuous Transfers) ...............................................................23-12 Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements ...........................23-12 Figure 24-1. PWM_INV Example ................................................................................................................24-6xvi

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Figure 25-1. Different Types of Touch Screens ..........................................................................................25-2 Figure 25-2. 8-Wire Resistive Interface Switching Diagram .......................................................................25-5 Figure 25-3. 4-Wire Analog Resistive Interface Switching Diagram............................................................25-6 Figure 25-4. Analog Resistive Touch Screen Scan Flow Chart ..................................................................25-9 Figure 25-5. 5-Wire Analog Resistive Interface Switching Diagram..........................................................25-11 Figure 25-6. 5-Wire Feedback (7-Wire) Analog Resistive Interface Switching Diagram ...........................25-12 Figure 25-7. Power Down Detect Press Switching Diagram .....................................................................25-13 Figure 25-8. Other Switching Diagrams ....................................................................................................25-14 Figure 25-9. Measure Resistance Switching Diagram ..............................................................................25-15 Figure 26-1. Key Array Block Diagram ...................................................................................................26-1

Figure 26-2. 8 x 8 Key Array Diagram ......................................................................................................26-3 Figure 26-3. Apparent Key 00H...................................................................................................................26-4 Figure 27-1. IDE Interface Signal Connections ...........................................................................................27-2 Figure 28-1. System Level GPIO Connectivity ............................................................................................28-2 Figure 28-2. Signal Connections Within the Standard GPIO Port Control Logic (Ports C, D, E, G, H) ...............................