ep manual master final 28-01-10 new1

8/2/2019 EP Manual Master Final 28-01-10 New1

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Laboratory Manual for

Electronic Communication

B. E.

SEM. V (EC)

Developed by

Rizwan Alad

Supported by

Vasim Vohra, Harekrushna Rathod, Shambhavi Bhatt, Tanmay BhattMitul Shah, Trushna Parikh, Dipak Rabari, Narendra Chauhan

Reviewed by

Dr. Nikhil Kothari

January 2010

Faculty of TechnologyDharmsinh Desai University


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Nadiad

Dear students,

This learning material consists of two parts. First part includes the contents related to thelaboratory activities, and the questions for conceptual understanding are covered in the secondpart.

The main objective of providing this learning material is to encourage self learning andadvance preparation. The lab manual describes the methodology of conducting theexperiment with theory background. All experiments in the manual have been conducted inlaboratory earlier as per the procedure mentioned here.

A few sample data sheets are attached in the appendix for realizing the importance ofspecifications of electronic components while performing the experiments. Sample question

papers would help you for better preparation for theory examinations.

Improvement is a continuous process. Hence, there is a scope of improvement in this manual.Your suggestions for improvement will be useful to us.

Nevertheless, we hope this first printed version of the learning material from Department ofElectronics & Communication will help you understand the subject better.

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad 2


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P A R T I

LAB MANUAL



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TABLE OF CONTENTS

Sr. No. Title Page No.

1. Single Tuned Amplifier . 05

2. Crystal Oscillator 08

3. Colpitt Oscillator.itch 10

4. Additive Mixer. 12

5. Amplitude Modulator. 15

17

6. Emitter Follower as a Buffer 19

7. Common Base Configuration of an Transistor Amplifier 22

8. Binary to Gray code and Gray to Binary Code Conversion 25

9. Half Adder and Full Adder using Basic Logic Gates 29

10. Half Subtractor and Full Subtractor using Basic Logic Gates

32

11. Multistage Amplifier using BJT

35

12. Study of AM

39



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LAB 1

Logic Gates

AIM: To Study Different Types of Logic Gates.

COMPONENTS: IC -7400 (Quad Two Input NAND Gate),IC -7408 (Quad Two Input AND Gate),IC -7432 (Quad Two Input OR Gate),IC -7402 (Quad Two Input NOR Gate),IC -7486 (Quad Two Input EX-OR Gate),IC -7404 (NOT Gate)

APPARATUS: DC Power Supply, Bread-board, Connecting Wires, Voltmeter.

THEORY:

Digital integrated circuits operate with binary signals often representing Boolean values. DigitalICs are normally consisting of number of logic gates which may be interconnected or availableseparately as individual logic gates. The Digital Integrated Circuits are available in differenttypes of packages e.g. Dual in line package, Flat package. Dual in line package are widely usedDigital IC Gates classified not only by the logic operation but by specific circuit families, e.g.TTL, CMOS etc. However, the experiments in this manual are based on TTL versions.

Boolean expressions can be implemented with the help of different types of logic gates found indigital ICs. This in turn also facilitates realization of binary arithmetic operations useful fordesigning and developing a digital computer system.

This experiment introduces a few logic gates capable of performing basic logic operations likeAND, NOR, NAND, OR using digital ICs.

AND GATE (IC 7408)

The AND gate performs logical multiplication, known as AND function. It has two inputs and oneoutput. It is known as two input AND gate.

Y = A1 * A2Pin Diagram Truth Table

Department of Electronics & Communication, Faculty of Technology, Dharmsinh Desai University, Nadiad

A1 A2 YA1 A2 Y

6


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OR GATE (IC 7432)

The OR Gate performs logical addition, known as OR Function. It has two inputs and oneoutput. It is known as two input OR gate.

Y = A1 + A2

Pin Diagram Truth Table

NOT GATE (IC 7404)

The NOT gate performs logical complement, known as NOT function with one input and oneoutput.

Y = (A1)


NAND GATE (IC 7400)

It is a combination of NOT and AND gates. A two input NAND gate has two inputs and oneoutput.

Y = (A1 * A2)



A1 A2 Y

0 0 0

0 1 1

1 0 1

1 1 1

A1 Y

0 1

1 0

A1 A2 Y

0 0 1

0 1 1

1 0 1

1 1 0

7


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NOR GATE (IC 7402)

It is a combination of NOT and OR gates. A two input NOR gate has two inputs and one output.

Y = (A1 + A2)


X-OR GATE (IC 7486)

When both the inputs of the gate are same, the output is low. Otherwise the output is high.

Y = A1* A2 + A2* A1


PROCEDURE:

1. Mount the IC on a bread-board.

2. Connect appropriate supply voltage as per the pin-out diagram.

3. Apply input signals on the pins of the IC as per the truth table given earlier.

4. Measure the output voltage and compare its binary equivalent with the truth table.

5. Repeat the above procedure for all the above logic gates.

CONCLUSION:

ASSIGNMENT QUESTIONS:


A1 A2 Y

A1 A2 Y

0 0 0

0 1 1

1 0 1

1 1 0

8


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1. What is a truth table?2. Write truth tables of Three input OR, AND, NAND, NOR GATES?3. Realize the logic expression Y= A (XOR) B (XOR) C (XOR) D with XOR gates?



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LAB 2

NAND and NOR as Universal Gates

AIM: To implement basic logic gates using NOR and NAND gates.

COMPONENTS: IC -7400 (Quad Two Input NAND Gate), IC -7402 (Quad Two Input NOR Gate)

APPARATUS: DC Power Supply, Bread-board, Connecting Wires, Voltmeter.

THEORY:

Digital circuits are frequently constructed with only NAND or NOR gates; because these gates are

easier to fabricate with electronic components. NAND and NOR gates are said to be universal

gates because any logic operation can be implemented using only one type of these gates.

This property of NAND and NOR gates is useful in reducing the package count in the design of a

digital system. Reduction in number of components makes the system more compact and reduces

the cost significantly.

NOR as a Universal gate

The conversion of NOT, AND and OR gate is as shown below.


Input OutputInput Output

1 0

0 1

A1 A2 Y

0 0 0

0 1 1

1 0 1

1 1 1

A1 A2 Y

A1 A2 YA1 A2 Y

0 0 0

0 1 0

1 0 0

1 1 1

10


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NAND as a Universal gate

The conversion of NOT, AND and OR gate is as shown below.

PROCEDURE:

1. Mount the ICs on bread-board as shown in the figure (either NAND or NOR).

2. Connect appropriate supply voltage as per the pin-out diagram.

3. Apply input signals on the pins of the IC as per the truth table and observe the outputof each gate on voltmeter.

4. Measure the output voltage and compare its binary equivalent with the truth table.

5. Perform the above procedure for both NAND and NOR gates.

CONCLUSION:

ASSIGNMNET QUESTIONS:


Input Output1 0

0 1

Input Output

A1 A2 YA1 A2 Y

A1 A2 YA1 A2 Y

11


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1. Explain the Term Universal Gate?2. What is the difference between Basic gates and Universal Gates?3. Construct XOR and XNOR gates using Universal Gates?



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LAB 3

Transistor as a Switch

AIM: To Study the switching characteristics of Bipolar Junction Transistor.

APPARATUS: Bread Board, DC Power Supply, Multimeter, Function Generator, CRO

COMPONENTS: Transistor BC 547/BC 548, Resistors 10 K and 1K.

THEORY:

Digital circuits are often called switching circuits because their Operating Point (Q Point)switches between two points on the load line. In most designs, the two points are saturation andcutoff. A transistor with base biasing can be operated in cut off or saturation region with highand low output voltage respectively. In the cut-off region, the transistor acts like an open switchwhile in saturation it acts like a closed switch.

A transistor can be operated in cut off if the base current is zero or if the base-emitter junction isreverse biased. As a result no voltage drop is observed across Rc and collector voltage equalsto Vcc. If IB increases to a very large value, the transistor conducts and the voltage drop acrossRc reaches a high value towards Vcc. Since current is maximum the transistor works like aclosed switch. It operates in the saturation region when both the base-emitter and collector-base

junction are forward biased.

To operate the transistor in saturation region it is necessary to select the value of RB is ten timesthe value of RC. This is called hard saturation.

Mathematically we can say that,

IC = IB (i)

VCE = VCC - ICRC (ii)

Thus, in cut-off region,

VBE 0 V, IB 0 ; Therefore, IC 0

Substituting this value in equation (ii)

Then VCE VCC

Similarly we can find out that,

In saturation region, VCE 0



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CIRCUIT DIAGRAM:

VCC = +5V;

VIN = 0 or 5V

R2 = 10 K

R1 = 1 K

Transistor = BC 547 (NPN)

PROCEDURE:

1. Connect the circuit using bread board as shown in the figure.2. Provide the circuit with the DC power supply of 5 V.3. Apply input voltage Vin 0 V (ground the input terminal).4. Measure the base current IB and output voltage Vout.5. Apply Vin 5 V.6. Measure the base current IB and output voltage Vout.7. Apply a square wave signal 5 V (pp) between base and emitter of transistor using a

Function Generator.8. Connect CRO between collector and emitter of transistor.9. Observe waveform on CRO.

OBSERVATION TABLE:

Vin (V) IB (mA) Vout (V)

CONCLUSION:


1. Why an ordinary junction transistor is called bipolar?2. In how many modes the BJT works? Also discuss the biasing pattern for each of them?3. Show the following regions in a transistor characteristics

(i) Active (ii) Saturation (iii) Cutoff



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LAB 4

Transistor as an Amplifier

AIM: To study the transistor as an amplifier.

APPARATUS: Bread Board, CRO, D.C. Power Supply, Function Generator

COMPONENTS: CRO Probes, Connecting Wires, Resistor, Capacitor, Transistor (BC 547)

THEORY:

One of the most important functions of electronic circuit is amplification. Almost all electronicsystems use amplifiers. An amplifier may be defined as a circuit that increases power of aninput signal by furnishing the additional power from a dc source.

Transistor is made up of two diodes connected back to back. At the input side, one of the diodesis forward biased, which has the lower resistance and the other diode is reverse biased, which

has higher resistance. Thus, lower resistance is converted into higher resistance.

When a signal is applied at the input terminal of a properly biased transistor, a base currentstarts flowing. Due to transistor action, much larger AC current ( times base current) flowsthrough output terminals. As described above, the resistance is higher at the output sideproducing a larger voltage drop. Therefore a large voltage appears across the output terminals.In this way a weak signal applied between inputs terminals appear in amplified form at theoutput terminals.

CIRCUIT DIAGRAM:



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PROCEDURE:

1. Connect the circuit as shown in figure using bread board.2. Apply Vcc = 10 V from DC power supply.3. Apply input AC signal (Vin) of 12mV at 1 KHz frequency from function generator.4. Check the output voltage (Vout) on CRO.

5. Calculate voltage gain and compare the results with theoretical gain.6. Also increase biasing voltage Vcc and measure Vout.7. Plot the graph of VCC versus voltage gain.

OBSERVATION:

For VCC = 10 V

Vin(peak) Vout(peak) Gain (Practical) Gain(Theoretical)

Gain Calculation:

Thevenin Resistance and Thevenin Voltage,

Emitter Current,

Emitter Dynamic Resistance,

Now output resistance,

So Voltage Gain,

Now if we consider input base resistance Zin (base),

So actual input voltage,



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Hence Vout = (Av)(Vin(actual)) = 1.13 Volt

Observation Table:

Vcc Biasing Voltage RTH Theveninss Resistance VTH Thevenins VoltageIE Emitter Current r e Emitter Dynamic Resistance RC Output ResistanceAv Theoretical Gain AV Observed Gain * transistor goes to saturation

Graph for VCC Vs. Gain

CONCLUSION:


1. Discuss the need of transistor biasing?2. What is a Dynamic Emitter Resistance? How it is differ from DC emitter resistance?3. What is a significant of small signal analysis in transistor amplifier?


Sr.

No.VCC(V) RTH (k) VTH (V) IE (mA) r e () RC (k) Av AV

17


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LAB 5

Effect of RC and RE on Voltage Gain of CE Amplifier

AIM: a) To study the effect of collector resistance (R C) and b) emitter resistance (RE) on the

voltage gain of a CE amplifier.


COMPONENTS: CRO Probes, Connecting Wires, Resistors, Capacitor, Transistors (BC 547)

THEORY:

CE amplifiers are used to amplify voltage level of low amplitude or weak signals. They are found

typically in sound amplifiers and wireless receivers.

Voltage gain of CE amplifier can be controlled either (a) by changing the collector resistance RC

or b) by changing the emitter resistance Re.

a) The voltage gain of CE amplifier is given as Av = - (RC/Zi). The voltage gain is directly

proportional to RC. As RC increases, voltage gain increases and as RC decreases voltage gain

also decreases.

With the change in the value of RC the slope of load line changes and accordingly the Q point

also changes. For a fixed Vcc and IB as RC increases the Q point moves upward (towards

saturation region) on load line and hence, possibility of the transistor operation entering into

saturation region increases. Therefore, effect of RC on the voltage gain of the amplifier can be

observed in the active region only. Outside the active region the output will be distorted.

However, care must be taken while determining the minimum value of RC. Increased collector

current due to reduced RC causes increase in the power dissipation of the transistor. If it

increases beyond the maximum specified value, the transistor may get damaged.

CIRCUIT DIAGRAM:



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PROCEDURE:

1. Make required connections on the bread board as shown in the circuit diagram.

2. Apply Vcc = 10 V from DC Power Supply and input AC signal of 8 mV at 1.38 KHz

frequency.

3. Vary the value of collector resistance RC and note down the corresponding output

voltage.

4. Note down the value of collector resistance at which distortion starts.

5. Plot the graph of V0 vs. RC.

OBSERVATION TABLE:

Vin(peak)

(mV)

RC

(K)

V0

(V)

Av = V0/ Vin

CONCLUSION:


1. What is the significance of emitter bypass capacitor in CE Amplifier circuit?2. Why CE configuration is most popular in amplifier circuits?



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b) Effect of Emitter Resistance on the Gain of CE Amplifier

THEORY:

Voltage drop across emitter resistance (RE) in a CE amplifier introduces negative feedback in

the base circuit, which will restrict the voltage gain of the amplifier. This negative feedback will

change because of change in the value of either IC or RE. Hence, a fixed value of RE in the

design of the amplifier attempts to control the voltage gain in case of unexpected change in Ic,

which may be due to the current gain or rise in temperature. It may be noted that Thus, the

main role of RE is to keep the Q point stable. This stability is achieved at the expense of voltage

gain.

In this experiment, we examine the effect of RE on a CE amplifiers voltage gain. The focus is on

controlling voltage gain by changing RE rather than Ic to change the negative feedback. Voltage

gain would be similarly affected due to change in Ic.

As discussed earlier, the voltage gain of CE amplifier is given as Av= - (R C/Ri) and Ri is given

as [hie + (1 + ) RE]. Since the value of hie is very small compared to (1+ )RE, the Av can beapproximated as RC/RE. Thus, voltage gain is inversely proportional to RE. As already

observed in the part a) this characteristic can also be examined in the active region only.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Make required connections on the bread board as shown in the circuit diagram.

2. Apply VCC = 10 V and i/p ac signal of 0.8 V at 1.38 KHz frequency.

3. Vary the value of collector resistance RE and note down the corresponding output

voltage.

4. Note down the value of emitter resistance at which distortion starts.



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5. Plot the graph of V0 vs. RE.

OBSERVATION TABLE:

Vin(peak)

(V)

RE

(K)

V0

(V)

Av = V0/ Vin

CONCLUSION:

ASSIGNMENT:

1. How can the gain be adjusted by help of increasing/decreasing Emitter Resistance?2. What is the frequency response of amplifier? Why it is required?



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LAB 6

Emitter Follower as a Buffer

AIM: To study the Common Collector transistor configuration as a buffer.


COMPONENTS: CRO Probes, Connecting Wires, Resistor, Capacitor, Transistor (BC 547)

THEORY:

A buffer is a circuit usually placed between to stages of a multistage amplifier or between theoutput of a voltage amplifier and the load. Its main role is to increase the driving capacity of theoutput signal due to low output impedance and reduce the loading effect with high inputimpedance.

In the Common Collector or Grounded Collector configuration, the collector is common and theinput signal is applied at the base, while the output is taken from the emitter terminal as shown

in figure. This type of configuration is commonly known as a Voltage Follower or EmitterFollower circuit. The Emitter Follower configuration is very useful for impedance matchingapplications because of the very high input impedance, in the region of hundreds of thousandsof ohms, and it has relatively low output impedance.

The common emitter configuration has a current gain equal to the value of the transistor itself.In the common collector configuration the load resistance is situated in series with the emitter soits current is equal to that of the emitter current. Then the current gain of the circuit is given as:

This type of bipolar transistor configuration is a non-inverting current amplifier with in phase V inand Vout. However, its voltage gain is always close to unity but less than 1. Therefore, it is usedas a buffer rather than a voltage amplifier.

In this experiment, this configuration of transistor is studied by changing input signal andmeasuring the corresponding outputs. This will in turn, demonstrate the voltage gain, which willbe observed to be unity for all combinations of the input and output voltages.



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CIRCUIT DIAGRAM:

PROCEDURE:

1. Make required connections on the bread board.2. Apply Vcc = 12 V and input AC signal of 20mV at 1 KHz frequency.3. Check the output voltage on CRO and measure the gain.4. Repeat the experiment with different input signals.5. Compare calculated and practical gain.

6. Increase Vcc and measure the o/p voltage.

OBSERVATION TABLE:

VCC = 12 V

Vin

(peak)

Vout

(peak)

Gain

(Observed)

Gain

(Calculated)



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Vin = 1 V (pp), 1 KHz frequency

VCC Vout

(peak)

Gain

(Observed)

Gain

(Calculated)

Theoretical Gain Calculation:

Thevenin Resistance and Thevenin Voltage,

Emitter Current,


So Voltage Gain,

CONCLUSION:


1. Define alpha () and beta () of a transistor? How these are related to each other?2. A transistor has =0.98. If emitter current of the transistor is 1mA .Determine the base

current and gain factor ?3. What are the main purposes for CC Amplifier in electronics circuits?



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LAB 7

Common Base Transistor Configuration as an Amplifier

AIM: To study the Common Base Transistor Configuration as an amplifier.


COMPONENTS: CRO Probes, Connecting Wires, Resistor, Capacitor, Transistor

THEORY:

The Common Base circuit is generally used in single stage amplifier circuits such asmicrophone pre-amplifier or RF radio amplifiers due to its very good high frequency response.

The common-base terminology is derived from the fact that the base is common to both theinput and output side of the configuration. In addition, the base is usually at ground potential.

The input signal is applied between the emitter and ground terminals. The corresponding outputsignal is taken between the collector and ground terminals as shown in figure.

The input current flowing into the emitter is quite large as it is the sum of both the base currentand collector current. Therefore, the output collector current is less than the input emitter currentresulting in a current gain for this type of circuit of less than, but close to unity.

This type of amplifier configuration is a non-inverting voltage amplifier circuit. Signal voltages V inand Vout are in-phase. This type of configuration has low input impedance and high outputimpedance with a high voltage gain. However, the voltage gain of this configuration will be lowerthan that of the CE configuration. We observe the voltage gain for different values of thecollector resistance RC.

CIRCUIT DIAGRAM:

The Common Base Configuration,

R1= 10 k; R2= 2.2 kRC= 6.6 k; 10 kC= 1FVCC =10 VoltsTransistor- BC 547 (NPN)



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PROCEDURE:

1. Make required connections as per circuit diagram on the bread board.2. Apply Vcc = 10 Vdc and i/p ac signal at 1 kHz frequency.3. Check the output voltage on CRO and calculate the gain.4. Vary the value of RC and measure the output voltage and calculate gain.

Gain Calculation:

Base voltage,

Emitter current,

Internal ac emitter resistance,

Voltage gain,



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OBSERVATION TABLE:

RC Vin(pp) Vout (pp) Gain

CONCLUSION:


1. What is Early Effect? Explain how it affects the BJT characteristics in CB configuration?

2. What are the various properties of Common Base Transistor Amplifier?



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LAB 8

Gray Code Conversion

AIM: To Implement and verify Gray to Binary & Binary to Gray Code converters.

APPARATUS: IC 7486, Bread Board, Power Supply, Connecting Wires, Multi Meter.

THEORY:

Binary information consisting of 0 and 1 is normally encoded during information transfer fromone device to another. Binary pattern varies in different types of binary codes depending ontheir applications. The most popular ASCII code has been used in printers and text editors. Graycodes are useful in the design of digital circuits.

The availability of a large variety of codes for the same discrete elements of Information, results

in the use of different codes by the different digital systems. Therefore, it is sometimesnecessary to convert one code in to the other.

To convert binary code B to gray code G, the input lines must supply the bit combination ofelements as specified by code B and the output lines must generate the corresponding bitcombinations of code G. A combinational circuit performs this transformation by means of EX-OR gates. The input combinations for the binary code contain four variables which gives sixteencombinations. The truth table for the binary to gray code converter is as shown below. Where

a) Binary to Gray Code Converter

Circuit Diagram



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Truth Table

Binary Code Input Gray Code Output

b[3] b[2] b[1] b[0] g[3] g[2] g[1] g[0]

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

b) Gray to Binary Code Converter

Circuit Diagram



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Truth Table

Gray Code Input Binary Code Output

g[3] g[2] g[1] G[0] b[3] b[2] b[1] b[0]0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

1 0 0 0 1 1 1 1

1 0 0 1 1 1 1 0

1 0 1 0 1 1 0 01 0 1 1 1 1 0 1

1 1 0 0 1 0 0 1

1 1 0 1 1 0 1 0

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0

PROCEDURE:

1. Implement the diagram as per the circuit.2. Provide the power supply VCC equal to 5.0 V.3. Apply the input as shown in the table and measure the output voltage.

OBSERVATION TABLE:

Binary Code Input Gray Code Output

b[3] b[2] b[1] b[0] g[3] g[2] g[1] g[0]

0 0 0 0

0 0 0 1

0 0 1 0



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0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Gray Code Input Binary Code Output

g[3] g[2] g[1] g[0] b[3] b[2] b[1] b[0]

0 0 0 0

0 0 0 1

0 0 1 00 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 01 1 1 1

CONCLUSION:


1. What is Gray code?2. Derive Boolean equation of g[3], g[2], g[1] and g[0] using Boolean algebra.3. How do you convert Gray code numbers to corresponding Binary numbers using a

converter?



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LAB 9

Half Adder and Full Adder

AIM: To implement the Half ADDER and Full ADDER circuit using logic gates.

COMPONENTS: IC -7408 (Quad Two Input AND Gate)IC -7432 (Quad Two Input OR Gate),IC -7486 (Quad Two Input XOR Gate),

APPARATUS: DC Power Supply, Bread-board, Connecting Wires.

THEORY:

Digital circuits are the basic building blocks of digital computer systems. A binary adderdesigned using logic gates can be useful for performing arithmetic operations in a digitalcomputer.

In this experiment, two versions of adder circuits are introduced. A simple half adder isconsidered in the first phase. It generates sum and carry as a result of 1-bit addition. However,a half adder will not be able to produce a correct result for addition of more then 1 bit as it doesnot take into account the carry generated by the previous stage.

A full adder circuit eliminates the limitations of half adder. While performing addition of the bitsappearing at its input it also considers the carry generated from the addition of previous stage.

As a result an adder of any size can constructed using required number of full adder stages.Obviously, full adders are found in practical adder circuits.

a) Half Adder

Fig. 1 Half Adder



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Truth table

A B SUM CARRY

0 0 0 0

0 1 1 01 0 1 0

1 1 0 1

b) Full Adder

Fig. 2 Full Adder

Truth table

Inputs Outputs

A B Cin SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 11 1 1 1 1



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PROCEDURE:

1. Connect the circuit as shown in Fig 1.2. For Different values of A and B as shown in the truth table, note down the SUM and

CARRY outputs.3. Connect the circuit as shown in Fig.2

4. Repeat the step 2.

OBSERVATION TABLE:

Half Adder

Inputs Outputs

A B SUM CARRY

0 0

0 1

1 01 1

Full Adder

Inputs Outputs

A B Cin SUM CARRY

0 0 0

0 0 1

0 1 0

0 1 11 0 0

1 0 1

1 1 0

1 1 1

CONCLUSION:


1. What is difference between Half Adder and Full Adder?2. Design a full adder using NAND gates.3. Design a half adder using NOR Gates.

LAB 10

Half Subtractor and Full Subtractor



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AIM: To implement the Half Subtractor and Full Subtractor circuit using logic gates.COMPONENTS: IC -7404 (NOT Gate)

IC -7408 (Quad Two Input AND Gate),IC -7432 (Quad Two Input OR Gate),

IC -7486 (Quad Two Input EXOR Gate),

APPARATUS: DC Power Supply, Bread-board, Connecting Wires.

THEORY:

Conventionally a digital computer performs subtraction on binary numbers with the help of 2scomplement. However, subtraction can be done by even by using 1s complement. The sameconcept is demonstrated in this experiment using simple circuits that perform subtraction onsingle bit inputs.

Half Subtractor and Full Subtractor both produce difference and borrow outputs. As observed

earlier in case of Half Adder, a Half Subtractor does not consider the borrow produced by theprevious stage of 1 bit subtractor. Hence, it is not suitable for carrying out subtraction of binarynumbers consisting of multiple bits.

Since a Full Subtractor produces difference and borrow based on the inputs as well as theborrow from the previous stage, it can be used in binary subtraction of number with more than 1bit width.

Half Subtractor:

Fig. 1 Half Subtractor

Truth table



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Inputs Outputs

A B DIFFERENCE BORROW

0 0 0 0

1 0 1 0

0 1 1 1

1 1 0 0

Full Subtractor:

Fig. 2 Full Subtractor

Truth table

Inputs Outputs

A B BORIN DIFFERENCE BOROUT

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 01 1 0 0 0

1 1 1 1 1

PROCEDURE:

1. Connect the circuit as shown in Fig 1.



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2. For Different values of A and B as shown in the truth Table, Note down the SUM andCARRY outputs.

3. Connect the circuit as shown in Fig.24. Repeat the step 2.

OBSERVATION TABLE:

Inputs Outputs

A B DIFFERENCE BORROW

0 0

1 0

0 1

1 1

Inputs OutputsA B BORIN DIFFERENCE BOROUT

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

CONCLUSION:


1. What is the difference between Full Adder and Full Subtractor? Also give the differencebetween Half Adder and Half Subtractor?

2. Show how a Full adder can be converted to Full Subtractor with the addition of aninverter circuit.

3. Design a Half Subtractor using NAND Gates.

LAB 11

Multistage Amplifier



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AIM: To study the multistage Common Emitter amplifier.


COMPONENTS: CRO, Probes, Connecting Wires, Resistor, Capacitor, Transistor (BC 547)

THEORY:

The performance obtained from a single stage amplifieris usually insufficient. Designing a high

power single stage amplifier involves several issues like Q point instability, high current and

limited gain. Hence several stages may be combined together in cascade forming a multistage

amplifier thereby increasing the voltage gain. In such a multistage amplifier, output of the first

stage is connected to the input of the second stage, whose output becomes input of third stage,

and so on.

In this experiment, the amplified and inverted signal out of the first stage is coupled to the base

of the second stage. The amplified and again inverted output of the second stage is then

coupled to the load resistance. Here we have taken two stages of CE amplifier into

consideration. So the signal across the load resistance is in phase with the input signal as each

stage inverts the signal by 180o. Therefore, two stages invert the signal by 360o, equivalent to

0o. Thus, even number of stages of a multistage amplifier give in-phase signals and odd number

of stages give signals out of phase.

Total voltage gain of the amplifier is given by the product of individual gains [A V = AV1* AV2] .The

input impedance of the second stage is the load resistance on the first stage.

Thus, a multistage amplifier gives a large voltage gain, which is required to be stabilized. One

way to stabilize the voltage gain is to leave some of the emitter resistance unbypassed,

producing negative ac emitter feedback. When ac emitter current flows through the unbypassed

emitter resistance re, an ac voltage appears across re. This produces negative feedback. The ac

voltage across re opposes change in voltage gain.

Circuit Diagram

http://en.wikipedia.org/wiki/Amplifierhttp://en.wikipedia.org/wiki/Amplifier


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V1 = V2 = VCC = 12 V

Vin = 20 mV (pp), 1 KHz.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Apply supply voltage VCC = 12 V.

3. Connect an ac signal of 20mV peak-peak at the input of the amplifier with 1 KHz

frequency.

4. Check the output voltage on CRO at each stage independently without cascading andcalculate the gain at each stage.

5. Combine the two stages in cascade. Check the output voltage and compute the gain atthe first stage of amplifier.

6. Also check the final output voltage on CRO, which is the output voltage at the secondstage of the amplifier and calculate the gain at this stage.

7. Obtain the total voltage gain of the amplifier given by the product of individual gains. [AV

= AV1* AV2]

8. Compare the theoretically and practically obtained valued of gain with and withoutcascading.

OBSERVATION TABLE:



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a) Multistage amplifier without cascading

VIN (peak) Vstage1= Vstage2(peak) Gain (Practical)[ AV1= AV2] Gain (Theory) [AV1=AV2]

b) Multistage amplifier with cascading

Vin

(peak)

Vstage1

(peak)

Vstage2

(peak)

Gain(Practical) Gain(Theory)

AV1 AV2 AV AV1 AV2 AV

CALCULATION:

Theoretical Gain Calculation

Stage 1:

Thevenin Voltage,

Emitter Current,


So Voltage Gain,

Av1=RC|| ZIN(stage2)/ re+ re = 1.05

Stage 2:



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So finally total voltage gain, AV = AV1 X AV2 = 112.35

CONCLUSION:


1. Define and explain the following terms:

(i) Gain (ii) Frequency Response (iii) Bandwidth

2. What are the different types of coupling schemes used in Multistage Amplifiers?

3. What is a multistage amplifier circuit? Why it is required?

LAB 12



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Amplitude Modulation

AIM: To study the characteristics of amplitude modulation and generate AM signal.

APPARATUS: CRO, Two RF Function Generators, CRO Probes

THEORY:

Modulation is one of methods for preparing information to be sent from one location to another.

Modulation is required for the following reason.

1. To transmit the signals over longer distance.

2. To reduces antenna size.

In modulation, two signals are used, carrier signal and information signal or modulating signal.

Frequency of carrier signal (fc) is always higher than the frequency of information signal (fm).

Carrier wave is varied in accordance with the modulating wave (signal). The resultant wave is

called modulated wave.

We have basically three types of Analog (Continuous Wave) Modulation schemes; Amplitude

Modulation (AM), Frequency Modulation (FM), and Phase Modulation (PM). Here we are

concerned with AM.

In amplitude modulation, amplitude of the carrier signal is proportional to the modulating signal.

Its figure of merit is indicated by Modulation Index (m).

In case of m > 1 known as over modulation, information in transmitted signal suffers from partial

loss. It will be a case of critical modulation when m = 1. Atmospheric effects can lead critical

modulation to over modulation causing loss of information. Therefore, for better transmission m

should be less than one. It is called under modulation.

Equation of AM wave,

ECmax Amplitude of carrier wave



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fm Frequency of modulating wave signal

fC Frequency of carrier wave signal

m Modulation index, for better transmission m should be less than 1

e (t) Transmitted modulated signal

(fC fm) Lower sideband frequency

(fC + fm) Upper sideband frequency

Frequency spectrum can be determined base on the value of upper side band and lower side

band frequency. This can in turn be useful for finding the bandwidth of modulated signal. It

should match with the bandwidth specification of transmission media.

AM Waveform

Under Modulation m < 1,

0 0.5 1 1.5 2 2.5 3-6

-4

-2

0

2

4

6

AMWaveform

time

Amplitude

Over Modulation m > 1,

0 0.5 1 1.5 2 2.5 3-15

-10

-5

0

5

10

15

AMWaveform

time

Amplitude



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Critical Modulation m = 1,

0 0.5 1 1.5 2 2.5 3-10

-8

-6

-4

-2

0

2

4

6

8

10

AMWaveform

time

Amplitude

PROCEDURE:

1. Take the two function generators FG1 and FG2 for modulating signal and modulated

signal respectively.

2. Select the AM mode of function generator in FG2 and observe modulated output.

3. Change amplitude and frequency of modulating signal from FG1 and measure Emax and

Emin.

4. Find modulation index from given formula.

5. Calculate bandwidth of transmitted modulated signal for different modulating frequency.

CALCULATION:

CONCLUSION:


1. What are the frequency components in an amplitude modulated wave?2. The maximum and minimum amplitudes of a sinusoidal modulated wave are 800 mV

and 200 mV. Determine the Percentage Modulation?3. Draw the amplitude modulated wave for information signal is voice signal. Also calculate

its BW.



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P A R T I I

TUTORIALS



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TABLE OF CONTENTS


1. Transistor Fundamentals 44

2. Number Systems & Digital Systems 48

3. Transistor Biasing 50

4. Binary Codes and Logic Gates 55

5. Transistor AC Models 57

6. Boolean Algebra and Combinational Circuit Design 59

7. Voltage Amplifiers using BJT 60

8. CC and CB Amplifiers 62

9. Power Amplifier 65

10. Signal and Systems 69

11. Linear System Analysis70

12. Amplitude Modulation 71



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Tutorial 1

Transistor Fundamentals

Q 1) Do as directed:

1. Draw the energy band gap diagram for biased and unbiased transistor.

2. Justify. The emitter is heavily doped in transistor fabrication.

3. What is one important thing transistor do?

4. If the base resistor is open, what is the collector current?

5. Justify in detail. The emitter junction is always forward biased while the collector junctionis always reverse biased, to operate transistor in active region.

6. What are the factors affecting the current gain?

7. State true or false with reason. The base is thin and heavily doped in transistor

fabrication.

8. State true or false.A transistor acts like a diode and a voltage source.

9. With reference to the output characteristics of CE configuration, for higher value of VCE,

IC is almost independent of VCE. Justify the statement.

10. State three requirements that a biasing network associated with a transistor should fulfill.

11. Draw and explain the input and output characteristics of a transistor in CE configuration.

Indicate cut-off, saturation and active regions.

12. Classify the amplifier on the basis of the position of the operating point on the output

characteristics. Support your answer with proper diagram(s).



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Q 2) Solve the following:

1. What is the value of IC for IE = 5.34 mA & IB = 475 A?

2. What is the DC when IC = 8.23 mA & IE = 8.69 mA?

3. A certain transistor has an IC = 25 mA & IB = 200 A. Determine the DC.

4. Given that DC = 0.987, determine the corresponding value of DC.

5. Given DC = 120, determine the corresponding value of DC.

6. A base current of 50 A is applied to the transistor & a voltage of 5V dropped across RC

= 1 K. Determine DC of transistor.

7. A certain transistor is to be operated with VCE = 6 V, if its maximum power rating is 250

mw, what is the most collector current that it can handle?

8. A transistor has a PD(max) = 5V at 25oC. The derating factor is 10 mw/oC. What is the

PD(max) at 70oC.

9. A 2N3904 has power rating 625 mW; Ic= 20 mA and Vce= 10 V. How safe if the ambient

temperature is 900C?

10.A 2N222 transistor has value of=0.99 and the emitter current flowing through it is

around 10mA, then determine the base current, collector current and .

11.If the base current in a transistor is 20 A when the emitter current is 6.4 mA, what are

the values of dc and dc? Also calculate the collector current.

12.In a certain transistor, 99.5% of the carriers injected into the base cross the collector-

base junction. If the leakage current is 6 A and the collector current is 10 mA, calculate

the value of dc and the emitter current.



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13.Design the transistor used as a switch with following output specifications: Either output

voltage should be 0 V or 10V.

14.Determine the following for the fixed bias configuration of Fig.1.

a) IBQ and ICQ b) VCEQ c) VB d)VC e) VE

Fig. 1

15.Determine the value of Q-point for Fig. 2. Also find the new value of Q-point if change

to 150.

Fig. 2



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16.Given the load line of Fig. 3 and defined Q-point, determine the required values of VCE,

RC and RB for a fixed bias configuration.

Fig. 3



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Tutorial 2

Digital Systems and Number systems

Q 1) Answer the following with necessary justification:

1. State the advantages of Digital systems over Analog systems.

2. Define Positive logic system and Negative logic system.

3. What are the two voltage levels normally used to represent binary digits 0 and 1?

4. The base or radix of the octal number system is ___________.

5. Enlist the characteristics of 1s and 2s complement system.


1. Convert the following number into 9s complement and 10s complement.

a) 3465 b) 782.54 c) 4526.075

2. Subtract using 9s complement and 10s complement method.

a) 274-86 b) 574.6 279.7 c) 376.3 765.6

3. Convert the following binary numbers to decimal.

a) 1011 b) 1101101 c) 1101.11

4. Convert the following decimal number to binary.

a) 128 b) 105.15 c) 197.56

5. Add the following binary numbers.

a) 11011 + 1101 b) 10111.101 + 110111.01

6. Subtract the following binary numbers.

a) 1011-101 b)1100.10 111.01 c) 10001.01 1111.11

7. Find the 2s complement and 1s complement form of the following decimal numbers.

a) -173 b) 65.5



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8. Subtract using 2s complement method: 125.3-46.7

9. Convert the numbers.

a) 2568 into binary, hexadecimal and decimal

b) 4F7.A816 into octal, binary

c) 1101112 into octal, hexadecimal and decimal

d) BC70.0E16 into decimal, binary and octal



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Tutorial 3

Transistor Biasing

Answer the following with necessary justification:

1. Find the value of base current and current gain in Fig. 1, if IC =5mA, VBB=10 V,

= 200, RB=330 K, RC=820, and VCC=10V.

Fig. 1

2. Differentiate Stiff and Firm voltage divider. And find whether the circuit shown in Fig. 2

is stiff or Firm? If R1=10 K, R2=2.2 K, RC=3.6 K, RE=1 K, = 200 and VCC=10 V.

Fig. 2



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3. Design a VDB circuit shown in Fig. 2 to meet the following specifications.

(a) VCC=10 V (b) VCE @ midpoint (c) Stiff voltage divider (d) IC=1mA (e)dc=70

4. Design a VDB circuit shown in Fig. 2 to meet the following specifications.

(a) VCC=10 V (b) VCE @ midpoint (c) Firm voltage divider (d) IC=10 mA

(e)dc=100

5. The operating point in the circuit shown in Fig. 2 is fixed such that IC=2 mA, VCE=4V. If

RC=2k, VCC=10V and =50, Determine the values of R1, R2 and RE. Assume I1=10 IB.

6. Fig. 3 Shows the circuit of fixed biased circuit with = 100.Determine the value of bias

resistor RB and value of the voltage between the collector and ground if VBE=0, RC=300

and VCC=12 V.

Fig. 3

7. Fig. 4 shows the circuit of collector to base bias using N-P-N transistor. Assuming

VBE=0.7, RB=200 K, = 100, RC=20 K, and VCC=20 V. Calculate the collector current IC

and the collector to emitter voltage VCE.



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Fig. 4

8. Calculate the collector current and the collector to emitter voltage of the circuit shown in

Fig. 5.If R1=40 K, R2= 4 K, RC=10 K, RE=1.5 K VBE=0.5 V, VCC=22 V and = 40.

Fig. 5

9. In a single stage CE Amplifier VCC=20 V, R1=60 K, R2=30 K, RE=200 and = 50.Refer Fig. 5.

10.Find the value of VCC, RB and of the circuit shown in Fig. 6.If current through RB is

20 A.



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Fig. 6

11.A P-N-P silicon transistor is used in a common collector circuit shown in Fig. 7, Find

Quiescent point.

Fig. 7

12.For the voltage-divider bias amplifier shown in the Fig. 8, what is the ac and dc load

line? Determine the maximum output compliance.



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Fig. 8



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Tutorial 4

Binary Codes and Logic Gates

Q 1) Answer the following with necessary justification:

1. What is the difference between a weighted code and a non-weighted code?

2. State the importance of Gray code.

3. Give the difference between an error detecting and an error correcting code.

4. What is the maximum number of the outputs of any logic gate?

5. NAND and NOR gate are known as universal gates. Justify the statement.


1. Express the decimal numbers into 8421 BCD code:

a) 296 b) 37.52 c) 821

2. Express the 8421 BCD numbers as decimals:

a) 1000 0011 1001 b) 0110 1001 0111.1011

3. Express the decimal numbers into XS-3 code:

a) 19 b) 251 c) 78.2

4. Express XS-3 code as a decimal:

a) 1100 1000 b)1001 1101. 0111

5. Convert the decimal number to Gray code:

a) 6 b) 20

6. Convert Binary to Gray Code.:

a) 1010 b) 1110111

7. Which of the following words contain an error for odd parity?

a) 1011 b) 11010101 c) 110101 d) 10010101



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8. Draw the truth table for 2-input Ex-NOR gate.

9. Draw the OR gate using two transistor logic and also mentions the truth table for the

same.

10. Specify the truth table for 3-input NAND gate.



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Tutorial 5

Transistor AC Models


1. In a CE amplifier, the capacitor produces an ac ground is called a _______ capacitor.

2. If vbe = 10 mV and ie = 75 A pp, find ac emitter resistance of the emitter diode.

3. Why coupling capacitors and bypass capacitor are used in an amplifier? How the

amplifier will be affected, if coupling capacitors and bypass capacitor are not used in an

amplifier.

4. What is non linear distortion? How it can be reduce?

5. Input voltage and output voltage of a CE amplifier are in phase. State true/false. Justify.

Q 2) Answer the following:

1. Draw a dc equivalent and an ac equivalent circuit for a CE amplifier shown in Fig. 1.



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Fig. 1

2. Find out voltage gain and output voltage for an amplifier shown in Fig. 1.

3. For an amplifier shown in Fig. 2 find out output voltage and also draw its ac equivalent

circuit using T and model. Consider =200.



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Fig. 2

4. For an amplifier shown in Fig. 2, draw waveforms at points A, B, C, D, and E with their

voltage levels.



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Tutorial 6

Boolean algebra and Combinational Circuit Design

Answer the following with necessary justification:

1. What are the axioms of the Boolean algebra?

2. State the distributive law of Boolean algebra.

3. State and Prove De Morgans theorem.

4. What do you mean by Duality in Boolean expressions?

5. State the dual expression for the following Boolean expressions.a) A(A+B) = A b) ((AB) + A + AB) = 0

6. Reduce the following Boolean expressions.

a) A[ B + C (AB+AC)]

b) A+B[AC+(B+C)D]

7. Show that AB+ABC+BC = AC+ BC.

8. Prove that ABCD + AB(CD) + (AB)CD = AB + CD.

9. Prove that (A+A) (AB+ABC) =AB.

10. Design Full adder using two Half-adder circuits.

11. Design 4-bit Gray to Binary code conversion.

12. Design 3-bit even parity checker circuit.



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Tutorial 7

Voltage Amplifiers using BJT

Q 1) Answer the following with necessary justifications:

1. State true or false with reasons. The distortion of an amplified signal can be reduced by

reducing emitter resistance.

2. What is swamped amplifier?

3. State true or false with reason. The emitter of a swamped amplifier has an ac voltage.

4. Draw the -model and T-model of a self bias common emitter amplifier.

5. The feedback resistor ______________.

(a) Decreases voltage gain (b) increases input resistance (c) reduces distortion (d)

all of these.

6. State true or false with reason. If the input resistance of the second stage decreases the

voltage gain of the first stage increases.

Q 2) Solve the following:

1. For the amplifier shown in Fig. 1, find out output voltage across R6.

Fig. 1



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2. Draw T-model for the amplifier given in Fig. 2 and find out output voltage.

Fig. 2

3. For the two stage amplifier shown in Fig. 3, draw -model and find out output voltage.

Fig. 3



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Tutorial 8

CC and CB Amplifiers


1. Draw the diagram of emitter follower and describe its advantages.

2. State the advantages of Darlington transistor.

3. Describe the purpose of cascading CE & CC amplifier.

4. Compare the characteristics of CE, CC, CB amplifiers.

5. Draw the schematic for zener follower and discuss how it increases the load current out

of zener regulator.

6. The output voltage of an emitter follower is

a) 0, b) Vg, c) Vin d) Vcc?

7. The input impedance of the base of an emitter follower is usually

a)Low b) High c) Shorted to ground d) open.

8. If a CE stage is directly coupled to an emitter follower

a) low and high frequencies will be passed b) only high frequencies will be passed

c) high-frequency signals will be passed d) low-frequency signals will be passed?

Q 2) Solve the given example:

1. Find out the input impedance of base in Fig.1 if = 200, what is the input impedance

of stage? VCC=+10V, Vg=1V, Rg=500, R1=10k , R2=10k , RE=4.5k , RL=10k.



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Fig. 12. Find out voltage gain of Fig.1 if =150, what is the ac load voltage? VCC=+30V,

Vg=1Vpp, Rg=600, R1=10k , R2=4.7k , RE=200, RL=200.

3. Calculate output impedance in Fig.1, VCC=+15V,Vg=1V (pp), Rg=600, R1 = 4.7 K,

R2 = 10 K,RE = 2 K, RL = 6.8 K.

4. In Fig. 2 each transistor has value of 150, what is overall current gain base current

of Q1 and input impedance at base of Q1? VCC=+15V, Rg = 600 , R1=10 K, R2 = 20

K, RE = 80 , RL = 40 .

Fig. 2

5. Find out output voltage in Fig.3, VCC = +15V, Vin =2 mV(pp), Rg=60 ,

RE = 2.2 K, R1=10 K, R2 = 2.2 K, RL=10 K, RC=3.6 K,C1=47F,C2=47F, C3=1

F.

Fig. 3



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6. Find out output voltage in Fig. 4, Vin = 30V, R1 = 680, R2 = 2.2 K, R3 = 2 K, R4 =

1 K, RL = 100 , Vz = 6.2V.

Fig. 4



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Tutorial 9

Power Amplifier


1. Fill in the blank. For class B operation, the collector current flows for ..

(a) The whole cycle (b) half the cycle (c) less than half the cycle (d) less than the quarter

of the cycle.

2. Fill in the blank. An audio amplifier operates in the frequency range of .

(a) 0 to 20 Hz (b) 20 Hz to 2 kHz (c) 20 Hz to 20 kHz (d) above 20 kHz.

3. Fill in the blank. When transistor is cut off .

(a) Maximum voltage appears across transistor (b) maximum current flows (c) maximum

voltage appears across the load (d) none of above.

4. Define: Distortion and collector efficiency.

5. Differentiate: Voltage and Power amplifiers.

6. Transformer coupling is generally employed in power amplifiers. Justify the statement.

7. An amplifier has only one load line. State true/false with reason.

8. For maximum peak to peak output voltage, the Q point should be at the centre of

the ac load line. State true/false with reason.


1. If the peak to peak output voltage is 12 V and the input impedance of the base is 100ohm, what is the power gain in Fig. 1?



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Fig. 1

2. What is the transistor power dissipation and efficiency of Fig. 1?

3. What are the values of Icq, VCEq and re in Fig. 2? Repeat the same example for R1 =75 .

Fig. 2



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4. Determine the saturation and cutoff points in Fig. 2.

5. What is the maximum peak to peak output in Fig. 3?

Fig. 3

6. Calculate the (a) output power (b) input power and (c) collector efficiency of the

amplifier circuit shown in Fig. 4. It is given that input voltage results in a base current of

10 mA peak.

Fig. 4



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7. A class A transformer coupled power amplifier has zero signal collector current of

50 mA. If the collector supply voltage is 5 V, find (a) the maximum ac power output (b)

the power rating of transformer and (c) the maximum collector efficiency.

8. A common emitter class A transistor power amplifier uses a transistor with

=100. The load has a resistance of 81.6 ohm, which is transformer coupled to the

collector circuit. If the peak values of collector voltage and current are 30V and 35 mA

respectively and the corresponding minimum values are 5V and 1 mA respectively,

determine: (a) the approximate value of zero signal collector current (b) the zero signal

base current (c) Pdc and Pac (d) collector efficiency.



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Tutorial 10

Signal and System

Q 1) State True or False with justification:

1. RMS value of Main Voltage is considered as a Signal.

2. A Signal V = Vm* (-t/RC) carry Information.

3. The random signal always carries information.

4. A signal r2 = 2sin (5t), 0 t 2*pi is unpredictable signal.


1. A signal is given by V = 2sin100t + 3sin300t. What is the fundamental frequency in Hz?

2. Plot the Amplitude and Phase Spectrum of the following signal.

a) V = 5sin100t + 10cos200t + 5cos(300t + /3)

b) V = 8sin50t + 7sin(50t +/3) + 12cos(100t + 3 /2)

c) V = 2.5sin(1000t+75o)+4cos(1000t+95o)+5sin(1000t+65o)+cos(1500t+45o)

Consider X axis as a frequency in terms of Hz.

3. Give the definition of the signal. Also differentiate predictable and unpredictable signal.

4. Why we use sine wave for testing the circuit?

5. What are the required conditions for having two identical AC signal?

6. Briefly explain the block diagram of the wireless communication



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7. If two sine wave of 1 KHz and 2 V (pp) amplitude but second signal is 60 o out of phase

with respect to first signals than draw the signal in time domain and frequency domain.

8. What are the importances of frequency domain signal description?

Tutorial 11

Linear System Analysis

Q 1) State True or False with justification:

1. Half wave symmetry indicates odd harmonics property of signal.

2. If in BJT amplifier Vcc=12 V, gain of amplifier is 100 and input signal is pure sine wave at

1V (pp), 1 KHz than output signal is pure sine wave 100V (pp), 1 KHz.

3. The negative feedback reduces harmonic distortion in system.

4. For negative feedback loop gain of system more than one.


1. What is the method for checking half wave symmetry of signal?

2. What is the advantage of DC biasing in amplifier circuit?

3. What is the meaning of saturation? When the amplifier operates in saturation region?

4. What are the two condition for avoid distortion in piece wise linear system? Justify these

conditions.

5. What is the meaning of small signal analysis?

6. What are the advantage and disadvantage of negative feedback?

7. A non-linear device has the transfer characteristic given by V0=2Vi+0.5Vi2. If

Vi=1+0.5sinwt, find out the expression for the output assuming small signal operation.



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8. The transfer characteristic of a device is given by V0=2Vi+0.5Vi2+0.3Vi3. If Vi=2+sinwt,

obtain the expression for the output and total harmonic distortion.



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Tutorial 12

Amplitude Modulation

Q 1) Answer the following questions with necessary justifications:

1. Why modulation is must in wireless communication?

2. What are the difference between amplitude modulation and frequency modulation?

3. In modulation, frequency of carrier signal must be very high compare to maximum

modulating frequency. Justify.

4. In amplitude modulation, modulation index should be less than one. Justify.

5. Bandwidth occupied by signal in SSB modulation is less than AM. Justify.

6. Explain concept of Frequency Division Multiplexing (FDM).

7. Find number of signal in one channel if channel BW is 10 MHz and one audio signal BW

without modulation is 4 KHz, consider AM.

8. What is the basic difference between Amplitude Modulator circuit and Frequency Mixer

circuit?


1. A modulating signal is human voice signal than sketch the modulated signal assuming

Vc = 2Vm.

2. A modulating signal is given by Vm=2sin (100t) +4sin (500t), if Vc=10sin (50000t) than

find the expression for the modulated signal and sketch the magnitude spectrum for

modulating and modulated signal.

3. A modulating signal is given by Vm=2sin (100t) +4sin (2000t) +5sin (200t) +6sin (5000t)

+7sin (700t). What is the bandwidth occupied by modulated signal in AM and SSB.

4. A modulated signal is given by V0= (Vc+Vm (t)) sin (108t). Find out the size of the /4

antenna required.



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5. A modulated signal is given by V0= (6+2f (t)) sin (Wct). What is the percentage

modulation index required?

6. A modulated signal is given by V0= (5+8f (t)) sin (Wct). Can the signal be detected by

peak detector? Explain briefly.

7. Derive the equation for RC time constant in peak detector circuit.

8. Draw the block diagrams of super heterodyne receiver explain in brief and give its

advantage with respect to straight through receiver.

9. Draw the block diagram of frequency mixer with all specifications, if RF signal frequency

4MHz and require output frequency 455 KHz.



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P A R T III

APPENDIX



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TABLE OF CONTENTS


1. Appendix A Transistor Configuration 75

2. Appendix B Datasheet of BJT BC 547 77

3. Appendix C Datasheet of Digital IC 7400 84

4. Appendix D Question Paper 86



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Appendix A

Transistor Configuration

Transistor Fabrication

Parameter Emitte

r

Base Collector

Relative Physical

Area

100 10 1000

Relative Doping

Implant

100 1 5

Doping Density

(App.)

1 0.1 0.005

Default thumb rules are

a) The junction with minimum area should be used as an input junction with forward

biasingand the other should be treated as an output junction with reversed biasing.

b) Doping Implant will decide total number of charge careers available for current flow; this

represents current carrying capacity of a structure. More number of charge careers at

output structure will allow larger amount of current flow at output, resulting into Current

Gain. Larger ratio (Say ) between output doping implant to Input doping implant results

into higher current gain.

c) Doping density indirectly represents structure resistance. Higher the doping densitylowers the device resistance. Larger ratio (Say ) between input doping density to output

doping density results into higher voltage gain.


Emitter Base Collector


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Configuration Output Input - Current Gain(Based on above

app.)

- Voltage Gain(Based on above

app.)

Remark

CB Collector Emitter 5 / 100 = < 0No

1 / 0.005 = 200Yes

MaximumVoltage Gain

CE Collector Base 5 / 1 = 5Yes

0.1/ 0.005 = 20Yes

AV*AI =Maximum

Power Gain

CC Emitter Base 10 / 1 = 10Yes

0.1/1 = < 0No

MaximumCurrent Gain

Comparison of Transistor Configurations

Sr.

No.

Characteristic Common Base Common Emitter Common Collector

1. Input signal applied

between

Emitter and Base Base and Emitter Base and Collector

2. Output signal taken

between

Collector and Base Collector and

Emitter

Emitter and

Collector

3. Input Current IE IB IB

4. Output Current IC IC IE

5. Current amplificationfactor

dc = IC/IE dc = IC/IB IE/IB

6. Input Resistance Very Low Low Very High

7. Output Resistance Very High High Very Low

8. Current Gain (Ai) Less than Unity Medium High

9. Voltage Gain (AV) High Medium Less than Unity

10. Application As a input stage of multistage amplifier

For audio signalamplification

For impedancematching or as a

buffer

Justify, Why CE configuration is widely used in amplifier circuits.



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Appendix B

Datasheet of BJT BC 547


BC546/547/548/549/550

82

Symbol Parameter Value Units

VCBO Collector-Base Voltage : BC546 : BC547/550 :BC548/549

80 50 30 V V V

VCEO Collector-Emitter Voltage : BC546 : BC547/550 :BC548/549

65 45 30 V V V

VEBO Emitter-Base Voltage : BC546/547 : BC548/549/550 6 5 V V

IC Collector Current (DC) 100 mA

PC Collector Power Dissipation 500 mW

TJ Junction Temperature 150 C

TSTG Storage Temperature -65 ~ 150 C

Symbol

Parameter Test Condition Min. Typ. Max.Units

ICBO Collector Cut-off Current VCB=30V, IE=0 15 nA

hFE DC Current Gain VCE=5V, IC=2mA 110 800

VCE(sat)

Collector-Emitter SaturationVoltage

IC=10mA, IB=0.5mA 90 250 mV

IC=100mA, IB=5mA 200 600 mV

VBE(sat)

Base-Emitter SaturationVoltage

IC=10mA, IB=0.5mA 700 mV

IC=100mA, IB=5mA 900 mV

VBE (on) Base-Emitter On Voltage VCE=5V, IC=2mA VCE=5V,IC=10mA

580 660 700720

mVmV

fTCurrent Gain BandwidthProduct

VCE=5V, IC=10mA,f=100MHz

300 MHz

Cob Output Capacitance VCB=10V, IE=0, f=1MHz 3.5 6 pF

Cib Input Capacitance VEB=0.5V, IC=0, f=1MHz 9 pF

NF Noise Figure : BC546/547/548 VCE=5V, IC=200A 2 10 dB

: BC549/550 : BC549 f=1KHz, RG=2K V CE=5V, 1.2 4 4 dB


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hFE Classification

General purpose switching and amplification.

DESCRIPTION

NPN transistor in a TO-92; SOT54 plastic package.

PNP complements: BC556 and BC557.

PIN DESCRIPTION

1 emitter

2 base

3 collector

Low current (max. 100mA)

Low voltage (max. 65V).

APPLICATIONS

83

FEATURES PINNING


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LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBO

L PARAMETER CONDITIONS MIN. MAX. UNITVCBO collector-base voltage open emitter

BC546 80 V

BC547 50 V

VCEO collector-emitter voltage open base

BC546 65 V

BC547 45 V

VEBO emitter-base voltage open collector

BC546 6 V

BC547 6 V

IC

collector current (DC) 100 mAICM peak collector current 200 mA

IBM peak base current 200 mA

Ptot total power dissipation Tamb 25 C; note 1 500 mW

Tstg storage temperature 65 +150 C

Tj junction temperature 150

Tamb operating ambient temperature 65 +150 C

Note

1. Transistor mounted on an FR4 printed-circuit board.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth j-athermal resistance from junction toambient

note 1 0.25 K/mW

1. Transistor mounted on an FR4 printed-circuit board.

CHARACTERISTICS

Tj=25 C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

UNIT

ICBO collector cut-off current IE = 0; VCB =30V 15 nA

IE = 0; VCB = 30 V; Tj = 150 C 5 A

IEBO emitter cut-off current IC = 0; VEB =5V 100 nA

hFE

DC current gain BC546A

IC =10 A; VCE =5V; see Figs

2, 3 and 4 90

BC546B; BC547B 150

BC547C 270

DC current gain IC = 2 mA; VCE =5V;

BC546A see Figs 2, 3 and 4 110 180 220

BC546B; BC547B 200 290 450

BC547C 420 520 800

BC547 110 800

BC546 110 450

VCEsat collector-emitter saturation IC = 10 mA; IB = 0.5 mA 90 250 mV

voltage IC = 100 mA; IB =5mA 200 600 mV

VBEsatbase-emitter saturationvoltage

IC = 10 mA; IB = 0.5 mA; note1

700 mV

IC = 100 mA; IB = 5 mA; note1

900 mV

VBE base-emitter voltage IC = 2 mA; VCE = 5 V; note 2 580 660 700 mV

IC = 10 mA; VCE =5V 770 mV

Cc collector capacitanceIE =ie = 0; VCB = 10 V; f = 1MHz

1.5 pF

Ce emitter capacitanceIC =ic = 0; VEB = 0.5 V; f = 1MHz

11 pF

fT transition frequencyIC = 10mA; VCE = 5 V; f = 100

MHz

100 MHz

F noise figure IC = 200 A; VCE =5V; RS=2k; f = 1 kHz; B = 200 Hz

2 10 dB

84


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Notes

1. VBEsat decreases by about 1.7 mV/K with increasingtemperature.2. VBE decreases by about 2 mV/K with increasingtemperature.

103

IC (mA)BC546B; BC547B.

Fig.3 DC current gain; typical values.

85


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hFE

200

100

50

0 102101 1 10 102 103IC (mA)

BC546A.


100

200

300

0 102101 1 10 102

hFE

400

200

0 102 1011 10 102 103

IC (mA)

BC547C.


86


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Appendix C

Datasheet of digital IC 7400



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APPENDIX D

Question Paper



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FACULTY OF TECHNOLOGYDHARMSINH DESAI UNIVERSITY, NADIAD

ELECTRONICS PRINCIPLES1ST SESSIONAL B. E.-SEM.-II (ALL)

DATE: 05-02-2008 Roll No. ___________ TIME: 1 Hour MAX. MARKS: 36

Q.-1: Answer the following. [06]

1. Justify, Most digital computers do subtraction by 2s complement method.

2. State the different ways to representing signed numbers.

3. Justify, An octal number is 1/3rd the length of corresponding binary number.

4. What is the advantage of frequency domain signal description?

5. State True or False with reason, The unpredictable signals are always carries

information.

6. Justify, The Sine-wave signal is extraordinary signal.

Q.-2: Answer the following.

1. Subtract 16 from 44 using 8-bit 2s complement arithmetic. [02]

2. Convert (367.28)10 to its equivalent octal number. [02]

3. Justify, The binary number system is a positional weighted system. With proper

example. [02]

4. Plot the frequency spectrum of input signal

V (t) =10sin100t+20cos (200t+/3) + 6sin (200t+/4) + 5sin (100t+/6). [03]

5. Plot the amplitude spectrum of 10V (pp), 10 KHz triangular wave. [03]

--------------------------------------------------OR-------------------------------------------------


1. Express (-73)10 in 8-bit 2s complement form. [02]

2. Convert (108.15)10 to its equivalent binary number. [02]

3. Give the different methods for obtaining the 2s complement of a given number. [02]4. Plot the frequency spectrum of rectangular pulse train with periodic time 1ms, 10V (pp)

amplitude and 20% duty cycle. [06]

Q.-3: Answer the followings. [06]



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1. We cannot use soft saturation in base bias circuit

to design switching circuits in mass production. State true/false with justification.

2. Draw the energy band gap diagram for biased and

unbiased transistor.

3. How can we find the circuit in saturation?

4. What are the factors affecting the current gain?

5. A 2N3904 has power rating 625 mW; Ic= 20 mA

and Vce= 10 V. How safe if the ambient temperature is 90 0C ?

[02]

Q.-4: Answer the followings.(Any three) [12]

1. Design a good voltage divider bias circuit with following specifications Vcc=20 V; Ic = 5

mA; Vce @ midpoint with stiff voltage source ranging from 80 to 400.

2. Show all transistor approximations & its effect on input & output curves & load line.

3. In voltage divider bias R1=10 K,R2=2.2 K, Rc=3.6 K, RE =1 K & Vcc=15 V. Draw

the load line and show the effect if (a) Rc increased and (b) RE decreased.

4. Give all types of biasing with figure and state its advantage or disadvantage only.

(description not required)



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FACULTY OF TECHNOLOGYDHARMSINH DESAI UNIVERSITY, NADIAD

ELECTRONICS PRINCIPLES2nd SESSIONAL B. E.-SEM.-II (ALL)

DATE: 18-03-2008 Roll No. ___________ TIME: 1 Hour MAX. MARKS: 36

Q.-1: Answer the following. [06]

1. State True or False with reason, Half wave symmetry indicates odd harmonics property

of signal.

2. What is the difference between frequency response and frequency spectrum?

3. Justify, The negative feedback reduces harmonic distortion in system.

4. Justify, Three or more variable EX-OR gates does not exist in market.

5. Convert 10110111011011102 to decimal by using Hexadecimal Conversion.

6. Justify 2 i/p -NOR gate is equivalent to 2 i/p bubbled AND gate.


1. The transfer characteristic of a device is given by V0=2Vi+0.5Vi2+0.3Vi3. If Vi=2+sinw0t,

find total harmonic distortion. If in the system Av=90 than find total harmonic distortion.

[04]

2. Draw the appropriate circuit diagram for frequency response like band reject filter andexplain in brief. [02]

3. Draw the simplest possible logic diagram that implements the o/p of logic diagram

shown in fig.1 [03]

4. Reduce the following expression up to its minimum level

(A+(BC)) (AB+(ABC)). [03]

--------------------------------------------------OR-------------------------------------------------


1. A non-linear device has the transfer characteristic given by V0=2Vi+0.5Vi2. If

Vi=1+0.5sinwt, find out the expression for the output assuming small signal operation.

[03]



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2. Find out the equation of output voltage for frequency response shown in fig. 2, if Vi=

2sin200t+4sin500t+5sin800t+7sin2000t. [03]

3. Draw a Four i/p NAND gate using Diode Transistor realization. [03]

4. Reduce the following expression up to its minimum level (((AB)+ABC)+A(B+AB)).

[03]

Q.-3: Fill in the blanks with appropriate answer. [06]

1. The D.C. load seen by the t

ep manual master final 28-01-10 new1

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