eoc status report giulio dellacasa gigatracker working group cern, december 9th 2008

EoC Status Report

Giulio Dellacasa GigaTracker Working GroupCERN, December 9th 2008

SEU aspects

Single flip-flops: Triple Modular Redundancy with voting FSM: States encoded using Hamming code, with auto-

recovery option from single errors Registers and FIFOs: Hamming code protected

During the design review of October it came out that also the End Of Column circuit must be SEU protected. So the circuit has been upgraded has follows

The adopted Hamming code allows to correct single-bit errors and to detect double-bit errors (but not to correct)

2Giulio Dellacasa GTK Working

GroupCERN 09/12/2008

Hamming code



Others changes

Depth of the 3 FIFOs (interchanging FIFOs and output FIFO) has been increased from 20 to 32 for two reasons To have a wider safety margin from overflows during the test

(simulations showed that 20 would be enough with a column rate of 4.5 MHz)

To have a depth which is power of 2 (more easy the design of the FIFO controller)

For those reasons (deeper FIFOs and SEU protections) the area of the EoC circuit increases from 250 x 750 µm to 300 µm x 2.5 mm (after floorplanning with occupancy 70%)



Synthesis

Synthesis has been performed with the following operating environment: clock frequency at 200 MHz (5 ns) VDD 1.08 Temperature 100 C

No timing violations observed in reports Post-Synthesis simulations has been performed at lower

frequency due the built-in delay there is the Synopsys library (3 ns each gate! Not realistic)

Only post-layout simulations will have realistic signals delays



EoC Layout

Internal-common signals (MQ)

From pixels (MG)External pads (MG)

Power rings (MQ)

Power rings (MG)

The design is not drawn to scale (300 µm x 2.5 mm)



Other things to change…

After a first floorplanning we discovered that we won’t have enough space for all the pads we need (29 differential signals + 9 debug/status signals)

One possible solution (maybe the only one) is to have serial data output from the EoC circuit (instead of the 16-bit parallel bus)

3 different serial data ports (+ 3 Dval ports) will provide the 3 columns read-out

Number of estimated signals with serial read-out: 15 (+ 9 debug/status)



Serial output

Each EoC circuit will be equipped with a 32-bit shift register working at 160 MHz by default, with the possibility to slow down at 80 or 40 MHz (work in progress)

One more differential signal will provide the write-enable signal for the DAQ (Data Valid Flag, Dval)



Conclusion

All the possible effort will be put in order to have a preliminary layout before Christmas, with the latest changes (serial output)

Post-Layout simulations and verifications will be performed in the beginning of January



eoc status report giulio dellacasa gigatracker working group cern, december 9th 2008

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