ensuring correctness of analog circuits using pattern matching rajeev narayanan, alaeddine daghar,...
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Ensuring Correctness of Analog Circuits Using Pattern Matching
Rajeev Narayanan, Alaeddine Daghar, Mohamed H. Zaki, and Sofiène Tahar
Hardware Verification Group, Dept. Of ECE,Concordia University, Montreal, Canada
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2FAC 2011
Motivation
Inheritance / Interactive
Noise
Non-Linearity
InfiniteState Space
TechnologyVariation
Combination of traditional and new verification strategies are needed
Analog Design
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3FAC 2011
Outline
• Simulation Based Methods• Pattern Matching
Longest Common Subsequence (LCS) Longest Closest Subsequence (LCSS)
• Proposed Methodology• Applications
Colpitts Oscillator Rambus Ring Oscillator
• Conclusion and Future Work
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4FAC 2011
State of the Art - Simulation
Behavioral Level Circuit Level
Statistical Modeling + Monte-Carlo Simulation
Pros:• Easy to Integrate• Fast
Cons:• Defining Complex Monitors• Accuracy of the Behavioral Model
Pros:• Accurate• Technology Aware
Cons:• Simulation Run-
Times• Difficult to Automate
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5FAC 2011
Question?
For different Monte-Carlo trials, if the simulation of the non-ideal circuit follows the output of an ideal circuit for say 99.0% and violates just 1.0% of the simulation time, ``Does the designer have to reject the circuit entirely?''
Pattern Matching Algorithm
# of Closely Matched Sequence
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6FAC 2011
Longest Common Subsequence (LCS)Given two sequences X[1..m] and Y[1..n], find a longest subsequence that is common to X and Y.
BCBA = LCS(X,Y)Run Time = O(n*2^m)
A
B
C
B
D
A
B
B
D
C
A
B
A
X(1:m)
m= 7
Y(1:n)
n= 6
One-to-One Mapping
One-to-One mapping is NOT possible for Analog Circuits
Closely Matching Sequence for a given tolerance level
Longest ClosestSubsequence(LCSS)
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7FAC 2011
Longest Closest Subsequence (LCSS)
LCSS(X, Y)
Brute-ForceMethod
RecursiveMethod
Computing the Length of LCSS
Optimal PathFinder
If 𝑌𝑛 ≤ (𝑋 𝑚+p) and 𝑌𝑛 ≥ (𝑋 𝑚 -p), then 𝑍𝑘 is an LCSS of 𝑋𝑚 and 𝑌𝑛
If 𝑋𝑚 ≠ 𝑌 𝑛 , then, if Zk ≠ Xm , then 𝑍𝑘 is an LCSS of 𝑋 -1𝑚 and 𝑌𝑛 If 𝑋𝑚 ≠ 𝑌 𝑛 , then, if Zk ≠ Yn , then 𝑍𝑘 is an LCSS of 𝑋𝑚 and 𝑌 -1𝑛
C[i,j] = C[i-1, j-1] + 1; (X𝑚 -p) ≤ Y𝑛 ≤ (X𝑚 +p)
max{C[i, j-1], C[i-1, j]}; otherwise
Worst-Case Run-Time = O(nm)
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8FAC 2011
Example – Chuas Circuit
Matching Percentage: 81.2% Run-Time
Brute-Force: 1.01 sec
Recursive: 0.49 sec
LCSS perform “Set-by-Set” matching rather
than “Value-by-Value” basis (Advantage during
Monte Carlo Simulation)
Efficient with offsets and signal with different
origins
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9FAC 2011
Dealing with Offset ConditionsStart-up Delay Time
Drift in Time Axis Ex: PLL Lock Time
Horizontal Offset
Shift of the entire signal Ex: Jitter Period
Question: How to verify such circuits that have offsets? Or Can we detect these offsets automatically?
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10FAC 2011
Proposed Methodology
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11FAC 2011
LCSS Based Offset Detection
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12FAC 2011
Application – Colpitts Oscillator Voltage divider made by C1 and C2 causes oscillation
L, C1 and C2 determine the frequency of oscillation
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13FAC 2011
LCSS Computational Results
• One ideal and Seven different Colpitts Oscillator Circuit
• Monte-Carlo Simulation of 1000 trials
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14FAC 2011
Rambus Ring Oscillator
Greenstreet et.al,
Question: What is the probability that the circuit will have the fastest start-up delay time and what is the “trade-off”? (Needed for PLL!!!)
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15FAC 2011
Parametric Analysis Sweep “r” and initial condition
Components Values are fixed at a given time
Not realistic – Follow MonteCarlo Simulation
Initial Condition = 1V
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16FAC 2011
MonteCarlo Simulation M = 100 trials
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17FAC 2011
What is the Trade-off?
38 out of 100 circuits have 67% matching and has fastest start-up
delay time (Initial Condition - 1V)
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18FAC 2011
Conclusion and Future Work
Methodology based on pattern matching for analog circuits LCSS based on variable simulation step-size Frequency Offsets Hypothesis Testing
hvg.ece.concordia.ca