enhancing a layout-aware synthesis methodology for analog ... · desenvolveu-se uma nova abordagem...

98
Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel Frederico Alexandre Esteves da Rocha Thesis to obtain the Master of Science Degree in Electrical and Computer Engineering Examination Committee Chairperson: Prof. Marcelino Bicho dos Santos Supervisor: Prof. Nuno Cavaco Gomes Horta Co-supervisor: Prof. João Paulo Baptista de Carvalho Member of the Committee: Prof. Rui Manuel Leitão Tavares October of 2012

Upload: others

Post on 28-Jul-2020

3 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Enhancing a Layout-Aware Synthesis Methodology for

Analog ICs by Embedding Statistical Knowledge into the

Evolutionary Optimization Kernel

Frederico Alexandre Esteves da Rocha

Thesis to obtain the Master of Science Degree in

Electrical and Computer Engineering

Examination Committee

Chairperson: Prof. Marcelino Bicho dos Santos

Supervisor: Prof. Nuno Cavaco Gomes Horta

Co-supervisor: Prof. João Paulo Baptista de Carvalho

Member of the Committee: Prof. Rui Manuel Leitão Tavares

October of 2012

Page 2: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento
Page 3: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

i

Abstract

The work presented in this dissertation belongs to the scientific area of electronic design automation

and addresses the automatic sizing of analog integrated circuits. Particularly, this work presents an

approach to enhance a state-of-the-art layout-aware circuit-level optimizer, by embedding statistical

knowledge from an automatically generated elementary gradient model into the multi-objective multi-

constraint optimization kernel based on the NSGA-II algorithm. The gradient model is automatically

generated by, first, using a design of experiments approach with two alternative strategies, the full

factorial design and the fractional factorial design, which define the samples from the design space

that will be accurately evaluated using the electrical simulator HSPICE®, second, extracting and

ranking the contributions of each design variable to each design performance or objective; and finally,

building the model based on series of gradient rules. The gradient model is embedded into the NSGA-

II based multi-objective multi-constraint optimization kernel, by acting on the crossover and mutation

operators. The achieved results for typical analog circuit structures show that, by enhancing the circuit

sizing optimization kernel with the gradient model, the optimal solutions are achieved considerably

faster and with identical or superior accuracy when compared with the non-enhanced optimization

kernel. The results are Pareto Optimal Fronts , which consist of a set of fully compliant sizing solutions,

allowing the designer to explore the different trade-offs of the solution space, both through the

achieved device sizes, or the respective layout solutions. Finally, the approach is here demonstrated

for traditional circuit structures using the UMC 0.13 µm integration technology.

Keywords

Analog Integrated Circuits Design

Automatic Sizing Generation

Electronic Design Automation

Evolutionary Computation

Genetic Algorithms

Gradient Model

Page 4: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

ii

Page 5: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

iii

Resumo

O trabalho desenvolvido nesta dissertação enquadra-se na área científica de automação de projectos

electrónicos, aborda o dimensionamento automático de circuitos integrados analógicos. Em particular,

desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta

de dimensionamento automático. A abordagem incorpora conhecimento do circuito descrito por um

modelo elementar de gradiente num kernel de optimização multi-objectivo e multi-restrição baseado

no algoritmo NSGA-II. O modelo de gradiente é gerado automaticamente, primeiro, através de uma

abordagem de design of experiments com duas estratégias possíveis, o Full Factorial Design e o

Fractional Factorial Design, que definem as amostras do espaço de projecto, em segundo lugar,

extraindo e classificando as contribuições de cada variável de projecto para cada variável de

desempenho ou objectivo do projecto, finalmente, construindo o modelo baseado numa série de

regras de gradiente. O modelo de gradiente está incorporado no kernel do NSGA-II baseado na

optimização multi-objectio e multi-restrição, agindo sobre os operadores crossover e mutação. Os

resultados obtidos para as estruturas típicas de circuitos analógicos mostram que, com a introdução

do modelo de gradiente no kernel de optimização, as soluções ideais são atingidas mais rapidamente

e com precisão idêntica ou superior em comparação com o kernel de optimização original. Os

resultados são Pareto Optimal Fronts, que consistem de um conjunto de soluções de

dimensionameto, permitindo ao designer explorar as diferentes soluções. Finalmente, a abordagem é

demonstrada para estruturas de circuitos tradicionais usando a tecnologia de integração UMC 0.13

µm.

Palavras Chave

Projecto de Circuitos Integrados Analógicos

Geração Automática de Dimensionamento

Automação de Projecto Electrónico

Computação Evolutiva

Algoritmos Genéticos

Modelo Gradiente

Page 6: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

iv

Page 7: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

v

Acknowledgments

I would like to acknowledge my supervisor Prof. Nuno Cavaco Gomes Horta for all the support, trust

and guidance since the first day, and also, the opportunity to develop my Master Thesis in the area of

integrated circuit in the unique conditions available in the Instituto de Telecomunicações. Nuno

Lourenço, for providing me the excellent tool he developed, GENOM-POF. His never-ending work,

support and motivation, allowed for this project to reach the level which I have the pleasure to present

in this document.

I would also like to present a word of recognition to Prof. João Paulo Baptista de Carvalho, whose

valuable discussions and ideas have undoubtedly contributed for the progress of this work.

I also want to thank my colleagues and friends, the faithful support and fellowship: Ricardo Martins,

Ricardo Póvoa, David Correia, Bernardo Ruivo and many others.

To my family, my dear parents and brother, being the fundamental basis of support and life-time

example of humbleness.

To Susana, my girlfriend and companion in this great adventure.

Page 8: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

vi

Page 9: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

vii

Table of Contents

ABSTRACT ...............................................................................................................................................I

KEYWORDS ..............................................................................................................................................I

RESUMO .................................................................................................................................................III

PALAVRAS CHAVE ...............................................................................................................................III

ACKNOWLEDGMENTS.......................................................................................................................... V

TABLE OF CONTENTS ........................................................................................................................ VII

LIST OF TABLES ................................................................................................................................... IX

LIST OF FIGURES ................................................................................................................................. XI

LIST OF ABBREVIATIONS .................................................................................................................. XV

CHAPTER 1 INTRODUCTION ..........................................................................................................1

1.1 Motivation .................................................................................................................. 1

1.2 Analog Design Flow ................................................................................................... 3

1.3 Goals ......................................................................................................................... 4

1.4 Achievements ............................................................................................................ 5

1.5 Document Structure ................................................................................................... 5

CHAPTER 2 STATE-OF-THE-ART ON AUTOMATIC ANALOG IC SIZING ...................................7

2.1 Design Flow: Circuit-Level Sizing ............................................................................... 7

2.2 Automated Circuit sizing ............................................................................................ 8

2.3.1 Knowledge-based sizing.................................................................................... 8

2.3.2 Optimization-based sizing ................................................................................. 9

2.3 Motivation for model-based optimization .................................................................. 14

2.3.1 Analyze of different models ............................................................................. 14

2.3.2 Choice of the model approach ......................................................................... 16

2.4 Conclusions ............................................................................................................. 16

CHAPTER 3 GRADIENT MODEL GENERATION ......................................................................... 19

3.1 Overview of Design of Experiments (DOE) .............................................................. 19

3.2 Design of Experiments with Full Factorial Design .................................................... 20

3.1.1. Step 1 - Characterization and construction of the matrix DOE ......................... 20

3.1.2. Step 2 - Evaluation of the DOE’s matrix .......................................................... 23

3.3 Design of Experiments with Fractional Factorial Design ( ) ......................... 24

3.3.1 Step 1 – Characterization and construction of the matrix DOE ........................ 25

3.3.2 Step 2 – Evaluation of the DOE’s matrix .......................................................... 26

3.4 Extraction of the Gradient Model from DOE ............................................................. 26

Page 10: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

viii

3.4.1 Step 1 – Maximum and minimum values of outputs ......................................... 26

3.4.2 Step 2 – Variables with the greatest Main Effect on each output ..................... 27

3.4.3 Step 3 – Generation of the Model .................................................................... 27

3.5 Conclusions ............................................................................................................. 29

CHAPTER 4 ENHANCED AIDA’S CIRCUIT-LEVEL OPTIMIZATION KERNEL .......................... 31

4.1 Architecture ............................................................................................................. 31

4.1.1 Inputs .............................................................................................................. 33

4.1.2 Structure of the Optimization Kernel ................................................................ 34

4.1.3 Outputs ........................................................................................................... 35

4.2 Integration of the Gradient Model in the Optimization Kernel ................................... 36

4.2.1 Gradient Model applied to the Crossover Operator.......................................... 39

4.2.2 Gradient Model Applied to the Mutation Operator ............................................ 40

4.3 Graphical User Interface (GUI) ................................................................................ 43

4.4 Conclusions ............................................................................................................. 47

CHAPTER 5 RESULTS .................................................................................................................. 50

5.1 POFs Analysis ......................................................................................................... 50

5.2 Random Model ........................................................................................................ 52

5.3 Case Study I – Single-Ended Folded Cascode Amplifier ......................................... 52

5.3.1 Case Study I for 15 input variables .................................................................. 53

5.3.2 Case Study I for 12 input variables .................................................................. 64

5.4 Conclusions ............................................................................................................. 70

CHAPTER 6 CONCLUSIONS AND FUTURE WORK ................................................................... 72

6.1 Conclusions ............................................................................................................. 72

6.2 Future Work ............................................................................................................. 72

REFERENCES ...................................................................................................................................... 74

Page 11: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

ix

List of Tables

Table 2.1 – Overview of analog sizing tools. ......................................................................................... 12

Table 2.2 – Overview of analog sizing tools [cont.]. .............................................................................. 13

Table 2.3 – Classification of translation tools based on techniques and abstraction level. .................. 14

Table 2.4 – Comparison between several models for sizing automation of ICs. .................................. 16

Table 3.1 - Range of input variables...................................................................................................... 21

Table 3.2 - Objectives and design constraints. ..................................................................................... 21

Table 3.3 - Variables with their values for each level of the DOE. ........................................................ 22

Table 3.4 - DOE’s matrix resultant for Full Factorial ( ), and their output. ......................................... 23

Table 3.5 - Main Effect obtained from the Full Factorial DOE matrix. ................................................... 24

Table 3.6 – DOE’s matrix constructed with the design: Fractional Factorial. ........................................ 25

Table 3.7 – Main Effect contributions of the input variables to DC Gain. .............................................. 26

Table 3.8 – Extraction of Gradient Rules for GBW. ............................................................................... 28

Table 3.9 - Set of Gradient Rules for GBW. .......................................................................................... 28

Table 3.10 – Overview of designs: Full Factorial and Fractional Factorial ............................................ 30

Table 4.1 - Range, objectives and design constraints example. ........................................................... 34

Table 4.2 - and normalization example. ................................................................................. 35

Table 5.1 – Range, objectives and constraints ..................................................................................... 54

Table 5.2 - Gradient generated for DC Gain (a0). ................................................................................. 56

Table 5.3 - Gradient generated for area. ............................................................................................... 56

Table 5.4 – POFs (20 different seeds) analysis for GENOM-POF. ....................................................... 61

Table 5.5 – POFs (20 different seeds) analysis for Gradient Model. .................................................... 62

Table 5.6 – POFs (20 different seeds) analysis for Random Model. .................................................... 63

Table 5.7 – Comparison between the models under study and GENOM-POF..................................... 64

Table 5.8 – Variables, ranges, objectives and constraints. ................................................................... 65

Page 12: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

x

Table 5.9 – Gradient Model generated for DC Gain (a0). ..................................................................... 66

Table 5.10 – Gradient Model generated for area. ................................................................................. 66

Table 5.11 – POFs (20 different seeds) analyses for GENOM-POF. ................................................... 68

Table 5.12 – POFs (20 different seeds) analyses for Gradient Model. ................................................. 69

Table 5.13 – Analyze of non-dominated area. ...................................................................................... 70

Table 5.14 – Summarized comparison between GENOM-POF and GENOM-POF + Gradient Model. 71

Page 13: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

xi

List of Figures

Figure 1.1 – Digital versus Analog design reality [18]. .............................................................................3

Figure 1.2 – From system level to device level tasks of analog IC design [3]..........................................4

Figure 2.1 – Circuit-Level flow. .................................................................................................................7

Figure 2.2 – Automatic sizing: knowledge-based. ....................................................................................8

Figure 2.3 – Automatic sizing: optimization-based. ..................................................................................9

Figure 2.4 – Automatic Circuit Sizing. ................................................................................................... 17

Figure 3.1 - Differential Amplifier. .......................................................................................................... 21

Figure 3.2 – Association between Range and DOE’s Levels. ............................................................... 22

Figure 3.3 – Full Factorial ( ) in hypercube, for DC Gain. .................................................................. 23

Figure 3.4 – Pseudo-code of getContributionMax(N). ........................................................................... 27

Figure 3.5 – Summary of the directions of the output variables. ........................................................... 29

Figure 3.6 – Pseudo-code for the generation of the model. .................................................................. 29

Figure 4.1 – AIDA Architecture. ............................................................................................................. 31

Figure 4.2 – GENOM-POF Architecture. ............................................................................................... 32

Figure 4.3 – GENOM-POF architecture with the integrated Gradient Model. ....................................... 32

Figure 4.4 – Electrical schematic of the single-ended folded cascode amplifier. .................................. 33

Figure 4.5 – POF obtained during the sizing task. ................................................................................ 36

Figure 4.6 – Abstract representation of the chromosome in the GA. .................................................... 36

Figure 4.7 – Abstract representation of the population in the GA. ........................................................ 37

Figure 4.8 – Evolution of the population in the GA. ............................................................................... 38

Figure 4.9 – Crossover operation. ......................................................................................................... 38

Figure 4.10 – Mutation operation. .......................................................................................................... 38

Figure 4.11 – Abstract representation of crossover operator integrated with the Gradient Model........ 39

Figure 4.12 – Example of application of the Gradient Model in the crossover. ..................................... 40

Page 14: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

xii

Figure 4.13 – Probability distribution for creating a mutated value [81]. ............................................... 41

Figure 4.14 – Example of application of the Gradient Model in the mutation. ...................................... 42

Figure 4.15 – Solutions search space for mutation integrated with Gradient Model. ............................ 43

Figure 4.16 – AIDA GUI: Overview. ....................................................................................................... 44

Figure 4.17 – AIDA GUI: Objectives. ..................................................................................................... 44

Figure 4.18 – AIDA GUI: Constraints. ................................................................................................... 45

Figure 4.19 AIDA GUI: Ranges of the input variables. .......................................................................... 46

Figure 4.20 – AIDA GUI: Strategy options, Gradient Model options and Typical Optimization options. 47

Figure 5.1 – Dominance solutions. ........................................................................................................ 50

Figure 5.2 – Trapezoidal numerical integration. .................................................................................... 51

Figure 5.3 – Illustration of non-dominated area. .................................................................................... 51

Figure 5.4 – Pseudo-code for Random Model. ..................................................................................... 52

Figure 5.5 – Electrical schematic and test-bench of the single-ended folded cascode amplifier. ......... 53

Figure 5.6 – GENOM-POF with mutation rate: 3% and for 2000 generations. ..................................... 55

Figure 5.7 – GENOM-POF with mutation rate: 30% and for 2000 generations. ................................... 55

Figure 5.8 – GENOM-POF for 60000 generations. ............................................................................... 56

Figure 5.9 – GENOM-POF + Gradient Model (Apply Rate = 50% and Change Ratio = 3%) for 2000

Generations. .......................................................................................................................................... 57

Figure 5.10 – GENOM-POF (60000 gen., 4000gen., 2000gen.) vs. GENOM-POF + Gradient Model

(2000 gen.). ........................................................................................................................................... 58

Figure 5.11 – 20 different initial populations for comparison between GENOM-POF and Gradient

Model. .................................................................................................................................................... 59

Figure 5.12 – Random Model for 20 different initial populations. .......................................................... 59

Figure 5.13 – GENOM-POF for single-ended folded cascode amplifier with 12 variables for

optimization. ........................................................................................................................................... 65

Figure 5.14 – Gradient Model for single-ended folded cascode amplifier with 12 variables for

optimization. ........................................................................................................................................... 66

Figure 5.15 – Comparison between GENOM-POF and GENOM-POF + Gradient Model. ................... 67

Page 15: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

xiii

Figure 6.1 – Alternative approach of application of Gradient Model. .................................................... 73

Page 16: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

xiv

Page 17: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

xv

List of Abbreviations

ADA Analog Design Automation

AMS Analog and Mixed-Signal

CAD Computer Aided Design

DOE Design Of Experiments

DSP Digital Signal Processing

EDA Electronic Design Automation

GA Genetic Algorithm

GP Geometrical Programming

IC Integrated Circuit

POF Pareto Optimal Front

SoC System-on-a-Chip

SVM Support Vector Machine

VLSI Very Large Scale Integration

Page 18: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

xvi

Page 19: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

1

Chapter 1 Introduction

This chapter approaches the evolution of integrated circuits (ICs) and the difficulties in the automatic

generation of analog ICs, which motivate this research in the area of analog IC design automation.

1.1 Motivation

In the last decades, Very Large Scale Integration (VLSI) technologies have been widely improved,

allowing the proliferation of consumer electronics and enabling the growth of Integrated Circuit (IC)

market from $10 billion in 1980 to more than $300 billion in 2013 (according to IC Insights Inc.) [1].

IC designers are building systems that are increasingly more complex and the integration in modern

systems is extremely high. In the System on Chip (SoC) age [2] it is common to find devices where the

whole system is integrated in a single chip. The complexity of electronic systems, the extremely

competitive markets, and the strict time-to-market impose the use of Computer Aided Design (CAD)

tools to support the design process.

In digital IC design, several Electronic Design Automation (EDA) tools and design methodologies are

available that help the designers keeping up with the new capabilities offered by the technology. On

the other hand, electrical simulation is the only analog design automation tool really established,

despite the algorithms and techniques introduced in the last 25 years [3].

Due to the lack of automation, designers keep exploring the solution space manually. This method

causes long design times, and allied to the non-reusable nature of analog IC, makes analog IC design

a cumbersome task. This difference in the level of automation between analog and digital design is

because analog in general is less systematic, more heuristic and knowledge intensive than the digital

counterpart, and becomes critic when digital and analog circuits are integrated together.

It is well acknowledged that presently most functions in mixed-signal ICs and SoC designs are

implemented using digital or digital signal processing (DSP) circuitry, where analog blocks constitute

only a small part of the components, being essentially the link between digital circuitry and the

continuous-valued external world. When integrating digital and analog circuits together on the same

die, to reduce production costs and increase performance, it becomes notorious that the development

time of analog blocks is much higher when compared with the development time of digital blocks [2].

Given the giant growth of analog mixed signal (AMS) systems, pressed by the need of the new

electronic products, which are affordable and reliable, and developed under very strict time-to-market

constraints, the development and improvement of computer aided design (CAD) tools that increase

analog designers’ productivity and the quality of the resulting designs is an urgent need.

Analog ICs designs are difficult to reuse, therefore designers have been replacing functions of analog

circuits for digital computing whenever possible. However, there are some typical blocks that will

remain forever analog, such as [4]:

Page 20: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

2

On the input side, the signals of a sensor, microphone or antenna has to be detected or

received, amplified and filtered, to enable digitalization with good signal-to-noise and distortion

ratio. Typical applications of these circuits are in sensor interfaces, telecommunication

receivers or sound recording;

Mixed-signal circuits like sample-and-hold, analog-to-digital converters, phase-locked loops

and frequency synthesizers. These blocks provide the interface between the input / output of a

system and digital processing parts of a SoC;

On the output side, the signal from digital processing must be converted and strengthened to

analog so the signal can be conducted to the output with low distortion;

Voltage/current reference circuits and crystal oscillators offer stable and absolute references

for the sample-and-hold, analog-to-digital converters, phase-locked loops and frequency

synthesizers;

The last kind of analog circuits are extremely high performance digital circuits. As exemplified

by the microprocessors custom sized as analog circuits, for achieving the highest speed and

the lowest power consumption.

The developments on the IC fabrication processes enabled the design of extremely complex electronic

systems. These complex single IC designs are established in telecommunications, medical and

multimedia applications, where blocks of AMS, digital processors and memory blocks appear together

[2][3][5]. To increase the performance of ICs, i.e. enhance functionalities with lower power

consumption, there is an exponential increase of the density of ICs, as described by Moore’s law. This

means that the designers deal with the project ICs containing billions of transistors, under extreme

competitive market conditions.

Moore’s law states that every two years the density of transistors on ICs doubles, and remains valid to

today. As expected, this increase in density of the transistors becomes more and more of concern to

the manufacturers. The major concerns are due to the fact that the leakage and parasitic currents are

increasing with density which causes the chips failures. This type of problems that circuit designers

face today and in the future makes a decrease in the productivity rate of design.

Despite the analog section in the SoC occupy only approximately 20% of the global circuit area (as

shown in Figure 1.1) the design effort is considerably higher in comparison to the design effort of

digital section. In digital design, it is usual to reuse digital projects unlike analog projects, leading to an

increased productivity of design. By contrast, in analog design there are no mature and well-defined

strategies to address a problem, leading to custom solutions that are difficult to reuse.

Despite the developments achieved in recent years in analog design automation, the analog design

tools and methodologies are still far from achieving a mature state, as there is no automation tool

really established to support the analog design flow.

Page 21: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

3

Figure 1.1 – Digital versus Analog design reality [19].

1.2 Analog Design Flow

A design flow well known and accepted for analog-mixed signal ICs is described in Figure 1.2. This

design flow was introduced by Gielen and Rutenbar in [4], which consists of a series of top-down

design selection and specifications step by step, from system level to the device level, and bottom up

layout generation and verification.

At the circuit level an optimization process is performed for each analog block. This process is

performed iteratively in order to determine the physical dimensions of each device. In this phase are

considered two major groups: the selection of circuit topology and a suitable methodology for the

design parameters of the electronic devices. The specifications required in the final draft of the circuit

are then verified through simulation of the circuit by HSPICE® [7] or Spectre® [8]. In the process of

circuit sizing and optimization there are two main approaches for automated circuit sizing, the

knowledge-based approach and an optimization-based approach.

After the analog blocks have been optimized the project enters into the next phase, where the analog

blocks are mapped into a physical representation of the circuit. Layout is therefore a set of geometric

shapes that obey to a certain number of rules defined by the manufacturing process. Typically, the

desired layout for a designer generated either manually or automatically is to have the smallest

possible area while reducing the parasitc effects in the circuit perfornamce. Then the layout needs to

pass the design rule check and the layout-versus-schematic. Finally this is extracted and simulated to

verify the impact of layout parasites on the overall performance of the circuit.

Despite the analog automation tools do not progress at the same pace of technology, knowledge and

experience of the designer is always crucial for making decisions at all stages of the analog design

flow. In a traditional analog design, the designer defines a methodology; interact manually with the

proper tools in order to achieve the project objectives, whether they are the best sizing of circuit

parameters to meet the desired performance specifications, either to optimize the parameters for

specific application (DC Gain, power, area, etc.), obtaining at the end a robust design. However, the

search space of the objective function, which relates the optimization parameters and the performance

specifications of the circuit, is characterized by a complex multidimensional and irregular space,

making the manual search for the ideal solution difficult to achieve. Along with the time constraints that

designers face, this search space becomes very limited.

Page 22: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

4

More

Abstract

More

Concrete

Circuit

Level

Level i

Verification

Extraction

Verification

Topology

Selection

Specification

Translation

Layout

Generation

Re

de

sig

n

Specification (level i+1) Layout (level i+1)

Specification (level i) Layout (level i)

System

Level

Device

Level

Backtracking

Redesign

Validation

Backtracking

Level i+1

...

...

Top-Down Electrical

Synthesis

Bottom-Up Physical

Synthesis

Validation

Redesign

Figure 1.2 – From system level to device level tasks of analog IC design [4].

In manual analog circuit design, designers are aided by CAD frameworks comprised by many tools

such as electric circuits simulators (for example, Spectre® [8] or HSPICE® [7]), by layout editors (e.g.,

layout Cadence Virtuoso [8]), or tools of verification (e.g., Cadence [8] and Mentor Diva [9]). Despite its

fundamental aid to designers, these tools have limited automation options, and the ones available are

usually not used by the majority of the designers. The time required to manually implement an analog

project is usually of weeks or months, which is in opposition to the market pressure to accelerate the

release of new and high performance ICs. To address all these difficult to solve problems, electronic

design automation (EDA) CAD is a solution increasingly strong and solid.

The use of tools to manage designs, integrated with some CAD tools and a database for dealing with

changes in the project from design to physical implementation, can also accelerate the development of

the project and consequently the productivity of designers. However, these management platforms are

far short of its technological potential compared with the existing for digital projects.

1.3 Goals

The general objective of this work is the enhancement of GENOM-POF, which performs a layout-

aware circuit-level optimization. The work of this thesis aims to demonstrate the advantage of

embedding simple statistical models, representing design knowledge, into the optimization kernel in

order to enhance the sizing optimization. The main objectives for this work are detailed below:

Page 23: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

5

- Create a simple model that is capable of extracting a set of gradients rules, automated and

autonomously, i.e. without any human knowledge. This set of gradients rules extracted should

contain knowledge about any analog circuit in study.

- Create a model of rules and integrate it with the Crossover/Mutation operator of the NSGA-II

[77], in order to improve its efficiency during the optimization of the analog circuit. Compare

the NSGA-II with the modified NSGA-II with the model of gradients, created in the previous

paragraph, and verify potential benefits of this modification.

- Evaluate and analyze the robustness of the models created previously, through its application

in highly complex analog circuits.

The goal of this work is not restricted to just reach the specifications proposed in an analog design, but

also improve the quality of sizing. The designer provides the chosen topology for the project, the

variables for optimization and their ranges, the specifications to be met and the objective functions

(e.g. minimize area/power, maximize DC Gain, etc.), the tool instantiates the components to size,

ensures that specifications are met and performs the search space of objectives.

The modified GENOM-POF, produced within this work, aims at helping the designer in his/her circuits

sizing task, not only by generating solutions faster but also by achieving better Pareto optimal

solutions.

1.4 Achievements

During the development of the methodology proposed in this thesis the following achievements were

obtained:

The work was integrated and validated using the state-of-the-art analog IC design automation

environment AIDA [6], which implements an automatic design flow from circuit-level

specifications to GDSII layout descriptions.

1.5 Document Structure

This document is organized as follows:

Chapter 2 presents a study of the existent approaches for analog IC design automation (ADA).

The aim is to analyze and compare methods and tools used until the present day, focusing on

the various strategies used and their relevant potential, both in terms of optimization and

modeling.

Chapter 3 describes the proposed methodology for the generation of the Gradient Model, with

emphasis on the sampling technique Design Of Experiments (DOE) and his respective

statistical analysis.

Chapter 4 presents the architecture and operation of the proposed approach for circuit-level

optimization, the NSGA-II – GENOM-POF. The integration of the optimization tool with the

Gradient Model Is described and discussed..

Page 24: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

6

Chapter 5 presents the developed work addressing a case study divided in two different

optimization problems and illustrates the capabilities of the implementation.

Chapters 6 shows the final conclusions, given the objectives, and outlines a set of topics for

future work concerning the development of Gradient Models to be embedded in automatic

circuit-level sizing tasks.

Page 25: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

7

Chapter 2 State-of-the-Art on Automatic Analog IC Sizing

This chapter presents the state-of-the-art on analog IC design automation tools and their evolution to

address the problem of circuit-level sizing. First, an overview of sizing process will be introduced, and

then, the techniques used for the automation of analog sizing are presented and discussed. Finally,

the motivation of this work is introduced by the presentation and comparison between the different

models.

2.1 Design Flow: Circuit-Level Sizing

The focuses of this dissertation is at circuit-level, and more properly the circuit sizing. Figure 2.1

presents the flow of this focuses in analogy to Figure 1.2 presented in the previous chapter.

Circuit-Level

Verification

Topology

Selection

Circuit Sizing

Layout

Generation

Re

de

sig

n

Top-Down Electrical

Synthesis

Bottom-Up Physical

Synthesis

Verification

Extraction

Figure 2.1 – Circuit-Level flow.

Leveling and abstraction to describe and simulate complex analog circuits becomes increasingly

necessary. This happens for three main reasons. First, in a sizing methodology, the detailed rules for

lower levels are still unknown, it is necessary to create models that translate high-level behavior. The

second reason is that the verification of mixed-signal ICs requires a description of higher levels for the

analog blocks, since these ICs are highly complex and computationally heavy, so that it can perform a

full simulation of the mixed-signal project. Finally, the use of IP macro cells in SoC, its virtual

component needs to be modeled efficiently.

The accuracy and precision of the analog sizing is obtained by simulation tools [10]. However, the

performance of analog ICs are highly affected by parasitic effects after its production, this type of

factors have to be taken into account during the sizing process.

Although this thesis aims to optimize the sizing process of the circuit, this is interconnected with the

generation of the layout, as illustrated above.

Page 26: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

8

The major methodologies for the automatic sizing of analog ICs proposed by the scientific community

will be presented in detail in the next section.

2.2 Automated Circuit sizing

After selecting the topology, the next step is to perform the circuit sizing. Many techniques for the

circuit sizing problem have been proposed by the scientific community over the past 20 years. Some

applied to the circuit level, others at the system level, or even both. Tools for automated circuit sizing

can be classified as knowledge-based or optimization-based, which will be explained in detail below.

2.3.1 Knowledge-based sizing

The first strategy to accomplish the task of circuit sizing was to use a design plan derived from

specialized knowledge. In this way, the designer knowledge has an important role in creating a design

plan along with equations and the strategy for components sizing according with performance

requirements. Figure 2.2 shows the strategy flow of knowledge-based sizing.

DESIGN PLAN

EXECUTION

KERNEL

DESIGN PLAN

AUTHORING

Design Specs

Design Plan

DE

SIG

N P

LA

N

LIB

RA

RY

Design

Parameters

Sized Circuit

Figure 2.2 – Automatic sizing: knowledge-based.

IDAC [20] uses the designer knowledge to carry out the design plan, where all the design equations

are solved during the setup of plan. As soon as the topology is chosen, the plan is performed to the

required specifications and a design is achieved. The obtained design has a local optimization. This

tool has a varied library of topologies with OpAmps, comparators, oscillators, DACs, ADCs, etc.

OASYS [21] addresses the issue with the same strategy, however it defines a hierarchy and makes a

design plan for each sub-block. This tool also added backtracking with design-reuse methodology for

retrieving design errors. BLADES [22], CAMP [49] and ISAID [56][57], present a strategy a little

different from those shown above, where the knowledge of the designer is embedded in artificial

intelligence techniques.

Page 27: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

9

The knowledge-based strategy achieved satisfactory results both in terms of circuit and system level.

The major advantages of this strategy are the short runtime and the incorporation of the design

knowledge in the plan. However, derivation of design plan is complicated and takes much time.

Another disadvantage of this approach is the constant need to keep the design plan updated with the

evolution of technology, and finally the results are not optimal, which makes this approach a first-cut-

design.

2.3.2 Optimization-based sizing

A totally different approach emerged through optimization-based sizing, where optimization techniques

were added to the tools. As the name suggests, the addition of such techniques had as main objective

to achieve optimal design solutions. The optimization-based sizing can be classified into three major

subclasses based on different techniques of evolution and they are: equation-based, numerical-

simulation-based and numerical-model-based. A typical flow of optimization-based strategy can be

seen in Figure 2.3.

Design Specs

OPTIMIZATION

KERNEL

Circuit

Performances

EV

AL

UA

TIO

N

EN

GIN

E

Sized Circuit

Design

Parameters

Spice Simulations

Equations

Model (SVM, NN)

Layout Inclusive

...

Figure 2.3 – Automatic sizing: optimization-based.

2.3.2.1 Equation-based

The equation-based approach consists of evaluating the performance of the circuit through analytical

design equations. In OPTIMAN [51] optimization is performed by applying simulated annealing to

analytical models created automatically by ISAAC [72]. ASTRX/OBLX [59] performs simulated

annealing also, using a cost function defined by equations for the DC operating point and small signal

Asymptotic Waveform Evaluation (AWE). DARWIN [30] uses the same type of technique. DONALD

[52] is a tool that performs the circuit sizing via the automatic manipulation of the circuit equations,

performing a space exploration of different sizings. Maulik et. al. [54] introduced the sequential

Page 28: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

10

quadratic programming in solving the issue of sizing considering a non-linear optimization problem and

using spice models and DC operating point constraints.

GPCAD [73] uses the Geometrical Programming (GP) to optimize a posynomial circuit model. Through

this technique, the sizing process was reduced to a few seconds with sizing results satisfactory.

Despite these promising advantages, the high time to extract the model for new circuits and the

application of posynomial models to all circuits is too heavy in terms of computational resources.

With the aim of solving the problems of modeling, Kuo-Hsuan et. al. [68] introduced the posynomial

modeling with geometric programming convex optimization. The model efficiency was achieved by the

addition of a local optimization using simulated annealing and circuit simulator. FASY [24][25] uses the

same type of strategy, where an initial solution is obtained by solving equations and then uses a

simulation-based optimization to refine the solution.

Despite being mostly used at the circuit level, the equation-based approach is also applied to the

system level. This is the case in SD-OPT [58], where the equation-based approach is applied in a

sigma-delta modulator. Also Doboli et. al. [46] uses the same approach, applying genetic programming

techniques to simultaneously get the specifications, topologies and sizing of sub-blocks.

The greatest advantage of equation-based approach is the short time that requires for evaluation, such

as knowledge-based approach, is excellent for first-cut designs. Moreover, the biggest disadvantage is

the great difficulty in extracting new models, despite the advances in analytical equations, which on

one hand facilitate the extraction of new models, due to approximations introduced in the equations it

produces less efficient results especially in complex circuits.

2.3.2.2 Numerical-simulation-based

The increase in computational resources provided a tremendous advantage to the simulation-based

optimization, in comparison with the approaches outlined above. In this approach SPICE [74] and

spice like electrical simulators are used to evaluate the circuits. In DELIGTH.SPICE [50], the designer

introduces a starting point from which the algorithm makes a local optimization. Kuo-Hsuan et al. [68]

and FASY [24][25] use numerical-simulation along with the simulated annealing to optimize the design.

Cheng et al. [67] focuses on the sizing problem by looking at the transistors bias conditions and

solving these conditions as constraints. The sizing of transistors is thus extracted from the bias point

using electrical simulations. In FRIDGE [55] optimization is done globally without any starting point

restriction. However, the designer introduces a range for the variables to be optimized for a finite

search space. MAELSTROM [60] and ANACONDA [61] reduce the time of evaluation by parallel

computation through a mechanism shared by multiple computers. MAELSTROM [60], however, due to

the huge success proven, used in many implementations the parallel re-combinative simulated

annealing. ANACONDA [61] also had a similar approach, however applied the parallel re-combinative

simulated annealing in algorithms for pattern matching, given the name of stochastic pattern search.

A different approach is taken in GENOM-POF [75], where a strategy of multi-objective is applied

through the use of evolutionary algorithms. In this approach the objectives and constraint functions are

Page 29: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

11

evaluated by HSCPICE [7]. GENOM-POF [75] outputs the Pareto optimal fronts (POF) with the

tradeoff between objectives, so the designer has a wider range of solutions and choices to the problem

of sizing.

The easy modeling (through the netlist of the circuit) and subsequent simulation is the strong point of

the techniques of numerical-simulation-based, but the runtime is high for complex circuits (with 100 or

more variables), which makes it almost impossible to use at system level. Furthermore, if the

constraints are misappropriated it may hinder the convergence of the algorithm.

2.3.2.3 Numerical-model-based

The basis of the approach of numerical-model-based is the evaluation of the circuit through the use of

macro models, like neural networks. To not fall into the same disadvantage of the technique of

numerical-simulation-based concerning the runtime of the simulations, models of learning are

incorporated in the optimization algorithm. Thus, the use of circuit simulators is decreased and

therefore obtains more quickly efficient sizing solutions. These models are automatically generated

before the optimization process, to be after integrated in the optimization algorithm. In general, these

models are easily generated and trained unlike the equations-based technique, however, there is a

relationship to take into account between the efficiency of the model and its generation time.

Alpayding et. al. [62] uses a neural-fuzzy model integrated into evolutionary optimization together with

equation-based approach for some AC metrics. The support vectors machines (SVM) is used by De

Bernardinis et. al. [70], this model is generated from the knowledge acquired by a set of electrical

simulations.

Wolfe et. al. [71] presents a model based on a neural network, which aims to increase the efficiency in

computing the parameter estimation. This goal is achieved by replacing the SPICE [74] by the model.

The set of vectors that are simulated to train the model are discrete points of the design space.

Several methods are presented for construction of these vectors in order to improve the performance

of the model. From this model are extracted rules to be applied on an optimization loop of an

automatic sizing task.

Barros et. al. [19][63] presents an optimization approach based on SVMs and evolutionary strategies,

at the level of the cell. The SVM is trained based on identifying potential feasible areas and

simultaneously search for a global optimization. HSPICE® [7] is used in evaluation to ensure the

precision, however the number of evaluations is reduced by using the model.

In Table 2.1 the various tools for analog sizing automation are summarized, and Table

2.3 presents the different classifications of translation tools based on the different techniques used.

Page 30: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Table 2.1 – Overview of analog sizing tools.

Tool\Author Circuits Design

Plan/Optimization Evaluation

Robust

Design

Topology

Layout Time

Setup/Exec

Code

IDAC [20] 1987 Analog Cells Design plan plus SA

post-optimization Equations - -

after sizing

months /few sec.

Pascal

DELIGTH.SPICE [50] 1988 Analog Cells Feasible directions

Optimization SPICE-like - -

moderate /18h

-

OASYS [21] 1989 OPAMP Design plan (includes backtracking features)

Equations before - 6 months

/3 sec. LISP

BLADES [22] 1989 OPAMP Expert system for

analog design Equations - before -

long /20 min.

LISP

OPASYN [23] 1990 OPAMP Steepest descent Equations before after sizing

2 weeks /5 min.

C and LISP

CAMP [49] 1990 OPAMP Expert system, flexible

architecture SPICE-like - during

after sizing

- /-

TURBO PROLOG

OPTIMAN [51] 1990 OPAMP SA Analytical models

ISAAC[57] - - -

-

/1 min. VAX PASCAL

SEAS [31] 1991 OPAMP SA Equations - during - - /-

C

DONALD [52] 1991 OPAMP Equation solver

(Newton Raphson variant)

Equations - - - - /-

LISP/ DIALOGUE/ FORTRAN

Chang [39] 1992 ADC Top-Down constraint

driven behavior models - during

after sizing

-

/4-89 hours

C++

STAIC [53] 1992 OPAMP 2 step optimization Equations - - after sizing

long /2 min.

C++

MINLP [28][29] 1992 OPAMP Branch & Bound Equations and BSIM

models - during -

6 months /1 min

-

Maulik et al. [54] 1993 OPAMP Sequential Quadratic

Programming Equations and BSIM

models - - -

6 months /1 min

C

FRIDGE [55] 1994 OPAMP SA SPICE-like - - - 1 hour /45 min

-

DARWIN [30] 1995 OPAMP GA small signal,

analytical expressions. - during -

- /-

-

ISAID [56][57] 1995 OPAMP Qualitative reasoning +

post optimization Equations and

Qualitative reasoning - - -

- /-

C\ PROLOG

SD-OPT [58] 1995 ΣΔ-

modulator SA

Equations and behavioral simulation

- - - long

/1,5 week -

12

Page 31: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Table 2.2 – Overview of analog sizing tools [cont.].

FASY [24][25] 1996 OPAMP SA + Gradient SPICE-like - before - -

/6 hours -

ASTRX/OBLX [59] 1996 Analog Cells SA AWE

Equations - - -

few days /few

seconds C

Koza [34] 1997 Analog Cells GA SPICE-like - during - - /-

C

GPCAD [69] 1998 OPAMP Geometric

Programming Posynomial models - - -

-

/fast MATLAB

Lohn [35] 1999 Filters GA SPICE-like - during - - /-

C

MAELSTROM [60] 1999 OPAMP GA+SA SPICE-like - - - -

/3,6 hours C++

ANACONDA [61] 2000 OPAMP Stochastic pattern

search SPICE-like - - -

-

/10 hours C++

Sripramong [36] 2002 OPAMP GA SPICE-like - during - -

/3 days C

Alpaydin [62] 2003 OPAMP Evolutionary strategies

+ SA Fuzzy + NN

trained with SPICE-Llike - -

-

/45 mins -

Shoou-Jin [37] 2006 Passive Filters

GA equations - during - - /-

-

Barros [19][63] 2006 Analog Cells GA SPICE-like + feasibility

SVM models - -

-

/20 min C

Castro-Lopez [64] 2008 OPAMP SA + Powels method SPICE-like - - - /25 min -

MOJITO [32][33] 2009 OPAMP GP(NSGA-II) SPICE-like during - - /<7 days Python

Pradhan [65] 2009 OPAMP,

Filter Multi-Objective SA

Layout aware MNA models

- - - -

/16 min C++

Matsukawa [66] 2009 ADC Convex Optimization Convex functions after - - /-

MATLAB

Roca [48] 2009 - - - - - - - -

Cheng [67] 2009 OPAMP SA Equations - - -

/<1 hour C

Hongying [38] 2010 OPAMP GA with VDE SPICE-like - during - - /-

-

Kuo-Hsuan [68] 2011 RFDA Convex optimization

Stochastic Fine Tuning posynomial SPICE-like

- - - -

/1 hour MATLAB

GENOM-POF [75] 2012 OPAMP Multi-Objective GA SPICE like - - -

/10 min C

13

Page 32: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

14

Table 2.3 – Classification of translation tools based on techniques and abstraction level.

Abstraction Level

System-Level Cell-Level

Kn

ow

led

ge

-based

TAGUS [41][42][43]

(+) Fast execution time (+) Use of Expert knowledge

(-) Expert knowledge is difficult to capture

(-) not optimal

IDAC[17] ;OASYS[18] ; BLADES[19]

CAMP[50] ; ISAID[53, 54]

(+) Fast execution time (+) Use of Expert knowledge

(-) Expert knowledge is difficult to capture (-) not optimal

Op

tim

izati

on

-based

Eq

uati

on

SD-OPT [58]; Doboli [46]; Matsukawa [66]

(+) Fast execution time (+) Use of Expert knowledge

(-)Difficult derivation of some equations (-) Simplifications lead to lack of accuracy

OPASYN [23]; STAIC [53]; Kuo-Hsuan [68]

OPTIMAN [51]; DONALD [52] ASTRX/OBLX [59]; DARWIN [30];

GPCAD [69]

(+) Fast execution time (+)* Use of expert knowledge

(+)* Automatic symbolic analysis (-) Difficult derivation of some equations

(-) Simplifications lead to lack of accuracy

Nu

meri

cal-

sim

ula

tio

n

Kuo-Hsuan [68]; FASY [24][25] ASTRX/OBLX [59];DARWIN [30] DELIGTH.SPICE [50];Cheng [67] FRIDGE [55]; MAELSTROM [60]

ANACONDA [61]; Castro-Lopez [64]; GENOM-POF [75]

(+) Easy to develop models

(++) Accurate and flexible (-) Still requires expert knowledge

(-) Long execution time (-) Limited to cell-level

Nu

meri

ca

l-m

od

el

Roca [48]

(+) Accurate and flexible

Alpaydin [62] ;De Bernardinis [70]

Wolfe [71]; Barros [19][63]

(+) Accurate and flexible (-) Limited to cell-level

* not present in all approaches

2.3 Motivation for model-based optimization

2.3.1 Analyze of different models

According to a study made by McConaghy and Gielen [76], there is a great improvement on efficiency

in the optimization cycle of the simulator for analog circuits, if models containing knowledge about the

circuit are used. This study analyses the impact of different models in the optimization process, which

were made for the following techniques: polynomials [14], posynomials [13], genetic programming [11],

feedforward neural networks [15], boosted feedforward neural networks [16], multivariate adaptive

regression splines [12], support vector machines [17] and Kriging [18].

Page 33: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

15

The choice of the models was based on their performance, and the following modeling methods were

considered:

As reference models were used: a constant (set as the mean of the data), a linear model, and

a 2nd

-order polynomial were used.

CAFFEINE [11] tool used a modified form of genetic programming (GP). CAFFEINE restricts

GP to canonical function forms via a grammar.

Boosting [16] creates a “stack” of models, each model is learned on a weighted version of the

data. The overall output is the average of the outputs of the individual models.

Feedforward neural networks (FFNNs) [15] which used the state-of-art training algorithm

OLMAM.

Multivariate Adaptive Regression Splines (MARS) [12] are piecewise polynomials. In the

constructive steps, input variables are iteratively added on as “as-needed” basis for greedily

chosen sub-regions of input space. MARS scales to a high number of input variables but is

locally accurate.

Support vector machines (SVMs) transform inputs into a space of much higher dimension and

do linear regression in that space. A fast-learning variant LS-SVM [17] was used.

Kriging [18] originated in geostatistics, but it has been shown to be useful in optimization. In

this model prediction is the value of nearby samples “corrected” by a correlated error

calculation.

Of the several existing ways to improve the optimization efficiency, the study indicates that the

construction of all models was based on the use of a Design of Experiments (DOE) technique [79].

Since circuit simulation is the bottleneck in simulator-in-the-loop optimization, improving efficiency

roughly translates to reducing the number of simulations, and thus emerges the need for the creation

of learning models that can improve this process, but, the commitment of these models will have a

high rate of prediction of unseen data.

For the comparison between different models another point to be taken into account it is the setup time

(the time necessary to create the model), which produce a tradeoff between model performance and

model setup time. None of these points of comparison can be disregarded, because if in one hand the

prediction error represents the reduction on the optimization loop, on the other hand the time setup

represents if that reduction on the optimization loop is valid or not.

Table 2.4 presents a summary of the study for the different models. From Table 2.4, CAFEINE is the

approach with the better performance of error prediction. On the other side, the Polynomial approach

has the worst performance in comparison with all the models compared. Based on this study, is fair to

say that the type of approach made in CAFFEINE will produce a reduction in the number of

simulations on loop of optimization. However, the setup time of this model is very high; a model that

has a setup time greater than the execution time is a huge contradiction in the optimization process.

Page 34: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

16

Table 2.4 – Comparison between several models for sizing automation of ICs.

Model Date Heuristics Circuits Simulator

Time Setup/

Exec.

Lang. Error

Prediction (%)

Polynomial [14]

- Polynomial

High-Speed CMOS

OTA, 13 inputs and 6

outputs

1-4min./ <10min

Matlab 82,6

Posynomial [13]

2002 Posynomial 1-4min./ <10min

Matlab 61,7

CAFFEINE [11]

2005 Posynomial 12 hours /

<10min Matlab 22,7

FFNNs [15] 2002 Neural

Networks

3,7 min / <10min

Matlab 41,7

Boosted FFNN [16]

2002 Neural

Networks SPICE

7 min. / < 10min

Matlab 43,2

MARS [12] 1991 Polynomial 5 min. / <

10min Matlab 29,4

LS-SVM [17] 2002 Support Vector

Machine

5 min. / < 10min

Matlab 45,9

Kriging [18] 1998 GeoStatistics 5 min. / <

10min Matlab 34,6

2.3.2 Choice of the model approach

The results of Table 2.4 present a real motivation for the mode-based optimization. The opportunity to

create a new and innovative model with a good performance of accuracy and time setup arises. Once

again it is emphasized the tradeoff existent between the complexity/accuracy and time setup of such

models. The expected result by creating a model is to optimize the sizing process by achieving

satisfactory solutions in less number of simulations, as the study has proved before to be possible. For

this work is predictable to acquire the simple knowledge of a designer in analog ICs by embedding

statistical knowledge into the evolutionary optimization kernel to improve the automation sizing cycle.

However, this knowledge must fall into a simple process not to compromise the goal of having a low

setup time. So, the methodology adopted is to automatically generate a Gradient Model, using a

Design of Experiments approach with two alternatives strategies, the Full Factorial Design or the

Fractional Factorial Design, which defines the samples from the design space that will be accurately

evaluated using electrical simulator HSPICE®, then, extract and rank the contributions of each design

variable to each design performance or objective, and finally, build the model based on a series of

gradient rules.

2.4 Conclusions

This chapter presented a number of techniques and approaches to the problem of analog circuit

sizing. Of all the approaches presented was possible to identify different advantages and drawbacks of

them. It has been shown the several classifications in terms of techniques used and the appropriate

Page 35: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

17

characteristics of each approach. It can be stated that in the field of analog circuits, the choice of

different approaches can have significant impact on the obtained solution to the problem taken into

account. The most significant impact observed of the different approaches was the setup and the

execution time, as well as the accuracy of the solutions.

The automation of circuit sizing (Figure 2.4) specifically the optimizer algorithm, seeks to make the

sizing automation more efficient and robust for all types of circuits, from the simplest to the most

complex analog circuits.

Topology

Selection

Automatic Circuit Sizing

Schematic

Netlist

SimulationOptimization

Algorithm

Layout

Synthesis

Figure 2.4 – Automatic Circuit Sizing.

Although much has already been achieved in the automatic design of analog circuits, the reality is that

these tools are not yet used in industrial design environment. In this research were presented several

ADA tools and analyzed to better understand the advantages and disadvantages that can be improved

in the future.

Despite that the creation of simple models automatically with knowledge of the circuits under study is a

huge challenge, is credible that these models bring improvements to the optimizer algorithm.

For this work it is intended to create a model that has as starting point the sampling of circuits through

the technique most used for this type of problem, Design of Experiments (DOE). After that, a statistical

study of the sampling performed will be realized in order to withdraw the main effects of the inputs on

the outputs. Identified the effect of inputs on the outputs, a refinement is accomplished through the

DOE. Finally, the model is extracted and integrated into the synthesis tool AIDA that will be properly

presented on Chapter 4.

Page 36: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

18

Page 37: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

19

Chapter 3 Gradient Model Generation

This chapter seeks to illustrate the automatic generation of the Gradient Model based on the DOE

technique to sample a circuit through the range of optimization variables. Then, the methodology

implemented for extracting the Gradient Model is presented.

3.1 Overview of Design of Experiments (DOE)

DOE is a highly used technique, as suggested in [78], to project and study the effects on the output (or

response variables), by varying the input (or factors). Moreover, using this technique it is possible to

make a statistical study of the output responses with a low cost, i.e., less computational time.

According to [79], the steps for development of the DOE are:

1. Characterization of the problem;

2. Selection of the response variables;

3. Choice of factor, levels, and ranges;

4. Choice of experimental design;

5. Conducting the experiment;

6. Statistical analysis of the data;

7. Conclusions and recommendations.

The purpose of using DOE is to extract the maximum amount of information of the system with the

smallest number of runs. Here, with DOE the influence of the inputs on outputs will be studied in order

to enhance the process of automatically generate the sizing of a circuit based on NSGA-II kernel.

The first step towards the use of a sampling technique is to recognize and describe the problem to be

tested and know what the objectives of this experiment. In this case, the problem to be tested is the

input of an electrical circuit and the objective of this experiment is the automatic generation of model.

In the next step of the DOE, it is necessary to select which output parameters are relevant, due to a

variation of the input. The output parameters and the ranges are provided by the user through a netlist.

The choice of factor and levels are placed and changed in the program by the user. Note that step 2

and 3 can be done simultaneously, or in the reverse order. The selection of factor and levels must take

into account the following equation (3.1) to construct the DOE’s matrix.

(3.1)

Page 38: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

20

The number of non-elementary variables corresponds to the variables which don’t have all the

possible combinations of sampling with the others variables. The number of input variables

corresponds to all the variables defined by the designer as variables for sizing optimization.

Analogously, to the non-elementary variables the elementary variables correspond to the variables

which have in DOE’s matrix all the sampling combinations between them in DOE’s matrix.

The base matrix corresponds to the number of range samples of input variables. Finally, the number of

simulations is defined by all the possible combinations of sampling between the elementary variables.

There is a trade-off between the base matrix and the number of elementary variable with the number

of simulations. On the one hand, the increase of the base matrix and the number of elementary

variables produces a more robust experience, on the other hand increases the cost of computing time

by increasing the number of simulations carried out. Later will be studied the effect of variation of the

base and the number of elementary variables in the DOE’s matrix (by the number of simulations /

computation time and the extraction of models).

In this model, the samples will only be performed through the Full Factorial Design and Fractional

Factorial Design. Other types of experiment design most commonly used are:

The Latin Square Design [79];

The Graeco-Latin Square Design [79];

In summary, and no matter the model used, it is intended to create a DOE’s matrix for an evaluation of

the output and input variables, for further creation of the optimizer model. This process will be

exemplified later for the Factorial and Fractional Design. For reasons purely visual, only levels of 2 will

be experienced on the DOE’s matrix base and for three inputs and two outputs. These numbers can

be increased, but the DOE matrix for simulation is broken into 1024 points each time for reasons of

interface with HSPICE® [7], also the heap of Java is a limitation in terms of DOE’s matrix size.

3.2 Design of Experiments with Full Factorial Design

3.1.1. Step 1 - Characterization and construction of the matrix DOE

From the steps presented in the last section for development of DOE, this step 1 will address the

characterization of the problem by the presentation of an electrical schematic. The selection of the

response will be defined by the outputs of this circuit. Choice of factor, levels, and ranges are also

presented in this step by the presentation of the input variables of the circuit, their respective ranges

and the number of levels used for sampling the range. This step serves also to select the type of

experimental design used, initially, will be used the Full Factorial Design. Finally, the experiment will

be conducted.

Page 39: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

21

For example considers the circuit differential amplifier, as shown in Figure 3.1, with three input

variables and two outputs. The circuit simulation was done using HSPICE® [7]. The ranges used for

the input variables are provided by the user through a netlist, and are as shown in Table 3.1.

M1

Ibias

Vdd

Vin

VCM

CloadM2

M3 M4

Vout

Figure 3.1 - Differential Amplifier.

Table 3.1 - Range of input variables.

Inputs Minimum Range Maximum Range

W1 (m)

W2 (m)

IBias (A)

The output variables also provided by the user through a netlist (Table 3.2):

Table 3.2 - Objectives and design constraints.

Outputs Objective

DC Gain [dB]

GBW [Hz]

Sampling these ranges with the DOE’s technique implies to perform an association between the

values of range and the levels to construct the DOE’s matrix. These ranges can be changed by the

user, which will change the values associated with the level. For this example, two points in the range

are considered, i.e., the DOE’s matrix base will have a value of two. The two levels are defined as

minimum and high, described by 0 and 1 respectively. The range is divided into two equal parts. In

each of these parts the level 0 is associated to the half of the lower half and level 1 to the half of the

upper half. For better understanding, this process is illustrated in Figure 3.2. This kind of design is

called the factorial design. In accordance with D. C. Montgomery [79], it is highly used in factor

screening experiments, especially in systems where the response is approximately linear with the

range of the factors. It is also a more simplified and fast design for a brief study of a system.

Page 40: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

22

Minimum Range

Maximum Range

Half of the lower half of

the range

Half of the upper half of

the range

Level 0 Level 1

Figure 3.2 – Association between Range and DOE’s Levels.

In the full fractional DOE the circuit is sampled in all the combinations of variables’ values. For each

variable (xi), B logic levels are defined, and to each value, it is assigned a value vi,b derived from the

variable’s range according to (3.2):

(3.2)

In Table 3.3 the mapping between logic values and variable values is illustrated for the simple

differential amplifier introduced previously, when B is set to 2.

Table 3.3 - Variables with their values for each level of the DOE.

Variables \ Levels 0 1

x1-W1 (m)

x2-W2 (m)

x3-1IBias (A)

Once the variables mapping is complete, the next step is to construct the DOE’s matrix. The matrix

has one line per each possible combination of values, being the total number of lines given by (3.1),

where p is 0. The columns are the inputs (x), identified with the logic levels, and the outputs (y)

described by the measured value. The concatenation of the values in the inputs is also referred as the

code of the sample, as it acts as unique identifier. Table 3.4 shows the 8 ( ) sample matrix, obtained

for the simple differential amplifier example. From the observation of the matrix, it can be seen that

simulation 2 does not have values in the outputs. This situation occurs when HSPICE® cannot

simulate the circuit, e.g. the simulation is not convergent for that set of input parameters. All vectors

which produce an output that is not measurable are not taken into consideration during the

generations of the model.

For a better observation of space exploration performed through the DOE’s matrix, the hypercube is

represented in Figure 3.3 to the output DC Gain, however, this may be extrapolate to any other output.

As can be seen through the hypercube, the greater the number of levels used in the DOE, the greater

the search space; however, it must take into account the tradeoff between search space and the

execution time.

Page 41: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

23

Table 3.4 - DOE’s matrix resultant for Full Factorial ( ), and their output.

x1-W1 (level) x2-W2 (level) x3-IBias (level) y1-DC Gain [dB] y2-GBW [MHz]

1 0 0 0

2 1 0 0

3 0 1 0

4 1 1 0

5 0 0 1

6 1 0 1

7 0 1 1

8 1 1 1

W1

IBias

W2

0 [dB]

W1 – Level 0; W2 – Level 0;

Ibias – Level 1.

46,46 [dB]

W1 – Level 0; W2 – Level 1;

Ibias – Level 1.

57 [dB]

W1 – Level 0; W2 – Level 0;

Ibias – Level 0.

32,62 [dB]

W1 – Level 0; W2 – Level 1;

Ibias – Level 0.

0 [dB]

W1 – Level 1; W2 – Level 0;

Ibias – Level 1.

46 [dB]

W1 – Level 1; W2 – Level 1;

Ibias – Level 1.

44,37 [dB]

W1 – Level 1; W2 – Level 0;

Ibias – Level 0.

31,13 [dB]

W1 – Level 1; W2 – Level 1;

Ibias – Level 0.

Figure 3.3 – Full Factorial ( ) in hypercube, for DC Gain.

3.1.2. Step 2 - Evaluation of the DOE’s matrix

This step 2 presents the statistical analysis of the experiment conducted in the previous step and the

conclusions obtained from it. After constructed the DOE’s matrix with the respective output values

simulated by HSPICE®, it is necessary to evaluate the effects of input variables on the outputs. This

process is called the main effect of the input in the output.

Page 42: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

24

The analysis of the data obtained in the DOE’s matrix, by calculating the main effect, it is intended to

understand which variables effects most to the outputs. This conclusion is reached through the highest

values obtained in module in main effect. The main effect is the effect of one independent (input)

variable on the dependent (output) variable, ignoring the effects of all other independent variables.

This calculation is one of the most important points due to its utilization on the generation of Gradient

Model. The Main Effect calculation is performed through (3.3) where mi,j, is the main effect of input

variable i in the output variable j, where k identifies the sample.

{

⁄ (3.3)

When the total Main Effect of an input variable is positive/negative, this is an indication that if the value

of that input variable is increased, the value of the output will tend to increase/decrease.

For the differential amplifier, Table 3.5 shows the main effects of the input variables to the outputs (DC

Gain and GBW) for the fully factorial DOE.

Table 3.5 - Main Effect obtained from the Full Factorial DOE matrix.

Input (xi) Calculation of the Main Effect to DC Gain mi,1

W1 (x1) ( – ( ) 23,13

W2 (x2) ( ) – ( ) 89,51

IBias (x3) ( ) – ( ) 61,35

Input (xi) Calculation of the Main Effect to GBW mi,2

W1 (x1) ( ) – ( ) 40,91

W2 (x2) ( ) – ( ) 49,29

IBias (x3) ( – ( ) 25,19

Table 3.5 shows that all the variables have positive contributions to the output, which means that

increasing their values may produce an increase in these objectives. However, for the DC Gain and

GBW the input variable that gives more certain about his contribution his W2.

3.3 Design of Experiments with Fractional Factorial Design ( )

With the increase of the number of input variables, the number of simulations for the Full Factorial

Design of Experiments increases exponentially (seen in (3.1)), which, as mentioned previously,

increases the time to complete the whole process of DOE. To reduce this effect, the fractional factorial

DOE introduces the notion of non-elementary variable, as a variable that is not used to generate the

Page 43: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

25

code of the sample, reducing the size of the matrix. The level of the non-elementary variables is

determined from the code, i.e. from the levels of the elementary ones.

3.3.1 Step 1 – Characterization and construction of the matrix DOE

Fractional Factorial Design corresponds to increase the non-elementary variables in the construction

of the matrix DOE, i.e., p > 0. Using p = 1, with B = 2 is obtained simulations. The number of

simulations decreases by half in comparison with Full Factorial Design studied above. For the simple

circuit in study the reduction in the number of simulations is irrelevant. However, it serves as a

demonstration for future use in more complex circuits. As an example, it will be used the variable IBias

as a non-elementary variable. It passes to the following status:

For the two elementary variables his logical values will be constructed analogously to the Full Factorial

Design. The non-elementary variables can be computed through several methods available in the

literature, in this work the level Lni of the non-elementary variable i is given by:

(3.4)

where % is the modulo operator and L1 and L2 are the levels of the first and second elementary

variables, which ensures an even distribution in the levels. For this example are obtained the following

results:

Table 3.6 shows the 4 ( ) sample matrix, obtained for the simple differential amplifier example by

considering the variable IBias as a non-elementary variable.

Table 3.6 – DOE’s matrix constructed with the design: Fractional Factorial.

x1-W1 (level) x2-W2 (level) x3-IBias (level) y1-DC Gain

[dB] y2-GBW [MHz]

1 0 0 0 1,7 0,34

2 1 0 1 30,56 10,24

3 0 1 1 31,13 12,18

4 1 1 0 56,46 20,34

Page 44: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

26

3.3.2 Step 2 – Evaluation of the DOE’s matrix

After the construction of DOE’s matrix, the next step is to perform the statistical analyze of their data.

This statistical study is made through the calculation of the main effect as performed in section 3.1.2.

In Table 3.7 is shown the main effects obtained from the fractional factorial DOE matrix. The analysis

of Table 3.5 and Table 3.7 shows all variables having a positive effect in the output, due to its highest

absolute value in both cases; W2 is the input variable that gives more certainty in its effect towards

both outputs.

Table 3.7 – Main Effect contributions of the input variables to DC Gain.

Input (xi) Calculation of the Main Effect mi,2

W1 (x1) – 54,19

W2 (x2) – 55,13

IBias (x3) – ( ) 3,53

Input (xi) Calculation of the Main Effect mi,2

W1 (x1) – ( ) 18,06

W2 (x2) ) – 21,94

IBias (x3) – ( ) 1,74

Observing the tables of Main Effects for both DOE strategies it is concluded that both strategies have

concordant directions.

3.4 Extraction of the Gradient Model from DOE

This section will be the connection point between the sampling, its statistical analyses and the

extraction of the model to be integrated into the optimizer. The steps for the extraction of the Gradient

Model presented below are totally different from the steps presented for the DOE.

3.4.1 Step 1 – Maximum and minimum values of outputs

The first point to be made in the extraction of the model is the verification of maximum and minimum

values of each of the outputs obtained in the DOE’s matrix. This operation is performed by the

methods getOutputsMax(); and getOutputsMin(), as the name suggests the first method returns the

maximum values of outputs and the second the minimum values generated by the matrix. Both values

are stored in two objects: max and min, respectively, for later use in defining a gradient for the output

variables.

Page 45: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

27

3.4.2 Step 2 – Variables with the greatest Main Effect on each output

As a second step, the designer indicates hardcoded the number of input variables (represented by N)

that want the model to be created for each of the outputs, through the method getContributionMax(N);

This method follows the pseudo-code of Figure 3.4:

Contribution_Max = 0;

for (each Output) {

for (each N contribution)

if (Main_Effect[Input][Output] greater or equal than Contribution_Max)

add Main_Effect[Input][Output] as maximum;

}

Return the inputs with the greatest Main_Effect of the output;

Figure 3.4 – Pseudo-code of getContributionMax(N).

Thus by this method is obtained the N’s inputs variables that have the greatest affect (either positive or

negative) for each output.

3.4.3 Step 3 – Generation of the Model

For the generation of the model is desired to assign a direction for both inputs and outputs, i.e., obtain

gradients of inputs direction, to get the response desired on the output. The knowledge about the

gradient of input variables and their respective response effect on the outputs, it is the final product

desired to be introduced in the kernel optimizer and then obtain better results with this addition.

Once the main effects are computed, the N input variables that have larger contributions to each

output are identified by having the large absolute value of the contribution. Then a refinement

procedure is executed. For each output variable , a new DOE matrix is constructed using the

fractional factorial sampling, with the N input variables that have the larger contributions as the only

elementary variables. The refinement DOE matrix is then converted to the set of gradient rules for that

output variable. This is done by discarding the columns referring to non-elementary variables and

transforming the levels of the elementary variables into input gradient symbols according to:

{

⁄ (3.5)

where k identifies the line of the matrix. The output gradient symbols So are converted from the output

values as:

{

( )

(3.6)

Page 46: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

28

where and

are respectively the maximum and minimum values of the output obtained in

the DOE matrix (not the refinement matrix), and is |

| ⁄ . The meanings of the symbols

are: (-) a decrease; (+) increase and (U) undefined.

Table 3.8 and Table 3.9 illustrate the extraction of Gradient Rules process.

Table 3.8 – Extraction of Gradient Rules for GBW.

(Symbol)

= 0,34

17,03 8,67

: (-)

= 10,24 : (U)

= 12,18 : (U)

= 20,34 : (+)

Table 3.9 - Set of Gradient Rules for GBW.

K Si1,2-W1 Si2,2-W2 So2-GBW

1 (-) (-) (-)

2 (+) (-) (U)

3 (-) (+) (U)

4 (+) (+) (+)

From the example of Table 3.9 some conclusions can be drawn. Of rules 2 and 3 it is apparent that

these do not give information of a set gradient for the output, thus these rules can be practically ruled

out. Already for rules 1 and 4, these show us a well-defined gradient for the output. Of the rule 1 is

concluded that should be invoked when one intendeds to decrease/minimize the value of this output,

for having the gradient symbol (-). In the same rule is observed that the value of the 1st variable should

be decreased as the value of the 2nd

variable should be decreased. Similarly, the rule number 4 should

be applied to increase/maximize the output value, since it has the gradient symbol (+). To this end, the

model tells that the value of the 1st variable and the 2

nd variable should be increased.

Figure 3.5 summarizes the correspondence between the gradient symbols and the directions of the

output variables.

Page 47: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

29

If the Output variable

has:

Gradient Level:

‘Undefined’

Gradient Level:

(+)

Gradient Level:

(-)

Maximize the

Output

Undefined

direction

Minimize the

Output

Figure 3.5 – Summary of the directions of the output variables.

For technical detail and better understanding of the Gradient Model generation the pseudo-code is

presented in Figure 3.6.

Vector Rules;

Delta;

getOutputsMax();

getOutputsMin():

for (each Output) {

Define the Delta for the Output;

getContributionMax(N); //Returns the inputs with the greatest Main_Effect of the output

Set those inputs as elementary variables;

DOEMatrix.Fractional();

for (each DOEPoint)

for (each Input)

Set gradient symbol for the input in Rules;

If (getOutput.getValue <= min.getOutput.getValue + delta)

Set “(-)” for the output in vector Rules;

If (getOutput.getValue > min.getOutput.getValue + delta &&

getOutput.getValue < max.getOutput.getValue - delta)

Set “Undefined” for the output in vector Rules;

If (getOutput.getValue >= max.getOutput.getValue - delta)

Set “(+)” for the output in vector Rules;

}

Return Rules;

Figure 3.6 – Pseudo-code for the generation of the model.

3.5 Conclusions

In this chapter two different techniques were demonstrated for extraction of knowledge for analog ICs

through the use of samples. The techniques shown were the Full Factorial Design and Fractional

Factorial Design, and Table 3.10 presents an overview of these both techniques. Additionally, the

calculation of the effect of the input variables on the output using the DOE’s matrix was also

presented. As stated previously, this calculation is extremely important in the extraction of the model,

since it is the main indicator of the variables that most contribute to the change of outputs as well as

their gradients. Then, after the sampling process and its statistical study, the extraction of the Gradient

Page 48: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

30

Model step-by-step was presented. A refinement to the variables with greater main effect was carried

out in order to obtain a more accurate model for these variables. Finally, it was explained how to

generate the gradients for the input and output variables obtained by the DOE’s matrix of refining.

Thus, through this model is intended to include in the optimization kernel to be obtain a better

performance in the genetic algorithm (better performance shall mean obtaining better solutions faster

than without the model and even to increase the search space of the objectives).

Table 3.10 – Overview of designs: Full Factorial and Fractional Factorial

Design Full Factorial Fractional Factorial

Advantages

- Robust study of circuits;

- Considerer all variables of the circuit as

elementary.

- Runtime lower;

- Convenient for an early

draft of the circuit.

Disadvantages

- High cost of computational resources

(for complex circuits);

- High runtime (for complex circuits).

- Lower accuracy in the study

of circuits;

- Difficulty in determining;

which variables are non-

elementary.

Page 49: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

31

Chapter 4 Enhanced AIDA’s Circuit-Level Optimization Kernel

This chapter explains how the Gradient Model described in the previous chapter is used to enhance

the circuit-level optimization tool, GENOM-POF. GENOM-POF is part of the Analog Integrated circuit

Design Automation environment (AIDA), developed in the Instituto de Telecomunicações. The

integration of the gradient model includes both embedding the model in the optimization kernel, and

add the model’s setup options to AIDA’s graphical user interface (GUI), which assures the visualization

of the results and the control of parameters such as the function objective, constraints and input

variables ranges of the circuit, is presented.

4.1 Architecture

The AIDA platform, whose architecture is shown in Figure 4.1, implements a fully automatic approach

from a circuit level specification to a physical layout description. AIDA monitors the implemented

design flow allowing the designer to intervene, e.g., by stopping the synthesis process whenever an

acceptable solution is already present or by selecting the solution to be integrated from a Pareto set of

optimally sized circuits.

A I D A

DESIGN KIT

Module Generator

Desing Rules

LAYGEN II

Layout Generation

DESIGN

Specs.

DATABASE

TopologyTemplate

Extraction

GENOM_POF

Circuit-LevelSynthesis

VALIDATION

RE-D

ESIG

N

Figure 4.1 – AIDA Architecture.

The analog ICs project supported by AIDA consists in two major phases. The first one is the

specification translation or circuit sizing at circuit-level, where the size of the devices is determined in

such way that the circuit fulfills the specifications. In AIDA this task is done by the circuit-level sizing

tool GENOM-POF. The second phase of the flow is the physical implementation of the devices

Page 50: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

32

constrained to the technology design rules, which is done in AIDA by LAYGEN II. Following the

automatic generation the design must be validated (after extraction).

For this work, GENOM-POF is the tool where the contributions will be made. GENOM-POF, whose

architecture is shown in Figure 4.2, uses an optimization kernel based on the multi-objective

evolutionary algorithm NSGA-II and uses the commercial electrical simulator HSPICE® to evaluate the

performance of the design. Although GENOM-POF allows the inclusion of corner cases during

optimization, this does not fall within the scope of this thesis, and is not addressed. The architecture of

the GENOM-POF integrated with the developed Gradient Model is shown in Figure 4.3.

OUTPUTS

Ele

ctr

ica

l S

imu

lato

r

Sized Circuits

POF

INPUTS DESIGN STRATEGIES NSGA2

KERNEL

Co

rner

s

Corner POF

Typ

icalCircuit

TestbenchSpecs

fm(x)

gP/F

i(x)

X(random)

fm(x)

gP/F

i(x)

Typical POF

HSP

ICE®

Figure 4.2 – GENOM-POF Architecture.

NSGA-II

KERNEL

Circuit Sizing

CORNERSTYPICAL

{X, F(x), G(x)}

OUTPUTS

Sized Circuits

POF

INPUTS

Targets &Constraints

Template

Circuit &Testbench

HSPICE®

Electrical Simulator

LAYGEN-II

Layout Estimator

evalu

ation

opera

tors

CROSSOVER

MUTATION

Enhanced Operators

Gradient Model

Figure 4.3 – GENOM-POF architecture with the integrated Gradient Model.

As inputs, GENOM-POF receives the circuit netlist and test-bench. These two files, provided by

designer match to: the circuit description, the definition of the variables for optimization and the

objectives and constraints of the design. The circuit is then modeled as an optimization problem

suitable to be optimized by the NSGA-II kernel. As show in Figure 4.3, the inclusion of the model aims

Page 51: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

33

that during the optimization process the variable sometimes have a direction defined by the model.

With this new feature, it is intended that the GENOM-POF optimization process is achieved faster.

The output is a set of Pareto Optimal Fronts (POFs) with different sizing solutions, presenting the

tradeoff between the objectives being optimized. From these outputs, the designer selects the ones to

be used in the automatic layout generator tool, LAYGEN II, where the physical design is executed.

In the following sections, a single-ended folded cascode operational amplifier will be considered to

illustrate the automatic design flow and interfacing.

4.1.1 Inputs

The inputs are provided by the designer, and consist in the netlist of the circuit and test-benches in the

format of HSPICE®. This netlist should contain both the parameterization of the optimization variables

and the performance measurement statements. Figure 4.4 presents the working example, a single-

ended folded cascode OpAmp.

M1

Vdd

Vbp

Vbpc

inip

Vss

out

Vbnc

vb

M2

M4 M11M12

M9 M10

M7 M8

M5 M6

Figure 4.4 – Electrical schematic of the single-ended folded cascode amplifier.

The designer also has to define: the ranges of variables to optimize; the design constraints; and the

optimization objectives. Table 4.1 presents a possible configuration that the designer can introduce as

input for the addressed example.

Page 52: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

34

Table 4.1 - Range, objectives and design constraints example.

Variables: cn, cp, l1, l4, l5, l7, l9,

l11, ib, w1, w4, w5, w7, w9,

w11

Ranges:

0.18e-6 <= l* <= 5.0e-6

0.24e-6 <= w* <= 200.0e-6

30.0e-6 <= ib <= 400.0e-6

Objectives: min(area)

max(a0)

Constraints: gb >= 1.2e7

55 <= pm <= 90

In Table 4.1, the area represents the total area of the circuit in , a0 the DC Gain in dB, gb the gain-

bandwidth product in Hz and pm the phase margin in degrees.

4.1.2 Structure of the Optimization Kernel

GENOM-POF is based on the NSGA-II algorithm, modified to interface with the simulator HSPICE®.

The simulator performs the evaluation of each potential solution generated by the algorithm. The

reason why the NSGA-II was chosen over other multi-objective evolutionary algorithms was due to his

excellent characteristics to produce Pareto optimal fronts, as mentioned in [77]. Regarding the choice

of the simulator to evaluate the performance of the circuits, HSCPICE®, was chosen because of his

high accuracy in the results, despite having high execution time in simulations. The modified GENOM-

POF uses the same structure and the model will be integrated into the evolutionary operators

crossover and mutation, and, subsequently, analyzed on which operator are obtained the better

results. This integration of the model into the tool GENOM-POF and its interface with the designer will

be explained in detail later in this chapter.

The multi-objective optimization kernel was designed to solve the problem:

(4.1)

In (4.1), is a vector of N input variables to optimize, is a set of M objective functions which may

be desired to minimize or maximize, corresponds to the set of constraints to be met and finally

is the range defined by the designer for the variables to be optimized.

Thus the first step involves transforming the design problem in an optimization problem that may be

executed by the NSGA-II kernel optimization. For greater uniformity, the objectives that are intended to

minimize are directly sent to the kernel, while the objectives to maximize are first multiplied by -1, as

shown by equation (4.2). In turn, the design constraints are multiplied by -1 according the

normalization of equation (4.3).

Page 53: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

35

{

(4.2)

{

(

)

(4.3)

In equation (4.3) pj is the measured performance characteristic, and Pj is the corresponding acceptable

limit.

In order to illustrate and exemplify the mentioned normalization, Table 4.2 is presented for the circuit of

Figure 4.4 and for the desired specifications of Table 4.1.

Table 4.2 - and normalization example.

Objectives: f0(x) = -a0

f1(x) = area

Constraints:

Where the area represents the total area of the circuit in , a0 the DC Gain in dB, gb the gain-

bandwidth product in Hz and pm the phase margin in degrees.

4.1.3 Outputs

Finally, the output is a set of circuits with different sizing solutions, giving the designer the possibility to

choose the tradeoff that is most appropriate among the objectives to be optimized. Figure 4.5 presents

a possible POF of Figure 4.4 with several different sizing solutions, that the designer has the option to

choose, and then generate the respective layout.

This type of output has usually a huge variety of points of tradeoff between the objectives. This set of

sizing solutions allows the designer not only a chance to explore various solutions within the solution

space, and choose the one that is the most suitable, as allow the designer to save a huge time in the

execution of at least a draft of the project

Figure 4.5 have some points referenced in POF to be observable with practical values the tradeoff

between objectives. For every point in the POF, the respective values for the dimensions of each

device of the circuit are defined, and can be generated automatically their respective layouts through

Page 54: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

36

the tool, LAYGEN II. Despite being presented a POF with only two objectives, this is due solely to

visual issues, yet more objectives are easily supported.

Estimated Area = 6,241 um2

DC gain = 54,42 dB

Estimated Area = 10,124 um2

DC gain = 64, 231 dB

Estimated Area = 27,936 um2

DC gain = 72,813 dB

Pareto Front of Optimal

Sizing Solutions

Figure 4.5 – POF obtained during the sizing task.

4.2 Integration of the Gradient Model in the Optimization Kernel

The integration of the Gradient Model into GENOM-POF is done by embedding it in the crossover and

mutation evolutionary operators. Each element in the population, chromosome, encodes the

information of a different sizing solution, corresponding each gene to one input variable. So, each

chromosome has a fixed number of genes equal to the number of input variables present in the circuit.

L1W1 IBias W2 ... W11

Input variables of a circuit

Figure 4.6 – Abstract representation of the chromosome in the GA.

Page 55: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

37

Population

Chromossome 1

W1’ L1’ IBias’ W2’ ... W11’

Chromossome 2

W1’’ L1’’ IBias’’ W2’’ ... W11’’

Chromossome N

W1’’’ L1’’’ IBias’’’ W2’’’ ... W11’’’

. . .

Figure 4.7 – Abstract representation of the population in the GA.

As the traditional genetic algorithms (GA), the population is composed by several chromosomes; each

one differs from each other due to their different variables’ values. The genetic operators, crossover

and mutation, perform changes in the genes and chromosomes and, the chromosomes are

subsequently evaluated. Then, the chromosomes are organized in the population according to a

ranking, and that ranking is performed by a specific sorting process, in the current implementation is

used the Pareto dominance.

Figure 4.8 shows the evolution of the population in the GA. The GA starts with an initial random

population, and over this population is performed the crossover operation. The crossover operator

increases genetic variation in the population by generating new chromosome, this process is realized

by combining two chromosomes (parents) to produce new chromosomes (offsprings), as illustrated in

Figure 4.9. The idea is that the new chromosomes may correspond to better solutions than both of the

parents by taking the best characteristics from each of the parents. Crossover can be compared to

sexual reproduction in natural organisms which permits the swapping of information between

individuals.

Page 56: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

38

Chromossome

1

Chromossome

3

Chromossome

2

Chromossome

N

Final Population

Crossover

Operator

Combining and Sorting

Mutation

Operator

Chromossome 1

Chromossome 2

Chromossome 3

Chromossome N

Chromossome 2'

Chromossome N'

Chromossome

1

Chromossome

3

. . .. . .

. . .

Chromossome 1'

Chromossome 2'

Chromossome 3'

Chromossome N’

. . .

Offsprings

Chromossome

2

Chromossome

N

Chromossome 1'

Chromossome 3'

. . .

Chromossome 2'

Chromossome N'

Chromossome

1

Chromossome

3

. . .

Selection

Initial Population

Offsprings

Figure 4.8 – Evolution of the population in the GA.

Chromosome – Parent 1

Chromosome – Parent 2

Chromosome – Offspring 1

Chromosome – Offspring 2

Figure 4.9 – Crossover operation.

After, the mutation operator is performed on the offsprings created by the crossover. This operation

changes the value of one or more genes on the chromosome, as shown in Figure 4.10. The operator

mutation is performed in order to increase the genetic diversity in the population, and thus increases

the search space of the algorithm. The mutation rate corresponds to the number of genes change

through the mutation operator. Then, all chromosomes (parents and offsprings) are combined and

sorted. The final population is achieved by selecting the best chromossomes.

Chromosome – Affected

by the mutation

Mutation

Figure 4.10 – Mutation operation.

Page 57: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

39

This cycle (crossover plus sorting plus mutation) ends when the maximum number of generations

defined previously is reached. The implementation of these genetic operators, crossover and mutation,

is presented in the following subsections.

4.2.1 Gradient Model applied to the Crossover Operator

The first approach implemented for integration of the Gradient Model in the optimization kernel was by

applying the model before the crossover operator.

Introducing the Gradient Model over some genes the aim is to make the offsprings with greater

potential performance. However, over these offsprings the mutation operator will be applied which may

decrease this potentiality.

Chromosome – Parent 1

Chromosome – Parent 2

Chromosome – Offspring

Gradient Model

Figure 4.11 – Abstract representation of crossover operator integrated with the Gradient Model.

The Figure 4.11 exemplifies an abstract integration of the Gradient Model after the crossover. The

grey color represents the affection of the model on the chromosome, more precisely changing the

value of two genes.

Figure 4.12 exemplifies a possible application of the Gradient Model integrated in the crossover. After

the crossover operator conjugates the genes of Parent 1 and Parent 2 a new chromosome is produced

with probably better performance than the parents, and in that chromosome called Offspring the

Gradient Model insert is knowledge For the example presented in Figure 4.12, the Gradient Model

have two input gradient for a certain output, that gradient is to increase the value of W1 and IBias.

These variables are increased between 0% - 3% of their value, as mentioned by Change Ratio (for the

example was always applied 3%). The Change Ratio is one of the variables that designer have control

of the model, later in the subsection Graphical User Interface those variables will be explained in more

detail, but for now is appropriate to retain that Change Ratio is the maximum percentage to change the

variable value. It is important to note that after the application of the model the crossover operator will

still be applied, which could destroy the information embedded by the model in chromosomes.

Page 58: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

40

W1

210

W2

105

L1

0.35

L2

0.35

Ib

300

Offspring 1

W1

150

W2

115

L1

0.5

L2

0.4

Ib

200

Offspring 2

GRADIENT MODEL

Objective: max(GBW)

Rules: W1 W2 L1 L2 Ib

GBW,(+) (+)

A0,(-)

(+)

(+) (-)

Parameters: c = 0.03

Gradient Model

W1 W2

105

L1

0.35

L2

0.35

Ib

Offspring 1

W1 W2

115

L1

0.5

L2

0.4

Ib

Offspring 2

309216.3 206154.5

Figure 4.12 – Example of application of the Gradient Model in the crossover.

4.2.2 Gradient Model Applied to the Mutation Operator

Another approach to integrate the Gradient Model in the optimization kernel was to implement the

model after the mutation operator.

With this approach it was intended to drive chromosomes to optimal solution before the evaluation of

them and after the crossover operator performed. Through this approach it is expectable to not fall into

the same problem of applying the model in the crossover operator, which can drive chromosomes for

areas of optimization and then that direction be destroyed by the intervention of mutation operator.

The NSGA II kernel is an evolutionary optimization scheme that simulates natural evolution. It

operates over a population composed by several chromosomes, each representing a different

candidate solution. The genetic operators, crossover and mutation, are used to create new individuals

from the initial population (usually obtained randomly), the first, by combining the genetic information

from the parents, and the second by introducing random changes in the individual.

The new individuals’ fitness is evaluated and they are mixed with the parents and ranked. The fittest

individuals are selected as the new parents, and the less fit discarded. The process is repeated until

the ending criterion is reached (usually a fixed number of iterations). The distinguishing characteristic

of NSGA-II is that the ranking is made using Pareto dominance.

Page 59: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

41

In GENOM-POF the chromosome is represented by the vector of continuous variables

representing the design variables. To speed up the convergence of the algorithm, the knowledge

extracted into the gradient model is used to make the mutation operator more efficient.

The mutation operator in GENOM-POF uses the continuous valued operator introduced by Deb and

Goyal in [82]. In this operator, defined as

⁄ , where

and are the

mutated and original values respectively, is the mutation perturbation applied. is a random variable,

with values in the interval of -1 to 1, and p.d.f.:

| | (4.4)

where is a parameter used to control the spread of the distribution. Figure 4.13 shows the p.d.f. for

various values of

η = 0

η = 1

η = 5

δ

P(δ)

-1 10

1

0.5

3

Figure 4.13 – Probability distribution for creating a mutated value [82].

A factor of disturbance of can be obtained from an uniform random number using (4.4),

which is obtained from (4.5) by solving ∫

.

{

]

(4.5)

and the mutated value, , is given by

.The gradient rules are then applied.

The application of the rules follows the expression in (4.6):

( )

(4.6)

Page 60: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

42

where is the variable value after the application of the rule, is a function of the gradient

symbol defined in (4.7), and is a uniformly distributed random number between 0 and c, the

change rate model parameter.

{

(4.7)

The application of the gradient rules is conditioned to existence of a suitable rule for the optimization

targets, i.e. it is irrelevant to have a rule to decrease the gain, if the optimization target is to increase it.

The rules are selected by searching for each optimization objective if there is a rule that causes the

desired effect in the corresponding response variable. If this rule is found, then the variables with

larger contributions are affected as described before. Figure 4.14 shows an example of the application

a gradient rule.

W1

216.3

W2

105

L1

0.35

L2

0.35

Ib

309

Individual: after gradient model

W1

210

W2

105

L1

0.35

L2

0.35

Ib

300

Individual: after mutation

Gradient Model

GRADIENT MODEL

W1

(+)GBW,(+)

W2 L1 L2 Ib

(+)

A0,(-) (+) (-)

Rules:

Parameters: c = 0.03

Objective: max(GBW)

Figure 4.14 – Example of application of the Gradient Model in the mutation.

Once again, the example of Gradient Model indicates to increase the values of W1 and IBias, and with

a maximum percentage of changing the values of 3%. After the application of the model the

chromosome may have incorporated the knowledge necessary by the model to achieve faster the

optimal solution.

With the introduction of knowledge about the circuit over the genes, through the gradient, it is

expectable to reach sub-optimal solutions faster than the GENOM-POF without model, or even to

reach optimal solutions that the GENOM-POF cannot reach alone, because of the statistical

knowledge embedded in chromosomes through the Gradient Model. The Figure 4.15 presents an

example of application of mutation integrated with Gradient Model in the solutions search space.

Page 61: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

43

W1

W2

W3

Increase W3 (3%)

Increase W3 (1%)

Gradient Model:

Increase W3

(0% - 3%)

Resulting point

Mutation decrease W2

Resulting point

Mutation

increase W1

Figure 4.15 – Solutions search space for mutation integrated with Gradient Model.

4.3 Graphical User Interface (GUI)

The AIDA environment integrated with the Gradient Model, framework and GUI are implemented in

Java™ 1.6. This GUI provides a simple and fast way for the designer set the values of constraints and

the range of input variables, also through the GUI designer can set the type of optimization to be made

on objectives (maximize or minimize), and monitor the results at any stage of the evolutionary

generation.

Figure 4.16 presents the overview of the GUI. From this overview is already possible to identify in the

upper left the schematic of the circuit in use. Beneath the schematic are the options available to the

user for controlling the circuit, model and algorithm, which will be presented in detail in below. In the

upper right, a layout window is shown (only with placer), which is obtained through the solutions of the

POF.

Page 62: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

44

Figure 4.16 – AIDA GUI: Overview.

Figure 4.17 shows possible objectives (DC Gain and area) for a design, however, these can be

chosen by the designer through the GUI since they are defined in the netlist. Also, using the GUI the

designer can define the type of objective that is intended, maximize or minimize

Figure 4.17 – AIDA GUI: Objectives.

In Figure 4.18 is possible to verify several constraints of design and their respective objective value.

The values of these constraints and the type of constraint objective (>= or <=) can be easily changed.

Also, the constraints variables can be chosen from this interface since they are defined in the netlist.

Page 63: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

45

Figure 4.18 – AIDA GUI: Constraints.

The last two options of GUI presented allow the designer to make several studies for the same circuit,

by changing the values of the objectives and their constraints. However, the designer can also change

the search space for the optimization problem by changing the range of the input variables.

Figure 4.19 shows the several input variables for optimization of the circuit, and their respective

minimum and maximum range. The designer can change these ranges values to his own desire by

introducing those values in the GUI. When changing the minimum and/or maximum value of the

ranges will also change the search space. The search space for optimization of the input variables

reduces when the ranges of the variables decreases, as well as the search space increases with the

increasing of the ranges. The point to keep in mind is that with narrower search space to optimize the

algorithm tends to converge more rapidly to the few points of optimal solutions, while with a search

space higher the same algorithm will have more difficulty in achieving the various points of optimal

solution.

Page 64: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

46

Figure 4.19 AIDA GUI: Ranges of the input variables.

Figure 4.19 shows the several input variables for optimization of the circuit, and their respective

minimum and maximum range. The designer from the interface of Ranges can change these ranges to

his own desire by introducing the values in these GUI. By changing the minimum and/or maximum

value of the ranges also will change the search space. The search space for optimization of input

variables decreases with decreasing the ranges of the variables, as well as the search space

increases with increasing the ranges. The point to keep in mind is that with narrower search space to

optimize the algorithm tends to converge more rapidly to the few points of optimal solutions, while with

a search space higher the same algorithm will have more difficulty in achieving the various points of

optimal solution.

The GUI not only provides the necessary parameters of design for control of the circuit optimization.

Other options like the type of strategy to use or the possibility to use or not the Gradient Model are

included in GUI. Also for the designer is provided the control of the parameters of GA and Gradient

Model.

Page 65: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

47

Figure 4.20, presents firstly the type of strategy to be adopted for the optimization problem; however,

for this work the typical strategy is the only one in study. It is also provided the possibility for designer

to choose the use or not of the Gradient Model or the Random Model, which will be presented in the

next chapter together with the obtained results for comparison with Gradient Model. In case of choice

of Gradient Model or Random Model the designer has the control of the parameters: - apply rate,

which is the frequency/percentage of use of the model chosen in the optimizer; - change ratio is the

maximum percentage of change of the value of a variable.

Figure 4.20 – AIDA GUI: Strategy options, Gradient Model options and Typical Optimization options.

The last option presented in Figure 4.20 is the GA parameters, the mutation rate has influence on the

diversity in the population, population size is the number of individuals (chromosomes) in a population

participating in the evolutionary process, crossover rate defines the frequency/percentage of the

crossover operation which enables the evolutionary process to move towards, and finally the number

of generations corresponds to the number of execution cycles of the algorithm, the GA terminates

when the maximum number of generations has been produced.

4.4 Conclusions

This chapter introduced the architecture of the AIDA environment for the automatic synthesis of analog

integrated circuits. It was also explained the more specific architecture of GENOM-POF, which is the

tool for circuit sizing optimization, and respective alterations with the integration of Gradient Model in

this architecture. All the specifications like inputs, structure of the optimization kernel, design strategies

Page 66: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

48

and the outputs of this architecture were explained to properly detail the integration of the GENOM-

POF tool with the Gradient Model.

In the next section of this chapter it was introduced the integration of the model into the genetic

algorithm. This introduction started with detail of all the cycle of the GA and his genetic operators, the

crossover and mutation applied to the population. The focus was to maintain the operators since this

model is applied through crossover or mutation operator. In this way, it were presented and explained

the application of the model in crossover and mutation operator, and an example of application of the

model into each of the operators was shown, however, for the application of the model into the

crossover operator was identified one possible loss of information since the mutation operator is

applied after the crossover. So, if the Gradient Model is applied in mutation operator this issue may not

occur by being the last operator applied in each cycle generation of GA.

Finally this chapter introduced the graphical user interface and all its possibilities of interaction

between the designer and the tool AIDA. Through several figures were presented all the possibilities of

the control of design variables for a proper circuit sizing. It was explained how to set and configure the

objectives, constraints and ranges of the input variables of the circuit. But the GUI is not restricted to

the several options for the circuit, and the control options for the GA and Gradient Model were

presented. All the obtained results at any stage of the evolutionary generation may be presented in the

developed GUI, since black-box generators are not suited for multi-report facilities.

Page 67: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

49

Page 68: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

50

Chapter 5 Results

This chapter presents one case study exploring two different problems. The code was run, on an

Intel® Core™ 2 Quad CPU 2.4 GHz with 6 GB of RAM and with multi-threads to perform the

evaluation process of each population, at each generation.

5.1 POFs Analysis

In order to compare the GENOM-POF with the integrated solution Gradient Model (GENOM-POF +

Gradient Model), the performance analysis indicators will be here defined and described. Moreover, in

this study two objectives will be considered to illustrate the multi-objective optimization approach.

Beyond, the graphical component that will be displayed through the POFs, the conclusions will be

supported based on statistical analysis of results. With this in mind, the following terms are defined for

comparison between POFs:

Non-dominated area of the POF;

Number of points in the POF;

Standard deviation of points on the x axis;

Standard deviation of points on the y axis.

One of the strongest points in the analysis and comparison of POFs is the non-dominated area. First,

is important to realize what a solution of dominance is. The definition of dominance says that a solution

dominates (as shown in Figure 5.1) if both following conditions are true:

1) The solution is no worse than in all objectives.

2) The solution is strictly better than in at least one objective.

x1

x2

)(1

yf

)(2

yf

Figure 5.1 – Dominance solutions.

If any of the above conditions is violated the solution does not dominate the solution . For a given

set of solutions all possible pairwise comparison can be performed and find which solutions dominate

and which solutions are not dominated. Thus, the desired for a set of solutions such as the POFs is

that they have the smallest non-dominated area possible. The smaller the non-dominated area by a

POF the better the solutions points for the design objectives.

Page 69: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

51

In order to carry out an analysis and comparison quantitative and fairly among different POFs the

calculation of non-dominated area for each POF was performed as follows:

- The axis of the x’s and y’s was normalized for their respective maximum values with value 1,

for limiting the numerical integration of the dominated area;

- The dominated area (in Figure 5.2 defined by the area A) was calculated by the sum of

trapezoidal numerical integration defined in equation (5.1):

Area

h

A

1

1a b

Figure 5.2 – Trapezoidal numerical integration.

(5.1)

- The non-dominated area (in Figure 5.3 defined as area B) was defined as being .

Figure 5.3 – Illustration of non-dominated area.

Pareto Front of Optimal

Sizing Solution

A

B

1

1

Area

Area

Normalized

for the

greatest

value of area

No

rma

lize

d

for

the

gre

ate

st

va

lue

of g

ain

Page 70: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

52

Note that the ideal of a POF has a non-dominated area equal a zero.

Another point of comparison between POFs is the number of solutions points that each POF contains.

Finally, another important point in comparison different POFs are the standard deviation of points in

both axes. So this calculation is performed through the equation (5.2):

(5.2)

In (5.2), represents the total number of points in the POF and the mean of points. The mean is

calculated with the following equation:

(5.3)

5.2 Random Model

With the aim of creating a comparison with Gradient Model, another model was implemented, called

Random Model. This model consists of choosing n random variables, which n is defined by the user,

varying with a gradient also random. The advantage of introducing this model in GENOM-POF is the

increase of randomness in the algorithm (which means more diversity on population), and a possible

search for more solutions.

In Figure 5.4 the pseudo-code for Random Model is presented:

Random Model(apply rate, change rate)

for (each Output) {

if (apply rate greater than pseudo_random())

for (each variable defined by the user)

if (apply_rate greather than pseudo_random())

Decrease the value of the input with the change rate(%)

else

Increase the value of the input with the change rate(%)

}

Figure 5.4 – Pseudo-code for Random Model.

The constants Apply Rate and Change Ratio are both introduced by the designer through the

graphical interface and correspond, respectively, to the application rate of the model and the maximum

change percentage of the variable value.

5.3 Case Study I – Single-Ended Folded Cascode Amplifier

The circuit used to compare the GENOM-POF with GENOM-POF integrated with Gradient Model is a

single ended folded cascade amplifier. For this comparison the items required were the netlist and the

test-bench of the circuit. The amplifier schematic is presented in Figure 5.5.

Page 71: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

53

ip

In

Vbp

Vdd

Vss

Ib

Ibp=1.1Ib

Vac

Vip

Vbpc

Vbnc

Vb Vss Vbnc

out

Vbpc Vdd

W=W5L=L5M=M5

W=W5L=L5M=M5

W=W7L=L7M=M7

W=W7L=L7M=M7

W=W9L=L9M=M9

W=W9L=L9M=M9

M1

Vdd

Vbp

Vbpc

inip

Vss

out

Vbnc

vb

M2

M4M11 M12

M9 M10

M7 M8

M5 M6

W=W1L=L1M=M1

W=W1L=L1M=M1

W=W4L=L4M=M4

W=W11L=L11M=M11

W=W11L=L11M=M11

Amplifier

(b)

(a)

Figure 5.5 – Electrical schematic and test-bench of the single-ended folded cascode amplifier.

For this electrical schematic two different studies will be performed, the first for 15 input variables (15th

dimensional search space solutions), this corresponds to a large search space of solutions and the

second for 12 input variables (12th dimensional) which have a smaller search space of solutions. For

this case study, the UMC 0.13 µm technology is used. The results presented for the models under

study were all performed with their integration in the mutation operator (presented in section 4.2.2).

5.3.1 Case Study I for 15 input variables

The first case study performed was for the circuit presented in Figure 5.5 considering 15 input

optimization variables. Two objectives and both performance and functional constraints are defined in

Table 5.1. This optimization problem is performed for the GENOM-POF and the GENOM-POF

integrated with Gradient Model for the same conditions, for a fair analysis and comparison between

both.

5.3.2.1 GENOM-POF

Before proceeding the comparison between GENOM-POF and GENOM-POF + Gradient Model, was

performed a brief study to find the optimal mutation rate, for such was performed various tests for the

circuit and conditions defined above.

Page 72: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

54

As starting point, GENOM-POF was executed for a typical value of mutation rate for genetic algorithm,

i.e., mutation rate of 3%. The crossover rate, the number of elements in the population and the number

of generations were fixed to the values 90%, 128 and 2000, respectively. Others tests were made for a

mutation rate of 25%, 30% and 50%, however, the best mutation rate found was 30%. For visual

reasons only the POFs to a mutation rate of 3% (Figure 5.6) and 30% (Figure 5.7) are shown.

Observing both POFs is proved that mutation rate of 30% produces better solutions than mutation rate

of 3% for the same number of generations.

Table 5.1 – Range, objectives and constraints

Variables: cn, cp, l1, l4, l5, l7, l9, l11,

ib, w1, w4, w5, w7, w9, w11

Ranges: 0.18e-6 <= l* <= 5.0e-6

0.24e-6 <= w* <= 200.0e-6

-0.4 <= cn <= 0.0

0.0 <= cp <= 0.4

30.0e-6 <= ib <= 400.0e-6

Objectives: min(area)

max(a0)

Constraints: gb >= 1.2e7

a0 >= 80

55 <= pm <= 90

sr >= 1e7

ov_m(*) >= 30e-3

d_m(*) >= 1.2

osp >= 0.3

osn <= -0.3

(*) the constraints apply to:

M1, M4, M5, M7, M9 and M11

In Table 5.1, the optimization variables include the W’s and L’s of all transistors, the tension gate-

source ( ) of transistor M1 and M2, represented by cp and cn respectively, and the bias current. The

objectives for this case study are: - the area of the circuit; - the DC Gain (a0). The design constraints

defined are: - Gain-Bandwidth product (gb); - DC Gain (a0); - Phase Margin (pm); - Slew Rate (sr); -

Overdrive Tension (ov_m); - Delta Margins (d_m).

Page 73: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

55

Figure 5.6 – GENOM-POF with mutation rate: 3% and for 2000 generations.

Figure 5.7 – GENOM-POF with mutation rate: 30% and for 2000 generations.

Found the value to be used for mutation rate, the Figure 5.7 can now be used for comparison with the

GENOM-POF integrated with Gradient Model for the same conditions. Before testing GENOM-POF

integrated with Gradient Model, an exhaustive simulation of GENOM-POF was performed for 60.000

generations as shown in Figure 5.8, this figure can also be used for comparison with GENOM-POF +

Gradient Model besides the different number of generations.

Page 74: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

56

Figure 5.8 – GENOM-POF for 60000 generations.

5.3.2.2 GENOM-POF integrated with Gradient Model

For this example a Gradient Model was generated with a base of DOE’s matrix of two (B = 2) and for

one optimization variable for each objective with the greatest Main Effect. The Gradient Model

generated will affect all the objectives, one variable to each objective. The resulted Gradient Model for

both objectives is shown in Table 5.2 and Table 5.3.

Table 5.2 - Gradient generated for DC Gain (a0).

DC Gain (a0)

L9 Gradient (-) (-)

L9 Gradient (+) (+)

Table 5.3 - Gradient generated for area.

area

W11 Gradient (-) (-)

W11 Gradient (+) (+)

The Gradient Model generated presents a linear gradient for both objectives, i.e. for the desired

objective of maximization of DC Gain the model tells us to increase the value of the variable L9, and

for the minimization of area the model indicates to the algorithm to decrease the value of W11.

Page 75: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

57

The model automatically generated for this example took less than 5 minutes to be generated. This

model generated can be reused for the same electrical schematic and optimization variables but with

different values of constraints functions.

For the same conditions mentioned before (mutation rate of 3%, crossover rate of 90% and population

size of 128), the GENOM-POF integrated with Gradient Model was performed. However for the

Gradient Model is important to refer same specific parameters used, is the case of Apply Rate and

Change Ratio which were already explained in Chapter 4 in subsection Graphical User Interface. For

these parameters several tests were performed to find the best values, which were obtained the Apply

Rate of 50% and the Change Ratio of 3%. Once again these values do not mean that they are the best

for the optimization problem, however, the optimization of parameters for the GA and Gradient Model

does not fall in the objective of this work.

The POF obtained for these conditions are shown in Figure 5.9. For a first visualization is easily

observed that this figure presents better results than Figure 5.7. However, the discussion between the

models under study will be made in the next subsection.

Figure 5.9 – GENOM-POF + Gradient Model (Apply Rate = 50% and Change Ratio = 3%) for 2000 Generations.

5.3.2.3 Comparison of different optimization sizing

This subsection serves to compare the results of GENOM-POF, GENOM-POF integrated with

Gradient Model and with GENOM-POF integrated with Random Model. Through the presentation of

several POFs and statistical study is intended to achieve some conclusions about the models under

study. The main goal is to observe if for the same number of generations the Gradient Model achieves

better solutions than GENOM-POF alone.

The Figure 5.10 which joins the POFs from GENOM-POF for 2.000 generations, 4.000 generations,

60.000 generations and GENOM-POF + Gradient Model for 2.000 generations, it is concluded that

Page 76: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

58

GENOM-POF integrated with Gradient Model for 2.000 generations obtain better results than

GENOM-POF for 2.000 and 4.000 generations. GENOM-POF for 60.000 generations presents

generically better results than GENOM-POF integrated with Gradient Model for 2.000 generations,

however, GENOM-POF can’t reach the maximum DC Gain reached by GENOM-POF integrated with

Gradient Model. By this figure is concluded that GENOM-POF integrated with Gradient Model

achieves better solutions more quickly than the GENOM-POF for the same number of generations.

Figure 5.10 – GENOM-POF (60000 gen., 4000gen., 2000gen.) vs. GENOM-POF + Gradient Model (2000 gen.).

For 2.000 generations the time of optimization is approximately 30 minutes, for 4.000 generations the

time doubles, and for 60.000 generations the optimization process is approximately 900 minutes or 15

hours. GENOM-POF + Gradient Model for 2.000 generations show competitive results in comparison

with GENOM-POF for 60.000 generations. The integration of Gradient Model in GENOM-POF in this

case study represents a time saving of approximately 14 hours and 30 minutes for a designer.

Twenty different initial populations (20 seeds) were compared between GENOM-POF and GENOM-

POF + Gradient Model, presented in Figure 5.11. The mean of the twenty different seeds shows that

Gradient Model helps to accelerate the process of sizing optimization.

For comparison with GENOM-POF + Gradient Model, the Random Model was also performed as

shown in Figure 5.12. Random Model was performed with the same conditions as Gradient Model,

which means that was defined an Apply Rate of 50% and a Change Ratio of 3%. The parameters of

GA were also maintained, that is a Mutation Rate of 30%, Crossover Rate of 90%, Population Size of

128 and the Number of Generations of 2000.

Page 77: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

59

Figure 5.11 – 20 different initial populations for comparison between GENOM-POF and Gradient Model.

Figure 5.12 – Random Model for 20 different initial populations.

This simulation shows that the knowledge of the circuit integrated in GENOM-POF really benefits the

sizing optimization and was not a randomly improve.

However, all these conclusions were made only through graphical visualization. In order to represent

the results shown in quantitative terms and achieve conclusions based on numerical and statistical

analyze is presented the Table 5.4, Table 5.5 and Table 5.6. These tables present the followings

analysis:

Page 78: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

60

- Low Area(x, y): To minimize (area) is one of the objectives of this design, so the lowest area

reached is a parameter that a designer would take in consideration. These parameter is

represented by the axes (x, y), but the lowest area reached in each seed is the x’s values.

- Max DC Gain (x, y): The other objective of this design is to maximize (DC gain). These

parameter is also represented by the axes (x, y), but the greatest area reached in each seed is

the y’s values.

- Number of points in POF: This parameter as referred in the beginning of this chapter shows

the number of solutions reached in the last POF.

- Area B: Represents the non-dominated area for both objectives.

- Standard deviation of x and y and their product: These parameters aims to analyze the

deviation of solutions for each objective and to correlate this deviation for the two objectives

Page 79: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Table 5.4 – POFs (20 different seeds) analysis for GENOM-POF.

Population: 128 Mutation: 30% Crossover: 90% Nr. of Generations 2000

Run ID Nr.

Seed Low Area (x) Max DC Gain (y)

Nr. Points

POF Area: 1 -A = B

GENOM 0 (2.008e-09, -8.021e+01) (5.004E-9, -85.191) 63 0.435 1.523 1.278 1.947

GENOM 1 (2.038e-09, -8.017e+01) (4.670E-9, -85.445) 55 0.393 1.400 1.072 1.501

GENOM 2 (1.676e-09, -8.067e+01) (4.528E-9, -85.364) 48 0.390 1.383 1.185 1.640

GENOM 3 (2.079e-09, -8.000e+01) (5.994E-9, -85.268) 37 0.424 1.459 1.260 1.839

GENOM 4 (2.057e-09, -8.110e+01) (4.956E-9, -84.991) 45 0.446 1.670 1.436 2.399

GENOM 5 (2.173e-09, -8.012e+01) (4.062E-9, -84.633) 48 0.480 1.208 1.494 1.805

GENOM 6 (1.892e-09, -8.042e+01) (4.474E-9, -85.967) 61 0.330 0.994 1.191 1.185

GENOM 7 (2.336e-09, -8.054e+01) (6.569E-9, -84.437) 44 0.519 2.389 1.223 2.924

GENOM 8 (1.985e-09, -8.000e+01) (5.064E-9, -84.992) 49 0.452 1.677 1.148 1.927

GENOM 9 (1.885e-09, -8.016e+01) (6.396E-9, -85.855) 63 0.358 2.131 1.064 2.268

GENOM 10 (2.003e-09, -8.016e+01) (4.709E-9, -85.508) 69 0.391 1.455 0.973 1.417

GENOM 11 (2.188e-09, -8.023e+01) (4.815E-9, -85.401) 52 0.411 1.160 1.282 1.488

GENOM 12 (1.736e-09, -8.056e+01) (4.204E-9, -86.809) 47 0.231 1.302 0.837 1.091

GENOM 13 (2.087e-09, -8.006e+01) (3.971E-9, -85.527) 60 0.387 0.997 1.208 1.204

GENOM 14 (2.441e-09, -8.072e+01) (5.573E-9, -83.757) 46 0.599 1.769 1.405 2.486

GENOM 15 (2.411e-09, -8.063e+01) (4.587E-9, -84.039) 47 0.563 1.985 1.049 2.083

GENOM 16 (1.932e-09, -8.009e+01) (4.360E-9, -86.120) 59 0.322 1.123 1.000 1.123

GENOM 17 (2.252e-09, -8.023e+01) (6.263E-9, -84.905) 41 0.462 2.828 1.201 3.396

GENOM 18 (2.156e-09, -8.084e+01) (5.836E-9, -85.245) 51 0.428 1.432 1.329 1.904

GENOM 19 (2.304e-09, -8.076e+01) (4.963E-9, -84.480) 46 0.511 1.093 1.118 1.223

Mean

51.55 0.426 1.549 1.188 1.842

Standard

Deviation

8.438 0.085 0.479 0.163 0.621

60

Page 80: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Table 5.5 – POFs (20 different seeds) analysis for Gradient Model.

Run ID Nr.

Seed Low Area (x) Max DC Gain (y)

Nr. Points

POF Area: 1 -A = B

Gradient Model 0 (1.544e-09, -8.010e+01) (5.167E-9, -87.850) 85 0.134 1.346 1.172 1.578

Gradient Model 1 (1.483e-09, -8.078e+01) (6.724E-9, -87.485) 93 0.167 2.928 1.085 3.178

Gradient Model 2 (1.769e-09, -8.026e+01) (6.099E-9, -87.291) 60 0.199 1.699 1.131 1.922

Gradient Model 3 (1.426e-09, -8.018e+01) (6.881E-9, -87.202) 87 0.197 1.732 1.168 2.024

Gradient Model 4 (1.546e-09, -8.052e+01) (5.836E-9, -87.806) 120 0.130 1.311 1.084 1.422

Gradient Model 5 (1.697e-09, -8.003e+01) (7.573E-9, -86.701) 90 0.275 1.765 1.048 1.851

Gradient Model 6 (1.572e-09, -8.009e+01) (6.318E-9, -87.594) 101 0.170 1.655 1.194 1.977

Gradient Model 7 (1.735e-09, -8.087e+01) (6.337E-9, -87.666) 60 0.162 0.921 1.102 1.015

Gradient Model 8 (1.685e-09, -8.089e+01) (5.503E-9, -87.692) 87 0.157 0.985 1.231 1.214

Gradient Model 9 (1.430e-09, -8.054e+01) (5.139E-9, -87.796) 98 0.128 1.073 1.100 1.181

Gradient Model 10 (1.628e-09, -8.020e+01) (7.740E-9, -87.842) 80 0.128 1.817 1.507 2.739

Gradient Model 11 (1.596e-09, -8.005e+01) (6.493E-9, -88.070) 95 0.117 1.197 1.159 1.388

Gradient Model 12 (2.143e-09, -8.026e+01) (6.694E-9, -86.202) 82 0.350 2.042 1.206 2.465

Gradient Model 13 (1.920e-09, -8.094e+01) (5.758E-9, -87.707) 53 0.158 1.046 1.213 1.269

Gradient Model 14 (1.543e-09, -8.023e+01) (5.157E-9, -87.363) 58 0.179 1.077 0.923 0.995

Gradient Model 15 (1.689e-09, -8.001e+01) (4.298E-9, -86.466) 75 0.262 1.498 1.264 1.894

Gradient Model 16 (1.514e-09, -8.057e+01) (6.109E-9, -87.518) 88 0.166 1.455 1.187 1.728

Gradient Model 17 (1.733e-09, -8.001e+01) (8.231E-9, -87.734) 70 0.178 2.316 1.214 2.813

Gradient Model 18 (2.117e-09, -8.053e+01) (5.892E-9, -85.774) 86 0.389 1.450 1.226 1.779

Gradient Model 19 (2.257e-09, -8.026e+01) (5.647E-9, -86.300) 66 0.348 1.220 1.023 1.249

Mean

81.7 0.200 1.527 1.162 1.784

Standard

Deviation 16.799 0.081 0.496 0.116 0.619

61

Page 81: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Table 5.6 – POFs (20 different seeds) analysis for Random Model.

Run ID Nr.

Seed Low Area (x) Max DC Gain (y)

Nr. Points POF

Area: 1 -A = B

Random Model 0 (2.731e-09, -8.018e+01) (7.013E-9, -84.288) 98 0.482 1.604 1.093 1.755

Random Model 1 (2.311e-09, -8.002e+01) (1.024E-8, -84.459) 74 0.440 3.771 1.392 5.252

Random Model 2 (2.462e-09, -8.007e+01) (1.368E-8, -84.655) 92 0.459 2.589 1.326 3.435

Random Model 3 (2.192e-09, -8.032e+01) (6.049E-9, -84.226) 72 0.455 2.810 1.250 3.516

Random Model 4 (2.192e-09, -8.004e+01) (6.524E-9, -84.038) 106 0.489 2.508 1.610 4.038

Random Model 5 (2.023e-09, -8.023e+01) (5.523E-9, -84.451) 86 0.414 1.653 1.271 2.103

Random Model 6 (2.364e-09, -8.013e+01) (1.293E-8, -84.781) 73 0.423 3.354 1.346 4.517

Random Model 7 (1.846e-09, -8.011e+01) (4.031E-9, -84.421) 117 0.407 1.185 1.388 1.645

Random Model 8 (2.130e-09, -8.025e+01) (5.016E-9, -83.880) 93 0.484 2.205 1.046 2.308

Random Model 9 (1.902e-09, -8.003e+01) (5.264E-9, -83.906) 97 0.463 4.285 1.340 5.747

Random Model 10 (2.102e-09, -8.033e+01) (1.148E-8, -84.858) 91 0.416 2.639 1.196 3.1589

Random Model 11 (2.363e-09, -8.002e+01) (7.653E-9, -84.342) 119 0.480 1.740 1.325 2.308

Random Model 12 (1.875e-09, -8.009e+01) (3.999E-9, -84.207) 106 0.431 1.136 1.423 1.618

Random Model 13 (1.964e-09, -8.030e+01) (9.805E-9, -84.625) 100 0.420 3.173 1.275 4.048

Random Model 14 (2.435e-09, -8.003e+01) (9.161E-9, -84.390) 104 0.460 1.978 1.466 2.901

Random Model 15 (1.865e-09, -8.016e+01) (5.345E-9, -84.754) 98 0.475 2.032 1.159 2.355

Random Model 16 (2.285e-09, -8.014e+01) (7.038E-9, -84.086) 87 0.468 2.666 1.320 3.521

Random Model 17 (2.115e-09, -8.012e+01) (7.343E-9, -84.251) 67 0.454 2.459 1.221 3.003

Random Model 18 (2.526e-09, -8.004e+01) (5.703E-9, -83.725) 124 0.518 1.511 0.906 1.370

Random Model 19 (2.359e-09, -8.051e+01) (8.147E-9, -84.196) 72 0.467 3.592 1.260 4.529

Mean

93.8 0.455 2.444 1.281 3.156

Standard Deviation

16.516 0.029 0.873 0.155 1.253

62

Page 82: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

64

From the tables above is observable that GENOM-POF reaches a maximum DC Gain around 86.81

dB for the seed 12 and a minimum area around 1.7 nm in the seed 2. On other hand the Gradient

Model reaches the maximum DC Gain of 88.07 dB at seed 11 and the minimum area 1.43 nm in the

seed 3. Finally the Random Model achieves the maximum of 84.86 dB at seed 10 and the minimum

area 1.85 nm in the seed 7. However, it has to be taken in account that all these maximum and

minimum values are achieved in different seeds. So, the mean of non-dominated areas becomes a

strong point of comparison between different approaches. By the observation of the tables the

Gradient Model presents very good results in terms of non-dominated area by having the lowest areas.

Through the observation of the non-dominated area, the number of points in the POF and the standard

deviations it is concluded that Gradient Model performs significant improvements in GENOM-POF.

The Table 5.7 summarizes all that conclusions for the different models under study.

Table 5.7 – Comparison between the models under study and GENOM-POF.

Non-dominated

area Nr. Points POF

Gradient Model

Better than GENOM-POF

Better than GENOM-POF

Similar to GENOM-POF

Similar to GENOM-POF

Similar to GENOM-POF

Random Model

Worse than GENOM-POF

Better than GENOM-POF

Worse than GENOM-POF

Similar to GENOM-POF

Worse than GENOM-POF

As concluded before by the POFs presented and now by the numerical and statistical analyze, the

Gradient Model integrated in GENOM-POF proves to be a significant improvement in the sizing

optimization process.

5.3.2 Case Study I for 12 input variables

The circuit presented in Figure 5.5 but with the number of variables to optimize reduced, 12 input

variables are now studied. The variables removed are the bias current and the tensions of M1 and M2

but with the same objectives and constraints, which results the Table 5.8. With the reduction of

variables to optimize the search space of solutions is also strongly reduced. The main reason for this

study is to prove that for the worse case of GENOM-POF + Gradient Model, this does not becomes

worse than the GENOM-POF alone, and may even get better results.

Table 5.8 shows the changes performed in Table 5.1 to realize this new study for the same circuit.

Page 83: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

65

Table 5.8 – Variables, ranges, objectives and constraints.

Variables: l1, l4, l5, l7, l9, l11, w1, w4,

w5, w7, w9, w11

Ranges:

0.18e-6 <= l* <= 5.0e-6

0.24e-6 <= w* <= 200.0e-6

Objectives: min(area)

max(a0)

Constraints: gb >= 1.2e7

a0 >= 80

55 <= pm <= 90

sr >= 1e7

ov_m(*) >= 30e-3

d_m(*) >= 1.2

osp >= 0.3

osn <= -0.3

(*) the constraints apply to:

M1, M4, M5, M7, M9 and M11

5.3.2.1 GENOM-POF

Figure 5.13 presents GENOM-POF optimization performed with the mutation rate of 30%, crossover

rate of 90%, population size of 128, the number of generations of 2.000 for each seed and 20 different

seeds.

Figure 5.13 – GENOM-POF for single-ended folded cascode amplifier with 12 variables for optimization.

Through Figure 5.13 are already observable worse results than the Figure 5.7. This is due to the

reduction of input variables to optimize and the subsequent reduction of the search space of solutions.

Page 84: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

66

Figure 5.7 presented a DC Gain around the 85 dB and an area around the 2 nm, however, the Figure

5.13 presents a DC Gain around the 84 dB and an area around the 3 nm.

5.3.2.2 GENOM-POF Integrated with Gradient Model

The Gradient Model for this example was once again generated with a base of DOE’s matrix of two

and for the greatest Main Effect for each objective. The resulted Gradient Model generated for each

objective is shown in Table 5.9 and Table 5.10.

Table 5.9 – Gradient Model generated for DC Gain (a0).

DC Gain (a0)

L11 Gradient (-) (-)

L11 Gradient (+) (+)

Table 5.10 – Gradient Model generated for area.

area

W5 Gradient (-) (-)

W5 Gradient (+) (+)

Gradient model, took less than 5 minutes to be automatically generated.

Figure 5.14 shows the application of Gradient Model for the circuit under study and for 20 different

initial populations. This result was performed for an Apply Rate of 50% and a Change Ratio of 3%.

Figure 5.14 – Gradient Model for single-ended folded cascode amplifier with 12 variables for optimization.

Page 85: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

67

This result in comparison with the Gradient Model shown in Figure 5.9, presents a real deterioration of

the solutions. For this optimization the maximum DC Gain obtained is around the 84 dB and in Figure

5.9 was around 88 dB. Also for the area the solutions found are worse. Figure 5.14, shows areas

around the , already the Figure 5.9 presented areas around the 2 nm. All this deterioration of

results is explained with the fixed variables IBias, Vcn and Vcp, which drastically reduces the search

space solutions for optimization

Despite the results for GENOM-POF and for Gradient Model are worse than for 15 variables of

optimization, a comparison between both still make sense to be performed.

5.3.2.3 Comparison of different optimization sizing

Before the comparison between GENOM-POF and Gradient Model it is important to refer that Random

Model is not presented in this subsection due to is similarity of results with GENOM-POF. The first way

to compare GENOM-POF and Gradient Model is performed by their POFs. Figure 5.15 shows the

connection of both POFs in the same figure. Through this figure significant improvements are not

easily seen, the results of the POFs seems very similarly between GENOM-POF and Gradient Model.

Figure 5.15 – Comparison between GENOM-POF and GENOM-POF + Gradient Model.

Besides the visual graphics of POFs does not permit any conclusion about the improvement or not of

Gradient Model the numerical and statistical study for analyze of POFs, presented in the previous

section is performed in this section again, with the goal of achieve some conclusions based on this

analyze. Table 5.11 and Table 5.12 show the analyses performed for GENOM-POF and Gradient

Model respectively. The subjects of analyses on both tables are the same subjects used in Table 5.4

and Table 5.5.

Page 86: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Table 5.11 – POFs (20 different seeds) analyses for GENOM-POF.

Population: 128 Mutation: 30% Crossover: 90% Nr. of Generations 2000

Run ID Nr.

Seed Low Area (x) Max DC Gain (y)

Nr.

Points POF Area: 1 -A = B

GENOM 0 (2.799e-09, -8.000e+01) (8.345E-9, -84.095) 129 0.287 1.297 0.638 0.828

GENOM 1 (2.688e-09, -8.004e+01) (5.342E-9, -82.798) 126 0.440 2.442 0.604 1.475

GENOM 2 (2.780e-09, -8.002e+01) (7.761E-9, -84.018) 128 0.302 1.231 0.716 0.882

GENOM 3 (2.688e-09, -8.003e+01) (9.084E-9, -84.254) 128 0.281 1.480 0.756 1.119

GENOM 4 (2.705e-09, -8.002e+01) (8.075E-9, -84.094) 130 0.283 1.522 0.667 1.015

GENOM 5 (2.626e-09, -8.000e+01) (6.478E-9, -83.457) 129 0.353 1.201 0.589 0.7083

GENOM 6 (2.624e-09, -8.001e+01) (7.320E-9, -83.798) 128 0.307 1.064 0.646 0.688

GENOM 7 (2.725e-09, -8.008e+01) (6.936E-9, -83.608) 128 0.328 1.859 0.743 1.383

GENOM 8 (2.648e-09, -8.006e+01) (8.021E-9, -84.089) 130 0.280 1.522 0.658 1.001

GENOM 9 (2.760e-09, -8.002e+01) (8.245E-9, -84.076) 127 0.295 1.139 0.711 0.811

GENOM 10 (2.735e-09, -8.019e+01) (6.924E-9, -83.674) 129 0.328 1.762 0.688 1.214

GENOM 11 (2.607e-09, -8.002e+01) (7.501E-9, -83.921) 130 0.293 1.593 0.605 0.965

GENOM 12 (2.791e-09, -8.001e+01) (7.750E-9, -83.996) 129 0.306 1.074 0.606 0.651

GENOM 13 (2.696e-09, -8.004e+01) (6.202E-9, -83.215) 130 0.379 1.761 0.627 1.105

GENOM 14 (2.867e-09, -8.004e+01) (5.925E-9, -83.112) 128 0.411 1.072 0.570 0.611

GENOM 15 (2.733e-09, -8.006e+01) (6.633E-9, -83.559) 130 0.339 1.76 0.734 1.296

GENOM 16 (2.644e-09, -8.001e+01) (5.139E-9, -83.014) 128 0.404 0.771 0.654 0.504

GENOM 17 (2.613e-09, -8.002e+01) (6.923E-9, -83.688) 129 0.313 1.522 0.606 0.923

GENOM 18 (2.639e-09, -8.002e+01) (7.085E-9, -83.730) 131 0.312 1.630 0.704 1.148

GENOM 19 (2.646e-09, -8.004e+01) (6.590E-9, -83.564) 128 0.333 1.640 0.658 1.079

Mean

128.75 0.329 1.467 0.659 0.970

Standard

Deviation 1.208522369 0.046 0.374 0.054 0.264

67

Page 87: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

Table 5.12 – POFs (20 different seeds) analyses for Gradient Model.

Population: 128 Mutation: 30% Crossover: 90% Nr. of Generations 2000

Run ID Nr.

ID Low Area (x) Max DC Gain (y)

Nr.

Points POF Area: 1 -A = B

Gradient Model 0 (2.647e-09, -8.001e+01) (7.238E-9, -83.771) 128 0.308 1.789 0.729 1.305

Gradient Model 1 (2.643e-09, -8.000e+01) (8.346E-9, -84.248) 130 0.252 1.490 0.625 0.933

Gradient Model 2 (2.577e-09, -8.002e+01) (8.784E-9, -84.414) 128 0.241 1.583 0.533 0.843

Gradient Model 3 (2.587e-09, -8.003e+01) (7.178E-9, -83.909) 127 0.276 1.655 0.671 1.111

Gradient Model 4 (2.623e-09, -8.003e+01) (8.478E-9, -84.352) 131 0.257 1.751 0.673 1.179

Gradient Model 5 (2.691e-09, -8.006e+01) (8.459E-9, -84.399) 129 0.252 1.337 0.608 0.813

Gradient Model 6 (2.713e-09, -8.002e+01) (7.299E-9, -83.876) 128 0.301 1.605 0.827 1.327

Gradient Model 7 (2.647e-09, -8.004e+01) (6.060E-9, -83.221) 128 0.371 2.142 0.746 1.599

Gradient Model 8 (2.750e-09, -8.002e+01) (8.678E-9, -84.406) 128 0.259 1.659 0.770 1.279

Gradient Model 9 (2.729e-09, -8.004e+01) (7.792E-9, -84.118) 128 0.280 1.671 0.622 1.039

Gradient Model 10 (2.622e-09, -8.006e+01) (8.005E-9, -84.204) 129 0.257 1.726 0.561 0.970

Gradient Model 11 (2.738e-09, -8.001e+01) (7.846E-9, -84.169) 128 0.275 1.266 0.582 0.738

Gradient Model 12 (2.638e-09, -8.003e+01) (6.959E-9, -83.807) 128 0.296 1.432 0.667 0.955

Gradient Model 13 (2.700e-09, -8.002e+01) (8.683E-9, -84.392) 128 0.249 1.642 0.792 1.301

Gradient Model 14 (2.631e-09, -8.000e+01) (7.658E-9, -84.112) 128 0.263 1.315 0.557 0.732

Gradient Model 15 (2.638e-09, -8.002e+01) (8.427E-9, -84.268) 128 0.256 1.854 0.712 1.321

Gradient Model 16 (2.589e-09, -8.004e+01) (7.568E-9, -84.025) 128 0.271 1.819 0.595 1.083

Gradient Model 17 (2.749e-09, -8.002e+01) (7.108E-9, -83.868) 129 0.295 1.650 0.872 1.439

Gradient Model 18 (2.767e-09, -8.010e+01) (8.424E-9, -84.372) 129 0.261 1.472 0.659 0.971

Gradient Model 19 (2.755e-09, -8.015e+01) (8.049E-9, -84.231) 128 0.262 1.718 0.693 1.191

Mean

128.4 0.274 1.629 0.675 1.106

Standard

Deviation 0.882 0.029 0.206 0.093 0.239

68

Page 88: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

70

As observed before through the POFs, the Table 5.11 and Table 5.12 don´t show significant

improvements by the addiction of Gradient Model. However, there are some values with importance to

be analyzed, is the case of the lowest area reached in both cases. GENOM-POF reaches the lowest

value of area at seed 11 with 2.607 nm. Already the Gradient Model obtains 2.57 nm at seed 2, which

in practical terms corresponds to an improvement. The same happens to the maximization of the DC

Gain. GENOM-POF presents the maximum DC Gain at seed 0 with the value approximately of 84.1

dB and Gradient Model achieves the maximum DC Gain at seed 2 with the value approximately of

84.41 dB.

Another important point of comparison between GENOM-POF and Gradient Model is the non-

dominated area (defined as area B). Through the Table 5.11 and Table 5.12 is shown that the non-

dominated area is generically lowest for the case of Gradient Model.

For this specific case another analyze was performed for the non-dominated area. For each seed was

analyzed from the generation 500 until the 2.000 generation which approach had constantly less non-

dominated area, shown in Table 5.13.

Table 5.13 – Analyze of non-dominated area.

Nr. of time that have

less non-dominated

area then

GENOM-POF

Percentage that have

less non-dominated

area then

GENOM-POF

Total number of

POFs analyzed

Gradient Model 270 84.64% 319

Table 5.13 shows that Gradient Model constantly have less non-dominated area, which means that

reaches better solutions faster than GENOM-POF.

Besides the fact of Gradient Model for this example doesn’t show significant improvements in

comparison with GENOM-POF, it is safe to say that for the worse case of Gradient Model, this at least

doesn’t worsen the results of GENOM-POF.

5.4 Conclusions

In this chapter was presented one case study with two different numbers of variables for sizing

optimization.

In the first example, an optimization for 15 input variables was performed with a wide search space of

solutions. For this example was analyzed the performance of GENOM-POF, GENOM-POF integrated

with Gradient Model and GENOM-POF integrated with Random Model. All the approaches were

compared through several POFs and statistical studies. For this example the conclusion were quite

clear and was proved that GENOM-POF integrated with Gradient Model presents significant

improvements in the sizing optimization. This study also shown the better solution for the maximization

of DC Gain was reached through the integration of Gradient Model in GENOM-POF.

Page 89: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

71

In the second example, the number of variables to be optimized was reduced by 12. The expectation

of reduction of the search space of solution was confirmed. The reduction of the complexity of the

problem the Gradient Model also had less significant improvement in the sizing optimization. However,

through the observation and analyze of several statistical studies was proved that for the worse case

of Gradient Model this don’t get worse than GENOM-POF.

Table 5.14 – Summarized comparison between GENOM-POF and GENOM-POF + Gradient Model.

Advantages Disadvantages

GENOM-POF

- Good application to unknown circuit.

- Good ability to adapt to any problem.

- Expandable to n dimensional space.

- The execution time

can be high, because

the entire analysis

requires many

evaluations of the

outputs during the

implementation of

internal GA.

- The user has no

control over the

optimization.

- Complex

implementation.

GENOM-POF

+

Gradient

Model

- Time model generation greatly reduced

(even negligible), for both simple and

complex circuits.

- Simple and functional implementation.

- Possibility for the designer to change the

gradient of the variables, the rate of

application of the model and the rate of

change the value of the variables.

- May be more robust

for problems where the

search space is large.

Page 90: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

72

Chapter 6 Conclusions and Future Work

This chapter presents the conclusions of all the work performed for this dissertation, and the future

directions for the continuous development of GENOM-POF integrated with Gradient Model.

6.1 Conclusions

The work presented in this paper corresponds to an innovative IC design automation approach by

embedding a simple but effective design knowledge model, Gradient Model, into the evolutionary

optimization kernel of a state-of-the-art sizing tool. The new technique proved to be capable to

accelerate and reduce the execution time of the circuit-level optimizer GENOM-POF. This integration

of the Gradient Model with GENOM-POF enhances the optimizer efficiency, forwarding the data to the

desired objectives and causing a significant reduction in the number of electrical simulations.

The model training over a circuit was performed through the technique sampling Design of

Experiments, with two possible strategies, Full Factorial Design and Fractional Factorial Design, both

showed no contradictions in their statistical analyze.

The Gradient Model created for a circuit has as main goal the creation of a set of gradient rules,

providing to designer a simple and direct analyze of the behavior of the input variables on the outputs,

for an easy knowledge of the circuit. The model generated also offers a set of parameters which the

user can explore and vary to adapt to the proposed problem. These manipulations can be performed

in the GUI. This optimizer represents an alternative, totally automated, to the traditional techniques of

optimization, where the execution time required for those techniques is extremely high.

The Gradient Model integrated in the operator mutation of Genetic Algorithm proved to be useful. This

fact is due to the tighter control of the operator mutation, producing a better management of this

operator.

The model potential has been proved through a complex case study presented. This case study was

divided in two different problems, where in the first exists a large solutions space and in the second the

solutions space is reduced. These two examples validated the fact that Gradient Model integrated in

GENOM-POF presents better solutions for large solutions space; also these examples proved that for

the worst case (short solutions space) of Gradient Model, this not worsened the results of GENOM-

POF and still get small improvements over the GENOM-POF results.

Finally, the proposed objectives for this work were achieved and a new optimizer was created.

6.2 Future Work

In analog design automation, the developments of new and better approaches are always necessary.

There is still a long way to end in this domain; the improvement on productivity of analog design is a

demand of economic market. Based on this work and his large application on analog design, there are

some suggestions for future research which may improve even more his efficiency.

Page 91: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

73

The first suggestion is the application of Gradient Model for the Corners validation. The second

suggestion to probably improve the accuracy of the model is to perform an extra sample of the circuit

after the first POF solution (feasible region) reached, to increase the accuracy of the model.

The integration of the model in GENOM-POF can be performed for alternatives approaches. An

alternative integration of the model in GENOM-POF is its application in only one objective variable.

Other alternative approach is an application of Gradient Model to each objective or all the objectives

with percentages defined by the user. An example of this approach is presented in Figure 6.1. The

expected result of this alternative approach is to accelerate the optimization problem by the application

of the model to all the objectives, and at the same time to maximize/minimize even more the objectives

by the single application of the model to an objective.

50% of application of the

Gradient Model to all

Objectives

25% of application of the

Gradient Model to Area

25% of application of the

Gradient Model to Gain

Figure 6.1 – Alternative approach of application of Gradient Model.

Page 92: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

74

References

[1] McClean, B. 2011. IC Market to Top $300 Billion for First Time in 2013.

http://www.icinsights.com/. Accessed December 13 2011.

[2] G. G. E. Gielen, “CAD tools for embedded analogue circuits in mixed-signal integrated systems

on chip”, IEE Proceedings on Computers and Digital Techniques, vol. 152, no. 3, pp. 317 – 332,

May 2005.

[3] “International Technology Roadmap for Semiconductors 2009 Edition,” http://public.itrs.net/.

[4] Gielen, G.G.E. and Rutenbar, R.A., “Computer-aided design of analog and mixed-signal

integrated circuits”, Proceedings of the IEEE, vol. 88, pp. 1825 – 1854, December 2000.

[5] N. Kordas, Y. Manoli, W. Mokwa and M. Rospert, “The properties of integrated micro-electrodes

for CMOS-compatible medical sensors”, Engineering in Medicine and Biology Society, 1994.

Advances: New Opportunities for Biomedical Engineers. Proceedings of the 16th Annual

International Conference of the IEEE, vol. 2, pp. 828 – 829, 1994.

[6] Martins, R., Lourenço, N., Guilherme, J. and Horta, N., “AIDA: Automated Analog IC Design Flow

from Circuit Level to Layout”, SMACD’ 12. International Conference on Synthesis, Modeling,

Analysis and Simulation Methods and Applications to Circuit Design, September 2012.

[7] Synopsis Inc. (2012) HSPICE® simulator.

http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/def

ault.aspx. Accessed September 2012

[8] Cadence Inc. (2012) Spectre simulator and other cadence products.

http://www.cadence.com/products/pages/default.aspx Accessed September 2012.

[9] Mentor Graphics Inc (2012) IC verification and other products

http://www.mentor.com/products/ Accessed September 2012.

[10] Rutenbar, R.A.; Gielen, G.G.E.; Roychowdhury, J.; “Hierarchical Modeling, Optimization, and

Synthesis for System-Level Analog and RF Designs”, Proceedings of the IEEE on Digital Object

Identifier, vol. 95, pp.640-669, March 2007.

[11] T. McConaghy, T. Eecklelaert, G. Gielen, “CAFFEINE: Template-free symbolic model generation

of analog circuits via canonical form functions and genetic programming”, Design, Automation and

Teste in Europe, vol.2, pp.1082-1087, 2005.

Page 93: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

75

[12] J. H. Friedman, “Multivariate adaptive regression splines”, Annals Statistics 19, pp. 1-141, March

1991.

[13] W. Daems, G. Gielen, W. Sansen, “Simulation-based generation of posynomial performance

models for sizing of analog integrated circuits”, IEEE Trans. CAD 22(5), May 2003, pp. 517-534.

[14] T. McConaghy, G. Gielen, “Analysis of simulation-driven numerical performance modeling

techniques for application to analog circuit optimization”, IEEE International Symposium on

Circuits and Systems, ISCAS, pp. 1298-1301, May 2005.

[15] N. Ampazis, S.J. Perantonis, “OLMAN neural networks toolbox for Matlab”,

http://iit.demokritos.gr/~abazis/toolbox/, 2002.

[16] R.E. Schapire, “The boosting approach to machine learning: An overview”, MSRI Workshop on

Nonlin. Estimation and Classification, 2002.

[17] H. Drucker, C.J.C Burges, L. Kaufman, A. Smola and V. Vapnik, “Support vector regression

machines”, Adv. in Neural Information Processing Systems 9, Cambridge, MA pp. 155-161, 1997.

[18] D. R. Jones, M. Schonlau, W.J. Welch, “Efficient global optimization of expensive black-box

functions”, J. Glob. Opt. 13(4), pp. 455-492, 1998.

[19] M. F. M. Barros, J. M. C. Guilherme, and N. C. G. Horta, Analog circuits and systems optimization

based on evolutionary computation techniques, Berlin: Springer, 2010.

[20] M. G. R. Degrauwe, O. Nys, E. Dijkstra et al., “IDAC: an interactive design tool for analog CMOS

circuits,” IEEE Journal of Solid-State Circuits, vol. 22, no. 6, pp. 1106-1116, 1987.

[21] R. Harjani, R. A. Rutenbar, and L. R. Carley, “OASYS: a framework for analog circuit synthesis,”

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 12,

pp. 1247-1266, 1989.

[22] F. El-Turky, and E. E. Perry, “BLADES: an artificial intelligence approach to analog circuit design,”

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 6,

pp. 680-692, 1989.

[23] H. Y. Koh, C. H. Sequin, and P. R. Gray, “OPASYN: a compiler for CMOS operational amplifiers,”

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 2,

pp. 113-125, 1990.

[24] A. Torralba, J. Chavez, and L. G. Franquelo, “FASY: a fuzzy-logic based tool for analog

synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,

vol. 15, no. 7, pp. 705-715, 1996.

Page 94: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

76

[25] A. J. Torralba, J. Chavez, and L. G. Franquelo, “Fuzzy-logic-based analog design tools,” Micro,

IEEE, vol. 16, no. 4, pp. 60-68, 1996.

[26] S. Jianfeng, and H. Ramesh, “Feasibility region modeling of analog circuits for hierarchical circuit

design,” Midwest Symposium on Circuits and Systems, Proceedings of the 37th vol. 1, pp. 407-

410, 3-5 Aug 1994, 1994.

[27] P. Veselinovic, D. Leenaerts, W. van Bokhoven et al., “A flexible topology selection program as

part of an analog synthesis system,” Proceedings of the European Design and Test Conference,

pp. 119-123, 6-9 Mar 1995, 1995.

[28] P. C. Maulik, L. R. Carley, and R. A. Rutenbar, “A mixed-integer nonlinear programming approach

to analog circuit synthesis,” Proceedings of Design Automation Conference, pp. 698-703, 8-12

Jun 1992, 1992.

[29] P. C. Maulik, L. R. Carley, and R. A. Rutenbar, “Integer programming based topology selection of

cell-level analog circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems, vol. 14, no. 4, pp. 401-412, 1995.

[30] W. Kruiskamp, and D. Leenaerts, “DARWIN: CMOS opamp synthesis by means of a genetic

algorithm,” Proceedings of the Design Automation Conference, pp. 433-438, 1995.

[31] Z. Q. Ning, T. Mouthaan, and H. Wallinga, “SEAS: a simulated evolution approach for analog

circuit synthesis,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 5.2-1-4,

12-15 May 1991, 1991.

[32] T. McConaghy, P. Palmers, M. Steyaert et al., “Trustworthy Genetic Programming-Based

Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks,” IEEE

Transactions on Evolutionary Computation, vol. PP, no. 99, pp. 1-14, 2011.

[33] P. Palmers, T. McConnaghy, M. Steyaert et al., “Massively multi-topology sizing of analog

integrated circuits,” Design, Automation and Teste in Europe, 2009, pp. 706-711.

[34] J. R. Koza, F. H. Bennett, III, D. Andre et al., “Automated synthesis of analog electrical circuits by

means of genetic programming,” IEEE Transactions on Evolutionary Computation, vol. 1, no. 2,

pp. 109-128, 1997.

[35] J. D. Lohn, and S. P. Colombano, “A circuit representation technique for automated circuit

design,” IEEE Transactions on Evolutionary Computation, vol. 3, no. 3, pp. 205-219, 1999.

[36] T. Sripramong, and C. Toumazou, “The invention of CMOS amplifiers using genetic programming

and current-flow analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems, vol. 21, no. 11, pp. 1237-1252, 2002.

Page 95: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

77

[37] C. Shoou-Jinn, H. Hao-Sheng, and S. Yan-Kuin, “Automated passive filter synthesis using a novel

tree representation and genetic programming,” IEEE Transactions on Evolutionary Computation,

vol. 10, no. 1, pp. 93-100, 2006.

[38] Y. Hongying, and H. Jingsong, “Evolutionary design of operational amplifier using variable-length

differential evolution algorithm,” International Conference on Computer Application and System

Modeling (ICCASM), 2010, pp. V4-610-V4-614.

[39] H. Chang, A. Sangiovanlli-Vincentelli, F. Balarin et al., “A Top-down, Constraint-driven Design

Methodology For Analog Integrated Circuits,” Proceedings of the IEEE Custom Integrated

Circuits, pp. 8.4.1-8.4.6, 3-6 May 1992, 1992.

[40] B. A. A. Antao, and A. J. Brodersen, “ARCHGEN: Automated synthesis of analog systems,” Very

Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 3, no. 2, pp. 231-244, 1995.

[41] N. C. Horta, and J. E. Franca, “High-level data conversion synthesis by symbolic methods,”

Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 4, pp. 802-805

vol.4, 12-15 May 1996, 1996.

[42] N. Horta, “Analogue and Mixed-Signal Systems Topologies Exploration Using Symbolic Methods,”

Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp. 161-176, 2002.

[43] N. C. Horta, and J. E. Franca, “Algorithm-driven synthesis of data conversion architectures,” IEEE

Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 10, pp.

1116-1135, 1997.

[44] E. Martens, and G. Gielen, “Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal

Systems,” Proceedings of Design, Automation and Test in Europe, vol. 1, pp. 1-6, 6-10 March

2006, 2006.

[45] E. S. J. Martens, and G. Gielen, High-level modeling and synthesis of analog integrated systems,

Dordrecht: Springer, 2008.

[46] A. Doboli, N. Dhanwada, A. Nunez-Aldana et al., “A two-layer library-based approach to synthesis

of analog systems from VHDL-AMS specifications,” ACM Trans. Des. Autom. Electron. Syst., vol.

9, no. 2, pp. 238-271, 2004.

[47] E. Deniz, and G. Dundar, “Hierarchical performance estimation of analog blocks using Pareto

Fronts,” Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2010, pp. 1-

4.

[48] E. Roca, R. Castro-Lopez, and F. V. Fernandez, “Hierarchical synthesis based on pareto-optimal

fronts,” in European Conference on Circuit Theory and Design, 2009, pp. 755-758.

Page 96: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

78

[49] B. J. Sheu, J. C. Lee, and A. H. Fung, “Flexible architecture approach to knowledge-based

analogue IC design,” Circuits, Devices and Systems, IEE Proceedings G, vol. 137, no. 4, pp. 266-

274, 1990.

[50] W. Nye, D. C. Riley, A. Sangiovanni-Vincentelli et al., “DELIGHT.SPICE: an optimization-based

system for the design of integrated circuits,” IEEE Transactions on Computer-Aided Design of

Integrated Circuits and Systems, vol. 7, no. 4, pp. 501-519, 1988.

[51] G. G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen, “Analog circuit design optimization

based on symbolic simulation and simulated annealing,” IEEE Journal of Solid-State Circuits, vol.

25, no. 3, pp. 707-713, 1990.

[52] K. Swings, and W. Sansen, "DONALD: a workbench for interactive design space exploration and

sizing of analog circuits.", Proceedings of the European Conference on Design Automation, pp.

475-479, 1991.

[53] J. P. Harvey, M. I. Elmasry, and B. Leung, “STAIC: an interactive framework for synthesizing

CMOS and BiCMOS analog circuits,” IEEE Transactions on Computer-Aided Design of Integrated

Circuits and Systems, vol. 11, no. 11, pp. 1402-1417, 1992.

[54] P. C. Maulik, L. R. Carley, and D. J. Allstot, “Sizing of cell-level analog circuits using constrained

optimization techniques,” IEEE Journal of Solid-State Circuits, vol. 28, no. 3, pp. 233-241, 1993.

[55] F. Medeiro, F. V. Fernandez, R. Dominguez-Castro et al., "A Statistical Optimization-based

Approach For Automated Sizing Of Analog Cells.", Conference on Computer-Aided Design, pp.

594-597, 1994.

[56] C. A. Makris, and C. Toumazou, “Analog IC design automation. II. Automated circuit correction by

qualitative reasoning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Systems, vol. 14, no. 2, pp. 239-254, 1995.

[57] C. Toumazou, and C. A. Makris, “Analog IC design automation. I. Automated circuit generation:

new concepts and methods,” IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems, vol. 14, no. 2, pp. 218-238, 1995.

[58] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez et al., “A vertically integrated tool for

automated design of &Sigma;&Delta; modulators,” IEEE Journal of Solid-State Circuits, vol. 30,

no. 7, pp. 762-772, 1995.

[59] E. S. Ochotta, R. A. Rutenbar, and L. R. Carley, “Synthesis of high-performance analog circuits in

ASTRX/OBLX,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and

Systems, vol. 15, no. 3, pp. 273-294, 1996.

Page 97: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

79

[60] M. Krasnicki, R. Phelps, R. A. Rutenbar et al., "MAELSTROM: efficient simulation-based

synthesis for custom analog cells.", Design Automation Conference, pp. 945-950, 1999.

[61] R. Phelps, M. Krasnicki, R. A. Rutenbar et al., “Anaconda: simulation-based synthesis of analog

circuits via stochastic pattern search,” IEEE Transactions on Computer-Aided Design of

Integrated Circuits and Systems, vol. 19, no. 6, pp. 703-717, 2000.

[62] G. Alpaydin, S. Balkir, and G. Dundar, “An evolutionary approach to automatic synthesis of high-

performance analog integrated circuits,” IEEE Transactions on Evolutionary Computation, vol. 7,

no. 3, pp. 240-252, 2003.

[63] M. Barros, J. Guilherme, and N. Horta, "GA-SVM Optimization Kernel applied to Analog IC

Design Automation.", IEEE Internation Conference on Electronics, pp. 486-489, 2006.

[64] R. Castro-Lopez, O. Guerra, E. Roca et al., “An Integrated Layout-Synthesis Approach for Analog

ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27,

no. 7, pp. 1179-1189, 2008.

[65] A. Pradhan, and R. Vemuri, “Efficient Synthesis of a Uniformly Spread Layout Aware Pareto

Surface for Analog Circuits,” in 22nd International Conference on VLSI Design 2009, pp. 131-136.

[66] K. Matsukawa, T. Morie, Y. Tokunaga et al., "Design methods for pipeline delta-sigma A-to-D

converters with convex optimization.", Design Automation Conference, pp. 690-695, 2009.

[67] L. Cheng-Wu, S. Pin-Dai, S. Ya-Ting et al., "A bias-driven approach for automated design of

operational amplifiers.", International Symposium on VLSI Design, Automation and Test pp. 118-

121, 2009.

[68] M. Kuo-Hsuan, P. Po-Cheng, and C. Hung-Ming, "Integrated hierarchical synthesis of analog/RF

circuits with accurate performance mapping.", Symposium on Quality Electronic Design (ISQED)

pp. 1-8, 2011.

[69] M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, “GPCAD: a tool for CMOS op-amp synthesis,”

International Conference on Computer-Aided Design, Digest of Technical Papers of the

IEEE/ACM pp. 296-303, 8-12 Nov 1998, 1998.

[70] F. De Bernardinis, M. I. Jordan, and A. SangiovanniVincentelli, "Support vector machines for

analog circuit performance representation.", Design Automation Conference, pp. 964-969, 2003.

[71] G. A. Wolfe, “PERFORMANCE MACRO-MODELING TECHNIQUES FOR FAST ANALOG

CIRCUIT SYNTHESIS,” University of Cincinnati, 2004.

Page 98: Enhancing a Layout-Aware Synthesis Methodology for Analog ... · desenvolveu-se uma nova abordagem para aperfeiçoar o núcleo de optimização de uma ferramenta de dimensionamento

80

[72] G. G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen, “ISAAC: a symbolic simulator for

analog integrated circuits,” IEEE Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1587-1597,

1989.

[73] M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, “GPCAD: a tool for CMOS op-amp synthesis,”

International Conference on Computer-Aided Design, Digest of Technical Papers of the

IEEE/ACM pp. 296-303, 8-12 Nov 1998, 1998.

[74] L. W. Nagel, “SPICE2: A Computer Program to Simulate Semiconductor Circuits,” EECS

Department, University of California, Berkeley, 1975.

[75] N. Lourenço and N. Horta, “GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs

with Corners Validation”, GECCO’ 12: Proceedings of the fourteenth international conference on

Genetic and evolutionary computation conference, July 2012.

[76] T. McConaghy, G. Gielen, “Analysis of simulation-driven numerical performance modeling

techniques for application to analog circuit optimization”, IEE International Symposium on Circuits

and Systems, ISCAS, pp.1298-1301, May 2005.

[77] Deb, K., Pratap, A., Agarwal, S. and Meyarivan, T. 2002. A fast and elitist multiobjective genetic

algorithm: NSGA-II. IEEE T Evolut Comput. 6, 2 (Apr. 2002), 182-197. DOI=

http://dx.doi.org/10.1109/4235.996017

[78] J. Antony, N. Capon, “Teaching Experimental Design Techniques to Industrial Engineers”, Int. J.

Engineering, No. 5, pp. 335-343, Aug. 1998.

[79] D. C. Montgomery, Design and Analysis of Experiments, 5th ed. John Wiley and Sons, New York,

2001

[80] Lourenço, N., Vianello, M., Guilherme, J. and Horta, N. 2006. LAYGEN - Automatic Layout

Generation of Analog ICs from Hierarchical Template Descriptions. In Proceedings of the

Conference on Ph.D. Research in Microelectronics and Electronics (Otranto (Lecce), Italy, June

12 - 15, 2006), 213-216. DOI= http://dx.doi.org/10.1109/RME.2006.1689934

[81] Martins, R., Lourenço, N. and Horta, N. 2012. LAYGEN II: Automatic Analog ICs Layout

Generator based on a Template Approach. In Proceedings of the Genetic and Evolutionary

Computation Conference (Philadelphia, USA, July 7 - 11, 2012),

[82] Deb, K., Goyal, M. A combined genetic adaptive search (geneas) for engineering design.

Computer Science and Informatics, 26(4):30-45, 1996.