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Dummy differenceSB differenceDummy w/o EtchCorrDummy w EtchCorrSB w/o EtchCorrSB w EtchCorr

Enhanced Resist and Etch CD Control by Design Perturbation

Abstract• Etch dummy features are used to reduce CD skew between resist and etch

processes and improve printability. However, etch dummy rules conflict with SRAF insertion because the two techniques each require particular spaces of poly-to-assist, active-to-etch dummy, etc.

• We first present a novel SRAF-Aware Etch Dummy Method (SAEDM) which optimizes etch dummy insertion to make the layout more conducive to assist-feature insertion after etch dummy have been inserted.

• We also describe a novel dynamic programming-based technique for etch-dummy correctness (EtchCorr) which is used in combination with the SAEDM for detailed placement.

• EtchCorr placement with SAEDM can achieve up to 100% reduction in number of cell border poly geometries having forbidden pitch violations.

• These techniques extend existing RET techniques to meet the ITRS CD tolerance spec by interactions with design. Hence, our techniques can delay the need for radically new RET or equipment solutions.

Summary and Ongoing WorkExperimental Results

Technique 2: EtchCorr Placement Correctness for Etch Dummy

• EtchCorr placement perturbation with SAEDM can achieve up to 100% reduction in number of cell border poly geometries having forbidden pitch violations. The corresponding reduction in EPE is up to 98% (resist CD) and 97% (etch CD)

• SB count and etch dummy counts, which indicate less through-focus CD variation and etch skew, increase up to 10.8% and 18.6%, respectively

• Increases of data size, OPC running time and maximum delay due to EtchCorr are within 3%, 4% and 6%, respectively

• Runtime of EtchCorr placement perturbation is negligible (~5 minutes) compared to running time of OPC (~2.5 hours)

• Ongoing research:– Investigate other perturbation objectives such as weighting of perturbation cost

by cell timing criticality – Develop methodologies for “correct-by-construction” standard cell layouts that

are always EtchCorrect and AFCorrect in any placement scenario

Optical and Etch Simulation

• After whitespace adjustment, additional SRAFs can be inserted to avoid forbidden pitch resist image (verifiable by simulation) is better

• Large resist-to-etch skew in isolated patterns necessitates etch dummy insertion

Cell boundaryForbidden pitch

Before AFCorr After AFCorr

Etch Dummy Insertion Problem

• Etch dummy features are placed to the outside of active-layer regions• Etch dummy features are inserted between primary patterns with

certain spacing to reduce etch skew between resist and etch process• Maximum allowable etch dummy space (MAEDS) is determined by

allowable CD skew of resist and etch

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#SB=1 #SB=2 #SB=3 #SB=4

forbidden pitch

Technique 1: SAEDM

Algorithm Approach: Dynamic Programming (DP)

Design and Test Flow

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Space (nm)

CD

(n

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Resist CDEtch CD

Maximum allowable etch dummy space (MAEDS)

Active

SRAF

Poly

Etch dummy

• Typical etch dummy rule: fixed rule for active-to-etch dummy spacing

• SAEDM: change rule of active-to-etch dummy spacing– Calculate left poly-to-dummy

and right poly-to-dummy spacings to insert Assist Features and Etch Dummies simultaneously

– Insert Etch Dummies with asymmetric left- and right- active-to-dummy spacings

Before SAEDM (SRAF missing: L=R)

After SAEDM (SRAF inserting: L R)

L

L

R

R

ActiveSRAF

PolyEtch dummy

• Key Idea: Change whitespace distribution of standard-cell placement best printability– Maximize number of assist

features (AFCorr)

– Optimize location of etch dummies (EtchCorr)

• AS (ES): sets of feasible spaces between two gates that allows insertion of required assist features (etch dummies)

• Cost(a;b) = the cost of placing cell a at placement site number b– |(x_a - b)| = placement perturbation of cell "a"– AFCost, EtchCost: printability deterioration of resist and etch CDs

• SRCH: Maximum allowable change in location of a standard-cell instance• λ: weight between goals of placement preservation and printability benefit• α and β: user-defined weights for AFCost and EtchCost

Forbidden pitch, CD slope and skew of resist and etch

SB OPC

- SB Insertion- Model-based OPC

Lithography & etch modelgeneration

Modified library & netlist

Placement

Assist and etch dummy corrected GDSII

Route

Typical GDSII

Route

Post-placement(AFCorr

+ EtchCorr)

OPCed GDS

SAEDM

TypicalDesign Flow

- Printability- #Etch dummy and #SB- EPEs of resist and etch

- Performance- Delay, OPC run time

• Our novel design flow adds steps of forbidden pitch extraction, SAEDM AFCorr and EtchCorr to typical design flow

• Minimize EPE (Edge-Placement Error) and maximize #dummy and #SB

Puneet Gupta*, Chul-Hong Park† and Andrew B. Kahng*†‡

* Blaze DFM, Inc.† UCSD, ECE Department‡ UCSD, CSE Department

• Number of total SRAFs and etch dummies increases due to EtchCorr• Reduction in Forbidden Pitch Count of resist process 57%-94% with SAEDM and 77%-100%

with SAEDM + EtchCorr• Reduction in Forbidden Pitch Count of etch process 73%-97% with SAEDM + EtchCorr

• “Etch-Correctness” solved by the following DP recurrence: