engn3213 digital systems & microprocessors clab 1: icarus...

Department of Engineering

Australian National University

ENGN3213

Digital Systems & Microprocessors

CLAB 1: ICARUS Verilog and ISE WebPACK

V3.0Copyright 2010 G.G. Borg ANU Engineering

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Contents

1 CLAB1: Introduction to ICARUS VERILOG and Xilinx ISE WebPACK 3

1.1 Aims . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 WINDOWS and the CYGWIN Command Prompt . . . . . . . . . . . . . . 3

1.3 ICARUS VERILOG and GTKWAVE . . . . . . . . . . . . . . . . . . . . . 5

1.3.1 VERILOG For Synthesis: the Multiplexer . . . . . . . . . . . . . . 6

1.3.2 A VERILOG Test Bench for the Multiplexer . . . . . . . . . . . . . 8

1.3.3 A 1-bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 ISE WebPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4.1 Schematics in ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.4.2 VERILOG in ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.5 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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1 CLAB1: Introduction to ICARUS VERILOG and

Xilinx ISE WebPACK

In this lab we will investigate the design and simulation of a multiplexer (MUX) and anADDER. The aim of the lab is to introduce some important software tools that you willfind indispensable in the course and to take a first look at VERILOG HDL. We will usetwo approaches. In the first part of the lab we will learn to use ICARUS VERILOG andGTKWAVE under WINDOWS. In the second part we will do the same with Xilinx ISEWebPACK.

Although we concentrate on simulation in this lab, ISE WebPACK can be used to performsynthesis in hardware. We touch on synthesis in this lab.

The lab is rather complex on a first try and you may not understand everything. It willbe a good idea to repeat the material at home. Clabs are not assessable and I will behappy to provide extra tutorials if need be. Also remember that whether you continue touse ICARUS VERILOG and/or GTKWAVE again is largely a matter of taste. Althoughyou must know about ICARUS VERILOG you may choose to do all of your projectsimulations in ISE WebPACK’s simulator. Mastering ISE WebPACK is crucial tomake progress in this course.

Roughly each couple of weeks I will produce a progressive reading brick that repeats thelecture notes in much more detail. To these bricks will be appended the lab notes. Youwill then be able to attempt the labs in the full context of the theory.

1.1 Aims

• Learn to use ICARUS VERILOG to simulate hardware described by VERILOG andGTKWAVE to plot the results.

• Learn to use Xilinx ISE WebPACK 9.2i to create hardware designs in schematicsand VERILOG HDL (Hardware Definition Language).

• Learn to use VERILOG to create combinational logic circuits.

• Investigate the synthesis of hardware in ISE WebPACK.

1.2 WINDOWS and the CYGWIN Command Prompt

First step is to make a directory where you can work under WINDOWS. Create a folderon the H drive.

REMEMBER TO USE YOUR FLASH DRIVE TO SAVE ALL YOUR WORKAFTER THE LAB.

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CYGWIN is a UNIX system running under WINDOWS. It produces a command promptthat is much more powerful than the DOS-style prompt under WINDOWS. At home youcan also run ICARUS VERILOG from the WINDOWS command prompt as well.

Run CYGWIN and navigate to your chosen folder by using the cd (change directory)command as in the following examples. To go to the top of the directory tree type,

cd /

To go to the H drive type,

cd /cygdrive/H

To go to the folder above the present folder type,

cd ..

To execute a binary file “mybin” in the current folder do,

./mybin |ret>

Whereas to execute it a binary such as notepad in the system folder (usual place to findthem under windows) do,

notepad |ret>

To find out where you are use the pwd (Print Working Directory) command and to takea listing of the contents of the current directory type ls.

Here is some background on all this. The reason for the ./ is that gtkwave is in the localfolder. Under unix and windows CMD a ”.” is the name for the current directory and“..” for the directory above and under UNIX only ”/” for the root of all directories (thetop directory). Also ”/” is the unix directory separator in a concatenated list of directo-ries such as ”DIR1/DIR2/DIR1/DIR2”. Under windows use ”\”. Thus ./gtkwave or.\gtkwave.exe are the ways to run gtkwave in unix respectively windows when gtkwaveis in the current folder. The gtkwave command also requires all the DLLs to be in thecurrent folder as well. The alternative for a classical WINDOWS install is to copy thebinary and all DLLs into the system folder but for some reason gtkwave does not comewith an installer. Under LINUX gtkwave does install and so all this “./” stuff is unnec-essary. ICARUS VERILOG is installed under WINDOWS and so you only need to type“iverilog” at the command line. This is because the WINDOWS system folder is in thepath for binary command execution.

Take a few moments to accustom yourself to the CYGWIN command prompt.

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1.3 ICARUS VERILOG and GTKWAVE

ICARUS VERILOG has already been installed on the Information Commons and IanRoss computers. Type the command

iverilog |ret>

to test it out. The CYGWIN window Fig 1 shows the outputs of all the above commands.

Next download GTKWAVE from,

http://engnet.anu.edu.au/DEcourses/engn3213/Software/WINDOWS/

The file GTKWAVE.zip contains all the files you need to make signal traces from ICARUSVERILOG. Whenever you use GTKWAVE you need all these files in the local directorywith your VERILOG code. A folder with all these files downloaded is shown in Fig 2.

In order to compile VERILOG source code files under ICARUS VERILOG the followingcommands must be executed,

iverilog myfile.v TB_myfile.v

vvp ./a.out

Here iverilog converts your VERILOG code into a NETLIST. A NETLIST is a standardnotation that provides a description of a circuit. The command vvp runs the simulationand produces the files for GTKWAVE. The file myfile.v is the VERILOG code thatdescribes your hardware. The file TB myfile.v is the test bench.

To run gtkwave under CYGWIN (assuming that you have a “.vcd” file in the currentfolder produced by iverilog),

./gtkwave myfile.vcd

You ’ll find it useful to create a .BAT file which contains these commands to save unec-essary typing. Assuming that the .BAT files is named cmp.bat, then to run it just typethe following at the CYGWIN command,

./cmp.bat

Note that again forward slash used by the UNIX command line compared to the backwardslash used by the WINDOWS CMD line.

For the following exercise down load CLAB1.zip from the following link and unzip it intoyour local folder.

http://engnet.anu.edu.au/DEcourses/engn3213/labs.html

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1.3.1 VERILOG For Synthesis: the Multiplexer

A multiplexer is an electronic switch that allows you to choose one of several inputs andsend it unaltered to an output. The truth table of a simple multiplexer is shown below.The × sign means a don’t care condition. Note that a multiplexer is a combinationalcircuit according to the definition provided in lectures.

X Y Sel Z0 × 1 01 × 1 1× 0 0 0× 1 0 1

Truth tables provide a unique representation of a combinational circuit. As you will seein class the Boolean logic representation of a combinational system can be immediatelyderived from the truth table.

Fact: The design of combinational circuits starts with the truth table. TheVERILOG source code can be obtained directly from the truth table or thecorresponding Boolean expression.

A VERILOG module following the truth table may be written as follows,

///////////////////////////////////////////////////////////////////////////

module mux16( Z, Sel, X, Y );

input [15:0] X;

input [15:0] Y;

input Sel;

output [15:0] Z;

reg [15:0] Z;

always @(X or Y or Sel) begin

case(Sel)

1:

Z = X;

0:

Z = Y;

default:

Z = 16’hz;

endcase

end

endmodule

///////////////////////////////////////////////////////////////////////////

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The MUX described here in VERILOG is actually a 16 bit MUX. A 16 bit MUX is similarto a 1-bit MUX except that 16 input lines on each of X and Y are connected through to16 output lines on Z according the 1-bit select valaue, Sel. It is described by a truth tablelike the one above except that it has 33 inputs and 16 outputs. Take a few moments tounderstand the code. It is your first example of VERILOG. In a 16-bit MUX all inputsand outputs (except for Sel) are 16-bit wide buses. That is: X,Y and Z are all 16 bitswide.

A bus is simply a collection of parallel wires. Each wire carries independentparallel data.

Note the syntax used to do this in VERILOG. A bus is defined by a kind of vectordeclaration: [15:0]. In VERILOG indices start from 0 as in the C programming language.

The DEFAULT case of the CASE statement makes Z a 16-bit open circuit output. Anoutput that can be an open circuit (disconnected) as well as a 0 or 1 level is referred toas a tristate output.

The operation of the ALWAY S block is as follows. Inside the ALWAY S block is a bunchof objects that take on updated values (in hardware) whenever any one of the variablesin the sensistivity list, (XorY orSel), changes. This is how VERILOG handles eventsas a function of time for combinational circuits. A similar simple construct applies tosequential circuits. Notice that it is an economical description - the only time anythinghappens is when a change occurs. All inputs likely to change must appear in the sensitivitylist of the ALWAY S block.

In simple VERILOG for synthesis all events occur instantaneously and inparallel. This is expected because hardware behaves precisely in this way. Compare thisto the sequential operation of programming languages like C, BASIC and JAVA.

The output Z is a reg variable type in VERILOG because it is on the left hand side in theALWAY S block. The datatype reg refers to a variable that can retain its value acrosstime steps. This is just what the ALWAY S block needs in order to effect changes in Z1.

In addition to a reg there is one other datatype in VERILOG known as a wire. A wireis a variable which attaches to a reg or another wire. Like real wires, a wire variable ispermanent and does not vary with time. All input and output variables in VERILOG arewires. In the schematic equivalent of a circuit, the VERILOG wires may be viewed asinterconnecting metallic wires as shown in lectures. A bus is described in VERILOGby either a reg or a wire vector1.

The above code is ready for synthesis. ISE WebPACK can be used to implement it inhardware.

1Note the implication of a reg being some kind of register. An electronic register however is a term

describing a volatile memory based on a multi-bit D-type flip flop. The electronic register is not to be

confused with the VERILOG datatype reg. Having said this they do have similarities in that reg too

imparts memory to an ALWAY S block. Having said this, the VERILOG datatype reg is a language

construct which would be but one variable in a complete VERILOG description of a single electronic

register. Make sure you understand the difference.

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This is an example of VERILOG for synthesis.

1.3.2 A VERILOG Test Bench for the Multiplexer

To test the MUX for proper operation we need a test bench. A test bench is a VERILOGprogram that provides stimuli for the VERILOG module under test. The test bench alsoproduces outputs from the test module that can be viewed and analysed.

Test bench VERILOG code is only used for simulation.

The following is a test bench for the MUX.

///////////////////////////////////////////////////////////////////////////

‘timescale 1 ns/1 ps

module TB_mux16;

reg [15:0] X;

reg [15:0] Y;

reg Sel;

wire [15:0] Z;

mux16 m16( Z, Sel, X, Y );

initial begin

$display("\t\t t \t X \t Y \t Sel \ t Z");

#1X <= 16’h0000;

#1Y <= 16’hFFFF;

#1Sel <= 1;

#1$display("%d \t %b \t %b \t %b \t %b", $time, X,Y,Sel,Z);

#1X <= 16’hFFFF;

#1Y <= 16’h0000;

#1Sel <= 1;


#1X <= 16’h0000;

#1Y <= 16’hFFFF;

#1Sel <= 0;


#1X <= 16’hFFFF;

#1Y <= 16’h0000;

#1Sel <= 0;

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end

initial begin

$dumpfile("MUX16.vcd"); //GTKWAVE stuff

$dumpvars;

end

initial begin: stopat

#50; $finish;

end

end

endmodule

//////////////////////////////////////////////////////////////////////////

The test bench provides output in two forms: a screen dump provided by the displaydirective (note the similarity to the C language printf command) and the dumpvarsdirective which produces .VCD output for GTKWAVE.

Another interesting simulation-only construct in the test bench is the #1. The #n tells thesimulation to wait n system times (here 1 ns) before executing the command immediatelyafter. Note that this assumes that ICARUS VERILOG is executing the code in a serialfashion. This is clearly only relevant to simulation.

Exercise 1. Using a WINDOWS editor such as WORDPAD or PROGRAM-MER’S NOTEPAD, save copies of the mux16.v file and its test bench. Usingthe above cmp.bat simulate the 16-bit multiplexer. You should get an outputlike that shown in Figs 4 and 5.

1.3.3 A 1-bit Full Adder

A full adder is an adder with carry-in and carry-out. The truth table of the 1-bit fulladder is as follows.

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X Y Cin Z Cout0 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 11 0 1 0 11 1 1 1 1

The truth table of the 1-bit full adder

The VERILOG for the 1-bit full adder and its test bench may be written as follows

//////////////////////////////////////////////////////////////////////////


module add1(X, Y, Cin, Z, Cout);

input X;

input Y;

input Cin;

output Z;

output Cout;

reg Z;

reg Cout;

always @(X, Y, Cin) begin

Z = ???;

Cout = ???;

end

endmodule

//////////////////////////////////////////////////////////////////////////

Exercise 2. Fill in the ??? code for Z and Cout in the VERILOG for theADDER

//////////////////////////////////////////////////////////////////////////


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module TB_add1;

reg X;

reg Y;

reg Cin;

wire Z;

wire Cout;

add1 a1(X, Y, Cin, Z, Cout);

initial begin

$display("\t\t t \t X \t Y \t Cin \t Z \t Cout");

#1X <= 0;

#1Y <= 0;

#1Cin <= 0;

#1$display("%d \t %b \t %b \t %b \t %b \t %b", $time, X,Y,Cin,Z,Cout);

#1X <= 0;

#1Y <= 1;

#1Cin <= 0;


#1X <= 1;

#1Y <= 0;

#1Cin <= 0;


#1X <= 1;

#1Y <= 1;

#1Cin <= 0;


#1X <= 0;

#1Y <= 0;

#1Cin <= 1;


#1X <= 0;

#1Y <= 1;

#1Cin <= 1;

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#1X <= 1;

#1Y <= 0;

#1Cin <= 1;


#1X <= 1;

#1Y <= 1;

#1Cin <= 1;


end

initial begin: stopat

$dumpfile("ADD1.vcd");

$dumpvars;

#120; $finish;

end

endmodule

//////////////////////////////////////////////////////////////////////////

Exercise 3. Compare the ICARUS VERILOG screen dump and the GTK-WAVE signal traces for the 1-bit full adder and try to reconcile them.

1.4 ISE WebPACK

In this section we are going to look at several aspects of project development with ISEWebPACK (or ISE for short). Specifically

1. Make a 1-bit MUX for synthesis using schematics

2. Implement the 1-bit MUX using VERILOG HDL in ISE

3. Implement the 1-bit adder using VERILOG HDL in ISE

The main exercise however is to become accustomed to using ISE.

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1.4.1 Schematics in ISE

There are two ways that one will design hardware in this course and both are acceptableapproaches. One uses schematics which are hardware blocks with inputs and outputs.Different blocks are interconnected by buses. The other is VERILOG HDL. In practive youwill find that VERILOG is the easier of the two methods to apply. However all VERILOGcode that you design should be accompanied by at least a hand written schematic. Thisis because VERILOG for synthesis is all about building hardware and you must knowin advance the hardware that will be built by the ISE synthesiser - i.e. theschematic. In this section we will look at how schematics can be handled in ISE.

Fig 6 shows a schematic of the 1-bit MUX that we are going to enter into ISE. Inspect thecircuit and make sure you understand how it works. It should already be obvious fromthe previous truth table.

To implement the 1-bit MUX in ISE proceed as follows2.

1. Open ISE from the start menu. Start with New Project under file and chooseSchematic from the list. ISE asks you for the project name and folder. Make surethat it is in a suitable place. See Fig 8.

2. Use the values in Fig 9 for this project. This information specifies the hardware.Note that the Top-Level Level Source Type shows Schematic. If you had chosena VERILOG project then it would read HDL and you would have to add your sourcecode from a text file rather than use the ISE schematic editor to draw a circuit.Working in VERILOG allows you to work off-line outside of ISE.

3. To make a schematic go to Projects → New Source and select schematic. SeeFig 10.

4. This will create a schematic pane in which you can draw your circuit diagrams. SeeFig 11.

5. Browse the categories in search of LOGIC type devices and add two and2 (twoinput AND gates) devices, one 2or (two input OR gate) and an inv (inverter) asshown in Fig 12

6. Next add the wires using the WIRE tool and add IO labels. These will be assignedin the next steps to the package pins on the XC2S50 PQ208 FPGA. Also changethe IO labels to the more suitable names: X,Y,Sel and Z. See Fig 13.

7. Once you have changed the labels, go to the process pane and start the design ruleprocesses. In particular click on Check Design Rules to check if the circuit has

2In this exercise we will do the design for a SPARTAN II XC2S50 FPGA. In the hardware labs however

the part used in the SPARTAN 3E starter kit is a XC3S500E FPGA

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been connected correctly. Be patient here as this could be a tricky step if you madea mistake in the wire and IO port label entries3. See Fig 14.

8. Assign the package pins as shown in Fig 15

9. Look at the contents of the User Constraints File (UCF) as shown in Fig 16. TheUser Constraints File (UCF) is a text file that contains hardware related informationabout your ISE project. The UCF can be included with your source files to specifythe pin assignments to the FPGA and other hardware specific information. Itallows you to bundle your completed projects for ENGN3213 assignments, productdeliveries etc.

10. An interesting resource is the FPGA floor planner shown in Figs. 17 and 24. Observewhere the inputs and outputs are indicated in the floorplan. The floorplan showsthat a single slice has been used in the design. Make sure that you revisit lectures3 and 4 and your FPGA datasheet to understand how the FPGA has implementedyour circuit.

11. Generate the fuse file. The .BIT file is the file you download to the FPGA. TheISE iMPACT tool allows you to download the BIT or fuse file to the FPGA overeither the proprietory USB interface or (as in this course) the JTAG cable via thePC printer port.

12. Finally the most useful piece of documentation is the device utilisation summaryin the synthesis report as shown in Fig 18.

Fig. 19 shows how the XC2S50 slice actually implents the 1-bit MUX as a LUT (LookUp Table).

1.4.2 VERILOG in ISE

This is the most important section as it shows you how to use VERILOG to design andmanufacture hardware. The last section already covered most of what you need to know.

First we will use the following VERILOG file of a 1-bit MUX.

module mux1( Z, Sel, X, Y );

input X;

input Y;

input Sel;

output Z;

3In fact this is the weakness of the ISE schematics editor. Generally it is hard to guarantee regular

good connections in the GUI. This is a reason why we will avoid ISE schematics in the rest of the course

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reg Z;

always @(X or Y or Sel) begin

Z = ???;

end

endmodule

Exercise 4. Use the schematic of Fig 6 to provide the Boolean expression to

replace the ??? in the ALWAYS block.

1. First close any old projects in ISE. Start with New Project under file and chooseHDL from the list and Verilog. ISE asks you for the project name and folder.Make sure that you save them in a suitable place that you can at least locate onthe PC. See Figs 20 and 21.

2. Skip through each of the next dialogues. Note however that you could have addedyour mux1.v here as your VERILOG code should be ready to go before firing upISE.

3. Now go to Project → Add Source and navigate to where you have put mux1.vabove and add it to the project. The project should look as shown in Fig. 22.

4. Now click on mux1.v in the sources pane. You should see your VERILOG codeappear in the right pane as shown in Fig. 23.

5. Now all the steps are as above. Assign the package pins in exactly the same mannerwith exactly the same names as in Fig. 15.

6. Run Synthesize XST etc. until all the steps get a green tick.

7. Finally have a look at the FPGA floorplanner, UCF file and the synthesis report.Note how Fig 24 is identical to 17.

In future for more complicated VERILOG designs, always view the floor-planner to get an idea of how you are using the hardware. Do not assumethat the ISE XST synthesiser will always produce efficient hardware. Try tounderstand how your VERILOG code determines the routed hardware

Exercise 5. We have now developed a 1-bit MUX in ISE. In order to getsome practice using ISE, do the same for the 1-bit adder that we previouslysimulated in ICARUS VERILOG.

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1.5 Figures

Figure 1:

Figure 2:

16

Figure 3:

Figure 4:

17

Figure 5:

X

Z

Y

Sel

Figure 6:

18

Figure 7:

Figure 8:

19

Figure 9:

Figure 10:

20

Figure 11:

Figure 12:

21

Figure 13:

Figure 14:

22

Figure 15:

Figure 16:

23

Figure 17:

Figure 18:

24

Figure 19:

Figure 20:

25

Figure 21:

Figure 22:

26

Figure 23:

Figure 24:

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engn3213 digital systems & microprocessors clab 1: icarus...

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