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ENGINEERING TRIPOS PART II A
ELECTRICAL AND INFORMATION ENGINEERING TEACHING
LABORATORY
EXPERIMENT 3B2-B
DIGITAL INTEGRATED CIRCUITS
________________________________________________________________________
OBJECTIVES :
1. To interpret data sheets supplied by the manufacturers of digital integrated circuits
and to use the data in a design exercise.
2. To make measurements on NAND gates from two different technologies to compare
logic output levels, propagation delays and power consumption.
3. To investigate how the power-delay products for each of these technologies varies
with switching frequency.
4. To gain experience in using oscilloscope probes with a 100 MHz oscilloscope to
make accurate measurements down to a few nanoseconds.
5. To assemble and test a simple system using digital ICs.
6. To record the system waveforms.
2
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3
PERFORMANCE AND APPLICATION OF DIGITAL INTEGRATED CIRCUITS
1. Introduction and aims.
2. Apparatus.
3. Procedures.
4. Performance measurements.
5. Applications.
1. Introduction
Skill and experience are needed before an engineer can quickly decipher Manufacturers’
Data sheets for integrated circuits and use the information they contain to design an
electronic system. As integrated circuits packages steadily increase in complexity the
importance of this kind of experience becomes greater. Different technologies have been
developed and manufacturing techniques are continually improving which has led to the
present day situation where there are many different digital integrated circuit families from
which to choose. The main factors affecting the designer’s choice are speed of operation,
power consumption, cost and the particular application.
In this experiment logic gates from two different families are examined for speed (in terms
of propagation delay) and power consumed at various switching rates to make a comparison
in terms of a power-delay product. Other basic parameters are to be measured and compared
with quantities in the published data sheets. A data sheet pack is issued for this experiment,
which includes all the necessary information and pin connections for all the devices, which
may be used.
The second part of this experiment is to construct and test in a breadboard form either a
pulse generator or a logic circuit to illustrate the operation of a traffic light sequence.
Records of the relevant waveforms are to be made and included in your report.
In addition to the two hours laboratory time a similar amount of time should be devoted to a
written report, which will include some design and further reference to the data sheets.
The integrated circuit types to be used are listed below: -
(a) 74C00, 74LS00 Quad 2-input NAND gates
(b) 74LS04 Hex inverters
(c) 74LS13 Dual 4-input NAND gates with Schmitt inputs
(d) 74LS76 Dual J-K Flip-flops
(e) 74LS123 Dual retriggerable monostable multivibrators
(f) 74LS93 4-bit binary counter
(g) 74LS86 Quad Exclusive-OR gates
4
2. Apparatus
The apparatus available for this experiment includes a 100 MHz oscilloscope to display
waveforms, a DMM for current and voltage measurements, a test box comprising of power
supply and oscillators to provide the necessary test signals, a prototyping “breadboard” for
the construction of test circuits and LEDs in red, green and yellow for use as diagnostic
indicators.
2.1 The 100 MHz oscilloscope has a rise-time of 3.5 nanoseconds and for the
measurements to be made it is most important that it is used with correctly adjusted x10
probes. The benefit of using probes is to reduce the loading of the oscilloscope input to a
capacitance of 15 pF in parallel with a resistance of 10 Megohms, whilst maintaining the full
oscilloscope bandwidth. If you are unsure of the techniques for displaying waveforms and
making the necessary measurements then you are advised to consult your demonstrator.
2.2 The digital Multimeter (DDM) is used in current mode to measure the current
consumed by the device or circuit under test at the sockets situated on the Test Box and may
be used in voltage mode to measure logic levels. Remember for greater accuracy it is
necessary to display as many digits as possible.
2.3 The Test Box contains a 5-volt power supply. Internal oscillators produce a low
frequency square wave at 1 Hz and a high frequency clock at selected frequencies of
100kHz, 300kHz and 1 MHz. The test socket is wired as shown in Appendix A to accept
74C00 and 74LS00 NAND gates, which have identical pin connections. The four gates in
each package are connected as inverters in series. The output of each gate is available at the
monitor points G1, G2, G3 and G4, whilst the input to the first gate has a separate monitor
point and is connected to the internal oscillator or to ground as determined by the switch.
2.4 A prototype “breadboard” is provided for the construction of test circuits. The
arrangement of the connections beneath the matrix of sockets is as indicated in Fig. 1; note
that top and bottom rows of the board are continuously linked and can act conveniently as
supply rails. For connections use only SINGLE STRAND wire or component leads of
less than 0.85 mm diameter.
2.5 An LED diagnostic probe suitable for TTL logic circuits is shown in Fig. 2. The
current limiting resistor is essential to prevent damage to the LED. The additional diode
limits the reverse bias of the LED to approximately 0.7 volts and so prevents the possibility
of reverse voltage breakdown. This protection diode may be omitted for most circuit
configurations such as the LED indicators in the traffic light sequence.
5
LED data: IF max = 50mA, VF = 2.1V at IF =12mA VR = 3V
Cathode is indicated by a notch or flat on the LED body.
3 Procedures – some general points to bear in mind
3.1 Digital circuits switch very rapidly. If the power supply is not adequately de-
coupled on the circuit board, then the self-inductance of the supply leads can lead to poor
transient behavior. This will be seen as high frequency ringing on outputs and can cause
spurious triggering of sequential circuits. A 10 or 100 nF capacitor connected across the
supply lines close to the IC package should alleviate any such problems
3.2 Propagation delays are customarily assessed as the time elapsing between the input
signal passing through a fixed voltage level, at which switching occurs, and the output
passing through the same level. You should study the manufacturer’s data to establish the
value of this fixed voltage for each IC technology.
3.3 The usual technique for measuring rise and fall times is based on finding the 10%
and 90% points of the transition being examined. It is relatively easy to obtain accurate
measurements of the rise and fall times by following the instructions in the oscilloscope user
manual.
3.4 Manufacturers quote in their data conditions under which any parameter is measured.
For propagation delay measurements a recommended load is specified and this in general
will relate to the loading, which would be imposed on an output by other logic inputs of the
same IC family. In order to compare your results with the manufacturer’s data remember
that the oscilloscope probe when correctly adjusted will load any monitor point with a
capacitance of approximately 15 pf. The resistance of the probe at 10 Megohms can be
ignored.
6
3.5 It is important that in the scheduled laboratory time you make all the
measurements and observations necessary for your write-up. If you have any
problems, particularly difficulties with operating the oscilloscope do not hesitate to
seek guidance from your demonstrator. Make sure you leave sufficient time to make a
record of the waveforms for your chosen application. Most of the comparisons with data
sheet values and all design can be done separately as part of your report and should not be
regarded as time to be spent in the laboratory.
4 Performance measurements
74C00 and 74LS00 Quad 2-input NAND gates
The type numbers above represent members of two different device technologies, namely
CMOS and low-power Schottky TTL respectively. A prefix of two or more letters is used
by semiconductor manufacturers to identify their products. A suffix usually refers to the
type of packaging. In TTL technologies bipolar devices are switched in and out of
saturation; in CMOS, p- and n- type MOSFETs are used in a push-pull arrangement. While
the pin connections and logical functions of the 74C00 and 74LS00 are identical, their
electrical characteristics differ in a number of important ways. There are several other
technologies available to the designer, including further CMOS and TTL variants, and the
emitter-coupled logic families. Although some of these are very widely used it is not
possible to investigate all of these within the scope of this experiment.
The aim of this section is to elucidate the main differences in the characteristics between the
different gate types, and to compare their measured performance with the manufacturer’s
specifications.
It will be seen from the data the CMOS gates consume only a very same amount of supply
current when the outputs are in either the logic “0” or logic” “1” states. This is because
either the p-channel or n-channel MOSFETs are cut-off and only leakage current flows.
Significant power is consumed only when switching occurs and this will depend on the
loading, which is assumed to be entirely capacitive for other CMOS gate inputs, and will be
directly proportional to the switching rate.
The data for the bipolar technologies shows that power is taken when outputs are at either
low or high. This because npn transistors capable of sinking or sourcing current are
conducting in the corresponding logic states. When switching, further supply current is
required to drive circuit capacitances and other TTL inputs, but this increase with switching
frequency is relatively small compared with the quiescent current.
7
4.1 CMOS NAND gates
Using the Test Box carry out measurements are follows:
(i) Insert a 74C00 package in the test socket. This is a “zero insertion force” (ZIF)
socket and the IC is retained and released by operating the attached lever. Connect the
DMM set to measure current between the 4mm sockets marked 1cc.
(ii) Set the Test Box oscillator frequency to 100 kHz and record the supply current
(in micro-amps). Repeat at 300 kHz, 1MHz and with the input grounded.
(iii) With the test oscillator frequency at 1 MHz compare the input waveform with the
waveform at the output of the first gate. Examine the output high-low and low-high
transitions and obtain a value of the propagation time in each case. Propagation delay is
measured at the typical switching level and this voltage is quoted in the manufacturer’s data.
(iv) Measure the propagation delay through all four gates in the package (i.e. from the
INPUT to G4 output), and thus obtain an average figure for tpHL and tpLH.
(v) Measure the low and high logic voltage levels. This can be achieved more
accurately by grounding the input so that gate outputs G1 and G3 will be high and gate
outputs G2 and G4 low. Values can then be read as DC voltages using the DMM.
4.2 Low Power Schottky TTL NAND gates
Replace the 74C00 device with a 74LS00 Quad 2-input NAND gate and repeat the
measurements as in 4.1(ii) to 4.1 (v). It will be necessary to use the milliamp scale for the
supply currents and to check again for the quoted switching level from the manufacturer’s
data.
Make sure that you have recorded all the necessary details for this measurement section then
proceed to one of the applications in the next section.
The write-up should contain on a single graph a plot of the power-delay product against
frequency for both types of NAND gate. It should be possible to conclude over what
frequency range CMOS has an advantage in the power-delay figure of merit over the low
power Schottky. In comparing measured parameters with the manufacturer’s data
draw up tables and list where appropriate the minimum, typical and maximum values
specified in the data against your recorded values. Comment on your findings.
8
5 Applications of Digital Integrated Circuits
You are expected to construct ONE of the systems:
EITHER (a) a Pulse Generator
OR (b) a Traffic Light Controller
In each case a basic circuit is provided and the prototype “breadboard” is to be used to
assemble the chosen system. Care should be taken to keep interconnections as short as
possible. The positioning of the oscilloscope earth lead in relation to the other circuit earths
can also be critical when observing high speed switching waveforms.
Use decoupling capacitors as recommended where necessary.
A small stock of discrete components (R, C, etc) is available in the laboratory. Consult a
demonstrator if you feel that you need components not already available on the bench.
Also available are printers to record the output and prepulse waveforms for the pulse
generator or the three traffic light controller outputs. A single printer output should show the
relative timing of the waveforms. Ask a demonstrator to check your display settings before
you attempt to record the waveforms.
5.(a) Pulse generator
5.1 Construct the simple pulse generator with the component values and digital
integrated circuit types as shown in Fig. 3. It is intended that the Schmitt oscillator generates
a basic pulse repetition frequency, the monostable multivibrator form a short duration
prepluse and the final bistable circuit shape the output into a symmetrical square wave. The
output of the Schmitt oscillator is not a symmetrical square wave although its frequency is
determined by a single RC time constant. This is because TTL devices have significant
output resistance for high level outputs and draw significant input current for low level
inputs. The circuit can function over a very wide frequency range by changing the
capacitance value but the choice of resistance value is limited to a narrow range around 330
ohms.
5.2 Make any modifications to the circuit to ensure the observed waveforms are as “clean”
as possible then record the output and prepulse waveforms. Optionally you may like to
include the Schmitt output waveform as part of the timing sequence. Some thought will be
needed to arrive at the best method for triggering the display.
9
Make accurate measurements of: -
(i) The frequency of the output square wave.
(ii) The duration of the prepluse.
(iii) The rise and fall times of the output square waves.
(iv) The supply current.
In your report compare your measurements with the quantities extracted from
manufacturer’s data wherever this is relevant.
5.3 As part of your report, design a pulse generator based on that shown in Fig. 3, and
using the same three digital ICs to provide, in addition, a second square wave output. Using
your experimental results or device data choose circuit component values to generate square
wave outputs at 100 kHz with the first square wave delayed by the prepulse by 500 ns.
The second square wave output is to have variable delay relative to the original square wave
output. Design for a minimum delay of 500 ns (so that both outputs can be coincident) and
the maximum feasible delay. What do you expect this maximum delay to be?
The NAND gate in the other half of the 74LS13 Schmitt can be used to combine the original
prepulse and square wave outputs. Explain why this combined waveform could provide a
more useful prepulse when used as a trigger signal for an oscilloscope.
Sketch the idealized waveforms you would expect to observe at the various parts of your
circuit showing clearly relative timing between device outputs.
10
5. (b) Traffic Light Controller
The requirement is for a unit to provide the following sequence:
Input I high: RED on, GREEN and AMBER off.
Input I Low: (a) Sequence starts with RED on, GREEN and AMBER off for
between 4 and 6 seconds;
(b) then RED and AMBER on, GREEN off for 2 seconds;
(c) then GREEN on, RED and AMBER off for 6 seconds;
(d) then AMBER on, GREEN and RED off for 2 seconds;
(e) then RED only for 6 seconds. The sequence should then continue
with phase (b), and so on. At any stage, setting input I high should
result in the RED “stop” condition being displayed.
The logic design is based on the sequence table below:
COUNTER OUTPUTS TRAFFIC LIGHTS
QD QC QB R A G
0 0 0 1 0 0
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 0 0 1
1 1 0 0 0 1
1 1 1 0 1 0
By using Karnaugh maps or by inspection from the above table the logic expressions for the
RED, AMBER and GREEN outputs in terms of the counter outputs are found to be:
_ _
R = QD A = QC QB G = QD. QC + QD. QB
__
= QD (QC +QB)
______
= QD (QC. QB)
by de Morgan
This logic design is translated straightforwardly into the circuit of Fig. 4.
11
Extra inverters have been added to drive the LED indicators. TTL outputs have lower output
resistance in the LOW-level state and a more closely defined output voltage level, which is
within a few tens of millivolts relative to ground. The inverters shown in Fig. 4 are the six
contained in a single 74LS04 package and the NAND gates are part of a 74LS00 package.
The pin connections can be found in the data. Remember that the power supply pins for
each package need to be connected to +5volts (VCC) and ground (GND).
5.4 Assemble this circuit on the “breadboard” provided and check that it functions
correctly as indicated by the RED, AMBER and GREEN LED indicators.
Measure the supply current taken by the circuit and in your report check that this falls within
the limits specified in the manufacturer’s data for the digital ICs used.
Replace the 1 Hz clock with a high frequency clock and obtain oscilloscope traces for the
RED, AMBER and GREEN outputs showing the relative timing of the sequence as a whole.
When a satisfactory display has been achieved, record your waveforms.
5.5 As part of your report, design a new logic circuit such that the reset condition, (I
high), is changed to AMBER only ON. On restart, (with I low), the sequence follows that
shown in section 5 (b).
In your report show how you derived your logic expressions, which should be simplified to
use the least number of Digital IC packages of the types listed on page two. Note that
exclusive-OR gates are available in the 74LS86 package.
Draw a full circuit diagram showing clearly ‘outputs’ and connections to the appropriate
LEDs, and estimate the maximum current your circuit will draw.
.
Experiment originally developed by R.R. Thorp
D.M. Holburn
January 2016
12
Appendix A
The connections to the IC test socket are as shown below:
Appendix B Page 1
TEXAS INSTRUMENTS LTD have given their permission for this material to be reproduced for educational purposes (their letter, 29 June 1982, Mr K Goldup, Operations Manager).
54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN ASSIGNMENT (TOP VIEWS)
See page 3 See page 3
See page 7 See page 14
See page 9
See page 16 See page 10
Appendix B Page 2
TEXAS INSTRUMENTS LTD have given their permission for this material to be reproduced for educational purposes (their letter, 29 June 1982, Mr K Goldup, Operations Manager).
You can see more detailed versions of the following data sheets as PDF files at:
http://www2.eng.cam.ac.uk/~dmh/ptiialab/3B2
For further information and data sheets, point your browser at:
http://www.ti.com/lsds/ti/logic/home_overview.page
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Page 5
Page 6
Page 7
Page 8
Page 9
SN54
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Page 10
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Page 11
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Page 12
SN54
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Page 13
Page 14
Page 15
Page 16