engineering portfolio of isaac bettendorf

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Engineering Portfolio of Isaac T. Bettendorf Degree: BS in Electrical Engineering, concentration in Computer Engineering School: George Mason University Volgenau School of Engineering Graduated: Summa Cum Laude in December 2016 GPA: 3.98/4.0 Relevant Engineering and Technical Classes Taken: 1. CS222: Computer Program for Engineers 2. ECE220/320: Signals and Systems 3. ECE285/286: Electrical Circuit Analysis 4. ECE331: Digital Systems Design 5. STAT346: Probability for Engineers 6. ECE333/433: Linear Electronics (Microelectronics) 7. ECE431: Digital Circuit Design (Digital Microelectronic Design) 8. ECE445: Computer Organization 9. ECE421: Classical System and Control Theory 10. ECE447: Single Chip Microcomputers 11. ECE460: Communication and Information Theory 12. ECE448: FPGA/ASIC Design with VHDL 13. ECE305: Electromagnetic Theory

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Page 1: Engineering Portfolio of Isaac Bettendorf

Engineering Portfolioof

Isaac T. Bettendorf

Degree: BS in Electrical Engineering, concentration in Computer Engineering

School: George Mason University Volgenau School of Engineering

Graduated: Summa Cum Laude in December 2016

GPA: 3.98/4.0

Relevant Engineering and Technical Classes Taken:1. CS222: Computer Program for Engineers2. ECE220/320: Signals and Systems3. ECE285/286: Electrical Circuit Analysis4. ECE331: Digital Systems Design5. STAT346: Probability for Engineers6. ECE333/433: Linear Electronics (Microelectronics)7. ECE431: Digital Circuit Design (Digital Microelectronic

Design)8. ECE445: Computer Organization9. ECE421: Classical System and Control Theory10. ECE447: Single Chip Microcomputers11. ECE460: Communication and Information Theory12. ECE448: FPGA/ASIC Design with VHDL13. ECE305: Electromagnetic Theory

Page 2: Engineering Portfolio of Isaac Bettendorf

ASLIM: Automated Slotted-Line Impedance Measurement DeviceTeam Members: Isaac Bettendorf, Valentina Morrison, Andrew Huttner, Charles Pritchard, Peter

Handjinicolaou, Ian KanyamanzaAdvisor: Dr. Peter Pachowicz

Figure 1: General system architecture and system signal flow of ASLIM Figure 2: Design Award

Page 3: Engineering Portfolio of Isaac Bettendorf

ASLIM: Automated Slotted-Line Impedance Measurement DeviceProject Description: • The purpose of the ASLIM Device is

to be an inexpensive alternative to a digital network analyzer. This device was designed to be capable of performing all of the core functionalities of a digital network analyzer.

• The system automates the Slotted-Line Impedance Measurement method

Device Process Description (look at Figure 1 for visualization):1. The device generates a frequency

sweep with the signal generator.2. Signals from signal generator travels

through the filter banks to eliminate noise.

3. Signal travels through Slotted-Line (copper coaxial transmission line with thin vertical opening) and power standing wave (PSW) is formed within.

6. Power detector and position data go to microcontroller (PIC24).

7. PIC24 controlled the runtime operation of device including the control of the direction and speed of power detector (using PWM) and the control of signal generator and filter banks.

8. PIC24 then sends (via SPI) all data to BeagleBone Black to be processed.

Figure 3: Front EagleCAD of 2 Ground Plane PIC24FJ and motor driver PCB

4. Power detector moves vertically along Slotted-Line sampling envelope of PSW.

5. Encoder keeps track of power detector’s position

Figure 4: Conceptual Schematic of PIC24FJ and motor driver PCB

Page 4: Engineering Portfolio of Isaac Bettendorf

ASLIM: Automated Slotted-Line Impedance Measurement DevicePersonal Responsibilities on Project Team:1) Project Manager:

• Administrative Duties: scheduling, record keeping, and technical writing

• System Manager: directing flow of ideas, dividing responsibilities among team mates, communication, orchestrated top-down design approach and directed integration/debugging at every stage of the design process.

2) Microcontroller and Embedded System’s Engineer:• Duties Performed: integration of hardware (PIC24 and

others) and software into a larger system; working with tradeoff between power consumption, speed of operation, cost, and size/area of device.

Further Specifications/Details of Project: • Signal generator can perform sweep up to a range of

500MHz to 3 GHz• User operates device through custom GUI• Device displays antenna impedance at different

frequencies (Smith chart).• Import and export data using file management

systemFigure 5: Showing how data travels from Slotted-Line, to PIC24, and then to BeagleBone Black

Page 5: Engineering Portfolio of Isaac Bettendorf

Microcontroller Projects (ECE447)

Basic Material Used:1) Resistors (100, 500, 1K, 10k, 30k Ohm)2) Capacitors (1, 10 uF)3) External Push Buttons4) 4x4 Matrix Keypad5) E336755 Color TFT LCD Display (1.8”)6) MMA8451 Accelerometer7) HC-SR04 Ultrasonic Sensor8) MSP430FR6989 LanchPad9) External LEDs (Red, Green, Yellow,

Blue)10) Piezoelectric Buzzer11) MCP4725 12-Bit DAC

General Description: There are nine different projects in all. These projects were part of laboratory design experiments for the undergraduate class titled ECE447: Single-Chip Microcomputer at George Mason University. This utilized the C language and some assembly to program the MSP430FR6989 microcontroller (MCU).

Figure 6: MMA8451 Accelerometer

Figure 7: MSP430FR6989 LanchPad (center), E336755 TFT LCD (upper right), HC-SR04 (lower right), External Buttons (lower left), 4x4 Matrix Keypad (upper left)

Page 6: Engineering Portfolio of Isaac Bettendorf

Microcontroller Projects (ECE447)

Project Descriptions and Concepts Learned:

1. Controlling LED by Polling Push Button: This project reviewed the concept of polling and how to assemble a pull-up networks both internal and externally to the MCU. (Resistor pull-up network for external).

2. Extended Segmented Display: create basic “Snakes Game” that moves around onboard LCD.

3. Continued Extended Segmented Display: Add functionality onto previous assignments with ball that moves around onboard display and adding external LEDs. Also utilized interrupt based inputs rather than polling based inputs.

4. PWM and Matrix Keypad Decoding: Scan a 4x4 matrix keypad to determine what button has been pressed.

Basic Concepts Utilized in Projects:

1) Polling Inputs

2) External Interrupts

3) Pulse Width Modulation (PWM)

4) Matrix Keypad Decoding

Page 7: Engineering Portfolio of Isaac Bettendorf

Microcontroller Projects (ECE447)

Project Descriptions and Concepts Learned Continued:

5. Timer Interrupts and Piezoelectric Buzzer: Using matrix keypad, external LEDs, and Piezoelectric Buzzer, change pitch of piezoelectric buzzer and ON state of external LEDs.

6. Ultrasonic Measuring Tap: Use the HC-SR04, timer capture mode, and onboard LCD to create an ultrasonic distance measuring device.

7. Basic Logic Analyzer: Use the E336755 Color TFT LCD Display (1.8”) which communicates via SPI to create a 4-channel digital logic analyzer.

8. Move Ball on Graphical LCD with Accelerometer: Use the MMA8451 Accelerometer (which communicates via I2C) to move a ball around on the E336755 Color TFT LCD Display (1.8”).

9. ADC and DAC Conversion: Use the internal 12-bit ADC and the external MCP4725 DAC to first convert a sinusoidal signal from analog to digital and then back from digital to analog.

Basic Concepts Utilized in Projects Continued:

5) Basic Internal Timers and ISRs

6) Debouncing External Button Inputs

7) Timer Capture

8) Serial Peripheral Interface (SPI)

9) Inter-Integrated Circuit (I2C)

10) Analog-to-Digital Conversion (ADC)

11) Digital-to-Analog Conversion (DAC)

Page 8: Engineering Portfolio of Isaac Bettendorf

FPGA and ASIC Design with VHDL Projects (ECE445/ECE448)General Description: There are seven projects in all but two of the projects were review exercises so they will not be presented here. The first project was part of the George Mason University class titled ECE445: Computer Organization. In this class, a MIPS processor was designed and created in VHDL with Xilinx ISE Design Suite 14.6 and then implemented on the Basys 2 Spartan-3E Trainer Board. The next four projects were part of the George Mason University class titled ECE448: FPGA and ASIC Design with VHDL and were designed and created in VHDL with Xilinx ISE Design Suite 14.7 and then implemented on the Nexys 3 Spartan-6 FPGA Trainer Board.

“Nexys 3 Spartan-6 FPGA Trainer Board (LIMITED TIME) >> see Nexys4 DDR,” Digilent. [Online]. Available: http://store.digilentinc.com/nexys-3-spartan-6-fpga-trainer-board-limited-time-see-nexys4-ddr/. [Accessed: 24-Dec-2016].

“Basys 2 Spartan-3E FPGA Trainer Board (LIMITED TIME) >>see Basys 3,” Digilent.

[Online]. Available: http://store.digilentinc.com/basys-2-spartan-3e-fpga-trainer-board-limited-time-see-basys-3/. [Accessed: 24-Dec-2016].

<< Figure 8: Basys 2 Spartan-3E FPGA Trainer Board

Figure 9: Nexys 3 Spartan-6 FPGA Trainer Board >>

Page 9: Engineering Portfolio of Isaac Bettendorf

FPGA and ASIC Design with VHDL Projects (ECE445/ECE448)Project Description and Concepts Learned:1. Fully Functioning MIPS Processor in VHDL (ECE445):

Basics of computer architecture design and assembly language.

2. Finite State Machine – Automated Teller Machine: Given set of requirements, designed and implemented finite state machines to carryout the required tasks. (Automated movie ticket teller)

3. VGA Display – Snake Game: Designed a version of Snakes (Snakes Game) and related digital circuits which allowed the game to be displayed on a VGA monitor.

4. Mandelbrot Fractal Viewer: Design digital circuit to plot a Mandelbrot fractal sets on VGA monitors.

5. Fast Sorting using PicoBlaze: Given a general datapathin the requirements that utilizes PicoBlaze, I designed a system that organized pseudo-random numbers and there corresponding memory addresses from least to greatest value.

Figure 10: Screenshot from Snake Game

Page 10: Engineering Portfolio of Isaac Bettendorf

Figure 11: four stage MOSFET amplifier with differential input

Microelectronics Circuit Design (ECE 333/433/431)General Description: During the courses of ECE333/433/431, multiple OrCAD PSPICE projects were assigned where both OrCAD Capture (circuit schematic construction of simulated circuit) or simple SPICE code was utilized and simulation results were calculated and displayed in PSPICE A/D. There were multiple simple assignments, but in ECE433 it was assigned to design a four stage differential amplifier which passed requirements in areas such as gain, phase margin, unit-gain bandwidth, slew rate, etc.

Four Stage Amplifier Description: Stage 01: Begins with a basic differential amplifier. (M1, M2, M3, M4)

Stage 02: Common source amplifier with C4 as a negative feedback route. (M7, M6)

Stage 03: Common drain amplifier. (M8, M9)

Stage 04: Common source amplifier. (M11, M10)

M12 and M5 are part of a current mirror used for biasing