ENG6090ENG6090Reconfigurable Reconfigurable

ComputingComputingSystemsSystems

Hardware Description Hardware Description Languages Part 6: Languages Part 6:

ConfigurationsConfigurations

TopicsTopics

Associating architectures to Associating architectures to entitiesentities

Default BindingDefault Binding Configuration SpecificationConfiguration Specification Configuration DeclarationConfiguration Declaration

ConfigurationsConfigurations

So far, we have seen that there are different ways in which to model the operation of digital circuit utilizing– Data flow– Behavioral– Structural

If you have different representations of one digital circuit (i.e. half adder or full adder).– Which architecture for the half adder should be

used? Is there a mechanism in VHDL to accomplish this?

ConfigurationsConfigurations

A design entity can have multiple alternative architectures

A configuration specifies the architecture that is to be used to implement a design entity

architecture-3

architecture-2

architecture-1

entity

binding

configuration

Configuration TechniquesConfiguration Techniques

The VHDL language provides configurations for explicitly associating an architecture description with each component in a structural model.– This process of association is referred to as bindingbinding an

instance of the component to an architecture.– In the absence of any programmer-supplied configuration

information, default bindingdefault binding rules apply.

There are several ways in which configuration can be provided:

– Configuration specificationConfiguration specification– Configuration declaration.Configuration declaration.

Component BindingComponent Binding

We are concerned with configuring the architecture and not the entity

Enhances sharing of designs: simply change the configuration

combinational logic

ab

z

carry

architecture gate_level of comb is

architecture behavioral of comb is

architecture low_power of comb is

architecture high_speed of comb is

Binding Information

D

Clk

Q

Q

R

Default Binding RulesDefault Binding Rules

If no configuration information is provided, then we can find a default architecture as follows:– If the entity name is the same as the component name,

then this entity is bound to the component.– If there are multiple architectures for the entity, then in

this case we use the last compiled architecture for the entity.

If no such entity with the same name is visible to the VHDL environment, then the binding is said to be deferreddeferred: that is no binding takes place now, but information will be forthcoming later.– This is akin to going ahead with wiring the rest of the

circuit and hoping that your partner comes up with the right chips before you are ready to run the experiment!!

Configuration SpecificationConfiguration Specification

Configuration specifications are used in the architecture body to identify the relationships between the components and the entity – architecture pairs used to model each component.

If we use a laboratory analogy, consider how we might specify the chips to be used for a component that we have declared.– We might specify the chip name and location, for

example, in the box labeled half adders in the grey cabinet.

How can we similarly define the exact location of an entity – architecture pair?

Configuration SpecificationConfiguration Specification

We can do so by naming the design library within which it is located and the name of the design unit within which such pairs are stored.

architecture structural of full_adder is----declare components heresignal s1, s2, s3: std_logic;---- configuration specificationfor H1: half_adder use entity WORK.half_adder (behavioral);for H2: half_adder use entity WORK.half_adder (structural);for O1: or_2 use entity POWER.lpo2 (behavioral)generic map (gate_delay => gate_delay)port map (I1 => a, I2 => b, Z=>c);begin -- component instantiation statementsH1: half_adder port map (a =>In1, b => In2, sum => s1, carry=> s2);H2: half_adder port map (a => s1, b => c_in, sum => sum, carry => s2);O1: or_2 port map (a => s2, b => s3, c => c_out);end structural;

library nameentity namearchitecture name

Configuration DeclarationConfiguration Declaration

Configuration specifications is part of the architecture: hence, we must be placing it within the architecture body.

Modification of our choice of models to implement a component requires editing the architecture and recompiling the model!!

A configuration declaration enables us to provide the same configuration information, but as a separate design unit and, if desired, in a separate file.

Suppose we take all of the configuration information provided in the previous slide, name it, and refer to it by its name.

This unit now becomes the configuration declaration and is a distinct design unit (like an entity, or architecture)

Configuration Configuration declarationdeclaration• A configuration is a design unit like entity, package

etc. Hence, it can be declared by itself.configuration_declaration <=

configuration id of entity_name is for architecture_name

{ for component_specificationbinding_indication;

end for; }end for;

end [ configuration ] id ;component_specification <=

( instantiation_label { , … } | others | all ) :

component_name;binding_indication <=

use entity entity_name [ ( architecture_id ) ]

Configuration Configuration DeclarationDeclaration

Written as a separate design unit Can be written to span a design hierarchy Use of the “for all” clause

configuration Config_A of full_adder is -- name the configuration-- for the entityfor structural -- name of the architecture being configuredfor H1: half_adder use entity WORK.half_adder (behavioral);end for;--for H2: half_adder use entity WORK.half_adder (structural);end for;--for O1: or_2 use entity POWER.lpo2 (behavioral)generic map(gate_delay => gate_delay)port map (I1 => a, I2 => b, Z=>c);end for;--end for;end Config_A;

ExampleExample

configuration reg4_gate_level of reg4 isfor struct

for bit0,bit1 : ffuse entity flipflop(behavior);

end for;for others : ff

use entity flipflop(struct);end for;

end for;end;

Default binding for ports

Design flowDesign flow

1. Partition design into sub-parts.

2. Define the interface between various sub-parts.

3. Construct components to specify the sub-parts.

4. Design actual implementations for the components.

5. Use configuration to integrate and simulate.

SummarySummary

The key issue to be understood here is that– Configurations are the language

mechanism that specifies a particular implementation when a myriad of alternative models is available for the constituent components.

– The use of configurations is motivated in part by the need to be able to reuse models and share models among developers