Research ArticleEnergy Efficient and High Speed Error Control Schemefor Real Time Wireless Sensor Networks

Ali Barati1 Ali Movaghar2 and Masoud Sabaei3

1 Department of Computer and Information Technology Engineering Qazvin Branch Islamic Azad University Qazvin Iran2Department of Computer Engineering Sharif University of Technology Tehran Iran3 Computer Engineering and Information Technology Department Amirkabir University of Technology Tehran Iran

Correspondence should be addressed to Ali Barati abaratiiaudacir

Received 5 October 2013 Revised 24 January 2014 Accepted 2 February 2014 Published 26 May 2014

Academic Editor Yong Jin

Copyright copy 2014 Ali Barati et alThis is an open access article distributed under theCreative CommonsAttribution License whichpermits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

Reliability and energy consumption are two of the main constraints in wireless sensor networks (WSNs) In this paper a novelenergy efficient and high speed error control scheme is introduced that is based on the Redundant Residue Number System (RRNS)allowing real-time application of WSNs The proposed approach employs a new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1 and an

efficient reverse converter which relies on the Mixed Radix Conversion (MRC) algorithm and achieves significant improvementsboth in terms of conversion delay and hardware design In order to obtain error controllability two-redundant-moduli set23119899+1

minus 1 24119899+1

minus 1 is also added to the main 3-moduli set The theoretical results backed by simulation tests confirm that thesolution put forward in this paper outperforms popular error control methods for WSNs in terms of error controllability energyefficiency and reduction of end-to-end delay

1 Introduction

Wireless sensor networks with a large number of multi-functional low power sensor nodes have a broad range ofapplications such as battlefield surveillance environmentalmonitoring disaster relief and healthcare [1ndash5] The maintask of wireless sensor networks is to collect the sensed datafrom environment and send them back to the sink node forfurther processing Because of the dynamic lossy and low-power nature of sensor networks two of the most importantconstraints that designers have to overcome in these networksare energy consumption and reliability [6] Moreover highspeed operation is another critical issue in real time wirelesssensor networks applications In-network data aggregationwhich is proposed for energy conservation [7] and errorcontrol schemes such as Automatic Repeat reQuest (ARQ)and Forward Error Correction (FEC) is used to improvereliability In ARQ-based schemes the receiver must detectlost packets and then request the sender to retransmit packets[8] In FEC codes to transmit data from sensor to thesink node each aggregator must decode the received data

aggregate them with new data and encrypt them againbefore sending to the sink node These operations cause asignificant end-to-end delay and high energy consumptionwhich leads to a decrease in the network lifetime Thereforeit is necessary to develop a new solution that offers both lowpower consumption and guaranteed reliability as well as lowend-to-end delay in real-time wireless sensor networks

In this paper authors utilize RRNS to design a reliableenergy-efficient and high speed algorithm for real time appli-cations of wireless sensor networks The proposed RRNS-based model offers desirable features including robust secu-rity an enhanced error detection and correction capabilityFurthermore the solution allows parallel operations and thusmaking real-time functionality as well as the use of low-power components possible By employing a 3-moduli set22119899+1

22119899+1

minus 1 2119899minus 1 and exploiting the MRC algorithm

an efficient reverse converter is designed Two redundant-moduli set 23119899+1 minus 1 2

4119899+1minus 1 is subsequently added to

the mentioned three main RNS moduli to create a 5-moduliRRNS set 22119899+1 22119899+1 minus 1 2

119899minus 1 23119899+1

minus 1 24119899+1

minus 1 This

Hindawi Publishing CorporationInternational Journal of Distributed Sensor NetworksVolume 2014 Article ID 698125 9 pageshttpdxdoiorg1011552014698125

2 International Journal of Distributed Sensor Networks

inclusion provides the new system with an effective errorcontrol capability

The rest of the paper is organized as follows a few ofrelated works are discussed in Section 2 In Section 3 a fulldescription of the proposed scheme is presented This isfollowed in Section 4 by a detailed explanation of an efficientreverse converter design and derivation of the necessaryexpressions In Section 5 error controllability of the proposedscheme is evaluated through simulation Finally the paper isconcluded in Section 6

2 Related Works

As was discussed in the introduction section error controlmethods in WSNs are divided into two general categoriesnamely Automatic Repeat reQuest (ARQ) and Forward ErrorCorrection (FEC) The ARQ method is used only for errordetection and once a corrupted data is sensed a request forinformation retransmission is made This approach is basedon Cyclic Redundancy Check (CRC) To set specificationsfor a CRC code it requires a generator of polynomial tobe defined This polynomial resembles the divisor in apolynomial long division which takes the message as thedividend and in which the quotient is discarded and theremainder becomes the result with the important distinctionthat the polynomial coefficients are calculated according tothe carry-less arithmetic of a finite field In order to makechecksum attach a polynomial generator to the packet beforeit is transmitted At the receiver if the division of the bitstream by119866(119909) generates no remainder then this is proof thattransmission has been free of error For each error-free packetreceived a positive acknowledgment (ACK) is sent back bythe receiver and for each corrupted packet received a negativeacknowledgment (NACK) is sent back by the receiver [9 10]

By adding redundancy to the sent data the FEC codeslet the receiver detect the errors and correct them by itselfOne of these codes is BCH which is represented by (119899 119896 119905)where ldquo119899rdquo refers to the length of the total sent bits ldquo119896rdquo denotesthe length of the main data and ldquo119905rdquo stands for the maximumnumber of the errors that could be corrected

In the age of modern wireless communications the needfor end-to-end reliable data transfer is growing incessantlyFortunately to ensure error free transmission a variety ofpopular error control techniques devoted to error detectionand correction have been published in the literature In whatfollows a number of these reported methods are examinedto ascertain how they achieve their objectives In [6 11] forexample we note that error control schemes in Bluetoothsensor networks were explored that is a low cost wirelesstechnology designed to facilitate the formation of ad hocnetworks In [11] authors studied an energy efficient modelfor adaptive and custom error control scheme and alsoinvestigated energy consumption and reliability constraintsof WSNs For custom coding they introduced new packettypes using some error control strategies These new packetsexploited CRC for error detection (without ARQ) BCH codewith and without CRC and the Hamming code with andwithout CRC They also unveiled two adaptive techniques

and a packet selection strategy that was based on channelstate The result of their analysis showed that error recoverywas energy efficient provided that the channel conditionswere known and a suitable control scheme was employedThis meant that with good channel conditions there was noneed to vary energy consumption and the use of packets withlittle or no error protection resulted in an efficient scenarioHowever for low values of signal to noise ratio (SNR) theBCH packet offered themost effective tool due to its ability tocorrect more errors in spite of higher energy consumptionThus under the circumstances where the error occurrenceprobability was high a more robust error recovery strategyhad to be employed for the network

Notice that the results obtained in [11] were only applica-ble to networks where designers had access to informationon the channel conditions Moreover power consumptionof the WSN had to be taken into account It is clear thatin situations where channel conditions are very vulnerablea robust error control scheme is the best choice But thefeasibility of this choice must be considered against energyconstraints of the givenWSNAnotherwork that also focusedon reliability in Bluetooth sensor networks was presentedby Khodadoustan et al [6] which included an attempt toestablish reliabilityenergy tradeoff in Bluetooth error controlscheme The paper investigated a combination of ARQ and aparticular CRC code known as CRC-CCITT and also carriedout an analysis of the data packets by using different BCHcodes Furthermore by conducting simulations authorsexamined the proposed coding techniquesrsquo performance asa result of changes in the number of hops and their effect onSNR The results of this study can help network designers todecide on suitable packet types and error control schemesTurning to [8 20] we find that researchersrsquo main interestswere in reliability for underwater wireless sensor networks(UWSNs) Sensors in underwater wireless sensor networksare often mobile and the channels are acoustic Such WSNshave low available bandwidth large propagation delays higherror probability and highly dynamic network topology [20]Thus error recovery is a major challenge in underwaterwireless sensor networks

Guo et al in [8] suggested the use of network coding inmultipath for UWSNs to achieve efficient error recovery inthe presence of high error probability An analytical evalua-tion of the performance of this scheme against several othererror-recovery systems revealed that this method was veryefficient in terms of error recovery and energy consumption

Segmented Data Reliable Transfer protocol (SDRT) wasanother solution that authors reported for UWSNs in [20]SDRT was a hybrid approach based on ARQ and FECtechniques which adopted efficient erasure codes wherebythe packets were transmitted block-by-block and hop-by-hop Moreover a mathematical model was subsequently putforward which achieved further energy saving and enableddesigners to set an appropriate size for the block for eachpacket By using this model the number of needed packetscould be accurately predicted

Iyer et al in [21] offered STCP protocol which is a reliableend-to-end transport protocol This protocol provides differ-ent levels of reliability in accordance with application that is

International Journal of Distributed Sensor Networks 3

it provides two levels of reliability for data flows for event-driven and continuous data flow applications When packetsare transmitted for event-driven applications and continuousdata flow applications ACK packets and NACK packets areused to indicate that the packets have reached the destinationrespectively Before transporting packets over STCP sensornodes transmit a Session Initiation packet to the base stationThis Session Initiation packet sends data such as the type ofdata flow transmission rate and number of flows to the basestationThe base station then stores this packet and sets timerand other parameters of this data flowWhen data is receivedthe base station sends a ACK message to make connectionWhen sensor node receives ACK it starts to transmit dataThe base station transmits ACK or NACK message basedon the type of the flow STCP transfers packets according tothe size of the window Also this method has a congestiondetection mechanism and employs occupancy monitoringof the queue of intermediate nodes The assumption in thispaper is that all network intermediate nodes have clockswhich are synchronized by sink

Marchi et al in [22] suggested a reliable transport proto-col called DTSNThis method provides two levels of reliabil-ity and is based on full reliability and differential reliabilityIf it is required that all packets are received at the destina-tion accurately full reliability is used otherwise differentialreliability is employed DTSN relies on Selective Repeat ARQand uses ACK and NACK to provide full reliability Packetstransmit data packets to destination in accordance withthe size of Acknowledgment Window (AW) Then ExplicitAcknowledgement Request is transmitted to destination Ifthe destination has received all the packets ACK packetwill be sent otherwise NACK packet will be sent DTSNprotocol adds Forward Error Correction (FEC) mechanismto provide differential reliability In this method a sessionis a sourcedestination relationship univocally identified bythe tuple ⟨source address destination address applicationidentifier session number⟩ designated the session identifierThe number of the session is selected randomly and thepackets of a session are numbered continuously Intermediatenodes store packets in their buffers and then transmit themso they are able to transmit them repeatedly if necessaryHowever when a large volume of data is transmitted a largememory is needed which is a problem

In all of the aforesaid schemes there is the need fordata decryption and encryption during the aggregation phaseusing secret key Thus these algorithms are very energy andtime deficient Moreover the security and confidentiality ofdata are in great peril because of decryption of the receivedpacket in each aggregator aggregation of the recovered mes-sagewith the new data and finally encryption of the new databy the aggregator that is to be sent to the sink In the proposedscheme security is preserved in each aggregator and there isno need to decrypt and then encrypt the data again in eachaggregator which results in notable conservation of energyand reduction of transmission time

In addition to these none of the above schemes consid-ered the ldquodelayrdquo parameter Although WSNs are immenselypopular but for real-time applications end-to-end delaybecomes a critical design issue In such circumstances if

delay turns out to be more than a fixed value the results andinformation will be useless It is clear therefore that methodspresented in [1 6 8 20] could not be adopted effectively andagain the technique explored in this paper is the one thatmeets the requirement for high speed operations

3 The Proposed Scheme

Minimizing energy dissipation and maximizing networklifetime are among the central concerns when designingapplications and protocols for sensor networks Clusteringhas been proven to be energy efficient in sensor networkssince data routing and relaying are only operated by clusterheads Besides cluster heads can process filter and aggregatedata sent by clustermembers and thus reducing network loadand alleviating the bandwidth

Residue number system is a nonweighted system thatemploys residue of numbers divided by several specificmoduli to represent them [23ndash25] Residue number systemcan be used for computational applications that need real-time processing such as digital signal processing [26] digitalfiltering [27] image processing [28] RSA encryption algo-rithm [29] and digital communications [30]

A residue number system is defined in terms of relativelyprime modulus set 119875

1 1198752 119875

119899 whose gcd(119875

119894 119875119895) = 1

for (119894 = 119895) In this system a weighted number 119883 can berepresented as (119909

1 1199092 119909

119899) where

119909119894= 119883 mod 119875

119894= |119883|119875119894 0 le 119909

119894lt 119875119894 (1)

Such a representation is unique for any integer 119883 in therange [0M) where119872 = prod

119899

119894=1119875119894is the dynamic range of the

modulus set 1198751 1198752 119875

119899 [31]

Redundant Residue Number system is specified bymoduli set 119898

1 1198982 1198983 119898

ℎ 119898ℎ+1

119898ℎ+119903

and 119898119894

gt

119898119894minus1

for 119894 = 2 3 ℎ + 119903 If all the moduli are set pair wiseprime the dynamic range of the system is [0119872 = prod

ℎ+119903

119894=1119898119894)

In the Redundant Residue Number system with ℎ + 119903

modulo 119883 where 120572 le 119883 lt 120572 + 119872 with ℎ + 119903 residue isrepresented as (119909

1 1199092 119909

ℎ 119909ℎ+1

119909ℎ+119903

) [32ndash34]Having studied a variety of literature on the issue of

error control in WSNs and the challenges it poses theproposed scheme has come upwith a solution that is based onRedundant Residue Number System (RRNS) The algorithmoffers many advantages and overcomes the weakness seen inother approaches Here each sensor in a cluster computesremainders of the sensed data using a predefinedmodulus setand sends the result that is data which is a smaller numbercompared to original data to the cluster head where thereceived numbers are then aggregated It is clear that sinceaggregation is being performed on remainders rather than onthe entire sensed data it allows for more compact processingunits to be utilized at reduced power consumption in clusterheads and also given that all aggregation operations takeplace in parallel this has the benefit of increasing the speednoticeably It should also be noted that unlike other methodsstudied where preaggregation decoding and postencodingare required in the proposed scheme these processes areunnecessary and only cluster head aggregation operation is

4 International Journal of Distributed Sensor Networks

Sink Cluster headSensor node

5 = ⟨2 | 1 | 0⟩

6 = ⟨0 | 2 | 1⟩ 7 = ⟨1 | 3 | 2⟩

16 = ⟨1 | 0 | 1⟩

12 = ⟨0 | 0 | 2⟩ 10 = ⟨1 | 2 | 0⟩

= ⟨5 | 8 | 6⟩RemaindersModuli set = 3 4 5

Resultoriginal message

| |||2 1 0

0 2 1

1 3 2

3 6 3

2 2 3

| ⟩⟩3 6 3|| ⟩⟩ | |

2 1 0

0 0 2

1 0 1| ⟩⟩2 2 3|| ⟩⟩

|⟨ ⟨5 8 6|| ⟩⟩

+

+

Figure 1 An example of data aggregation functionality using the proposed scheme

required It is therefore seen that this solution results in asignificant drop in end-to-end delay which makes it suitablefor real-time wireless sensor network applications

The proposed method for error control could be appliedto tree-like network topologies and cluster based networktopologies In tree-like network children transmit the residueof their sensed data that has been divided by the moduli setto their parent and their parent will aggregate the receivedresidues and his own residues Next the parent transmits theresult to his own parent This will continue until the residuesreach sink In a cluster-based network the members of thecluster transmit the residue of their sensed data divided bymoduli set to head cluster Then the head cluster aggregatesthe received residues and its own residues and transmits theresult to the next head clusters

In this study we considered 5 moduli 3 main and2 redundant Since wireless sensor networks are limitedin terms of energy processing power size memory selection of the number and value of moduli was madein a way that their reverse converters led to the lowestenergy consumption and delay How we select the mainmoduli determines the value of dynamic range (obtained byproduct of main moduli) In fact if we increase the dynamicrange it will allow us to represent larger numbers usingthe proposed method On the other hand increasing thenumber of redundant moduli results in higher capability oferror detection and correction Thus if 119905 redundant modulois considered 119905 modulo containing error can be detectedand lfloor1199052rfloor residue can be corrected However the increasein the number of the moduli leads to an increase in reverseconverter cost

An example illustrating the basic theme of the proposedscheme is shown below consisting of six sensors located intwo clusters Each cluster has three sensors and a cluster head

In this example aggregation is a summation operation wherethe remainders of 5 based on the moduli 3 4 5 are 2 1 0and the remainders of other sensed data are calculated inthe same way In the aggregators where summation takesplace all of the results received from the first modulo areadded together also as all of the results from the secondmodulo and so on for the thirdmoduloThis feature offers theadded advantage of requiring lower space for the arithmeticblock As can be seen in the sink node the final decryptedremainders are 5 8 6 and the modulus set is 3 4 5

Now in order to achieve a lower power consumptionand as compact a design as possible a new moduli set22119899+1

22119899+1

minus1 2119899minus1 replaces 3 4 5 in Figure 1 Moreover

the sink node using a reverse converter can decode themessage and recover the original data

Hence an efficient reverse converter is needed Thereare two basic approaches that convert a number from RNSto its binary equivalent These are the Chinese ReminderTheorem (CRT) and Mixed Radix Conversion (MRC) [6]with MRC algorithm being the preferred choice in thispaper Considering also that reliability in data delivery isan important issue in almost all wireless sensor networkapplications two-redundant-moduli set 23119899+1 minus 1 2

4119899+1minus 1

is added to the new 3-moduli set 22119899+1 22119899+1 minus 1 2119899minus 1

to further enhance error control capability of the proposedscheme It should be pointed out that the proposedmoduli setacts as secret key which is used by the sink node to decryptthe received remainders and obtain the original message Ifan adversary that has no knowledge of the moduli set couldacquire the transmitted packet it would not be able to decryptthe message It is clear that redundant residue number allowstransmit data to be encrypted by employing symmetric keyand thus provides a powerful tool for error bit detection aswell as an effective means for data correction

International Journal of Distributed Sensor Networks 5

4 Design and Implementation of ProposedResidue to Binary Converter

Various methods can be used to design a reverse converterThe most popular methods are MCR and CRT The use ofCRTorMRCdepends on selectedmoduli sincemultiplicativeinverse should be computed in both methods Computationof multiplicative inverse is the most difficult part of reverseconverterTherefore it is important to look for multiplicativeinverses that allow the formulation of the most simpleequations Certain moduli set can be designed well and atless cost by employingMCR since their multiplicative inverseis computed more easily through simplified (less complex)equations As a result the volume of required hardwareand consumption of energy as well as network delay are allreduced In this study we applied MRC Using this methodthe values of multiplicative inverse become so simpler andthe design of the reverse converter costs so much less

The residue to binary conversion can be performed usingthe MRC algorithm as follows

119883 = 119881119899

119899

prod119894=1

119875119894+ sdot sdot sdot + 119881

311987521198751+ 11988121198751+ 1198811 (2)

The coefficients V119894119875 can be obtained from residues by

1198811= 1199091

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752

(3)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753 (4)

In the general case we have

119881119899= (((119909

119899minus 1198811)10038161003816100381610038161003816119875minus1

1

10038161003816100381610038161003816119875119899minus 1198812)10038161003816100381610038161003816119875minus1

2

10038161003816100381610038161003816119875119899

minus sdot sdot sdot minus 119881119899minus1

)10038161003816100381610038161003816119875minus1

119899minus1|119875119899

10038161003816100381610038161003816119875119899

(5)

where |119875minus1119894|119875119895denotes the multiplicative inverse of 119875

119894modulo

119875119895 In mathematics a multiplicative inverse for a number119883 is

a number that when multiplied by119883 yields the multiplicativeidentity 1 The modular multiplicative inverse of a modulo119898can be derived from the extended Euclidean algorithm

According to (2)ndash(5) the proposed reverse converter canbe designed for the new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1

as followsConsider the 3-moduli set 119875

1 1198752 1198753 = 2

2119899+1 22119899+1

minus

1 2119899minus 1 with three corresponding residues (119909

1 1199092 1199093) In

order to design a residue to binary converter we first need toobtain the multiplicative inverse values and substitute thesevalues with the modulus set in the conversion algorithmformulas The resultant equations should then be simplifiedby using the arithmetic propertiesThe final conversion stageinvolves the implementation of these simplified equationsusing hardware components such as full adders and logicgatesThe following propositions are used to obtain the closedform expressions which will be the means to compute themultiplicative inverses based on the MRC algorithm

Proposition 1 The multiplicative inverse of (22119899+1) modulo(22119899+1

minus 1) is 1198961= 1

Proof One has1003816100381610038161003816100381622119899+11003816100381610038161003816100381622119899+1minus1

= 1 (6)

Proposition 2 The multiplicative inverse of (22119899+1) modulo(2119899minus 1) is 119896

2= 2119899minus1

Proof One has100381610038161003816100381610038162119899minus1

times 22119899+1100381610038161003816100381610038162119899minus1

=1003816100381610038161003816100381623119899100381610038161003816100381610038162119899minus1

= 1 (7)

Proposition 3 The multiplicative inverse of (22119899+1

minus 1)

modulo (2119899 minus 1) is 1198963= 1

Proof One has1003816100381610038161003816100381622119899+1

minus 1100381610038161003816100381610038162119899minus1

= 1 (8)

Therefore let the values lt 1198961= 1 119896

2= 2119899minus1

1198963

=

1 1198751= (22119899+1

) 1198752= (22119899+1

minus 1) and 1198753= (2119899minus 1) gt in

(2)ndash(4) and thus we have119883 = 119909

1+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)

(9)

1198811= 1199091 (10)

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1 (11)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753

=100381610038161003816100381610038162119899minus1

times ((1199093minus 1199091) + (minus119881

2))100381610038161003816100381610038162119899minus1

(12)

In order to design an efficient reverse converter expres-sions (9) and (11)-(12) can be rewritten as follows

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 +1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 11988121+ 11988122

(13)

where11988121

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 = 11990922119899

11990922119899minus1

sdot sdot sdot 11990920⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

11988122

=1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 12119899

12119899minus1

sdot sdot sdot 10⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

(14)

Now in order to implement 1198813on the basis of (12) we

have

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

100381610038161003816100381610038161003816P3

=100381610038161003816100381610038162119899minus1

times (1199093minus 1199091) minus 119881

2

100381610038161003816100381610038162119899minus1

= V31+ 11988132+ 11988133

(15)

6 International Journal of Distributed Sensor Networks

where

11988131

=100381610038161003816100381610038162119899minus1

times 1199093

100381610038161003816100381610038162119899minus1= 11990930⏟⏟⏟⏟⏟⏟⏟1bit

1199093119899minus1

sdot sdot sdot 11990931⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(119899minus1)bits

11988132

=10038161003816100381610038161003816minus2119899minus1

times 1199091

100381610038161003816100381610038162119899minus1=

10

1119899minus1

sdot sdot sdot 11

1119899

12119899minus1

sdot sdot sdot 1119899+1

+

12119899⏟⏟⏟⏟⏟⏟⏟1bit

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

11988133

=1003816100381610038161003816minus1198812

10038161003816100381610038162119899minus1 =

2119899minus1

sdot sdot sdot 2120

22119899minus1

sdot sdot sdot 2119899+1

2119899+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

22119899⏟⏟⏟⏟⏟⏟⏟1bit

(16)

Finally to obtain119883 based on (9) we have

119883 = 1199091+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119862

= 1199091+ (22119899+1

) 119862

119862 = 1198812+ (22119899+1

minus 1)1198813

119862 =

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞1198813119899minus1

sdot sdot sdot 11988130

(119899+1)bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞11988122119899

11988122119899minus1

sdot sdot sdot 1198812119899

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞3119899minus1

sdot sdot sdot 30

+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(2119899+1)bits

1198812119899minus1

sdot sdot sdot 11988120⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119899bits

119883 = 1199091+ (22119899+1

) 119862 = Concatenation (1199091 119862)

(17)

The area and delay specifications for the proposed reverseconverter are shown in Table 1

From this Table we have

Total area = (7119899 + 3)119860FA + (5119899 + 2)119860NOT

+ (4119899 minus 1)119860OR + (4119899 minus 1)119860XNOR

Total delay = (9119899 + 8) 119905FA + 3119905NOT

(18)

Now let us discuss comparison of the proposed reverseconverterrsquos performance for the newmoduli set 22119899+1 22119899+1minus1 2119899minus1 against competing models that have either the same

or a lower dynamic range in terms of hardware requirementand speed of operations It should be noted that in any reverseconverter most of the delay is associated with full adderswhich also occupy the largest area allocated to componentsassembly Thus for the sake of comparison it is sufficient toinvestigate only 119860FA and 119905FA see Table 2

5 Performance Evaluation

In this section the performance of the proposed moduli set22119899+1

22119899+1

minus1 2119899minus1 23119899+1

minus1 24119899+1

minus1 is evaluated in termsof error detection and error correction capabilities Evalua-tion of the error control capability requires an investigation of

Table 1 Characterization of each part of the proposed reverseconverter

Parts FA NOT ANDXOR ORXNOR DelayOPU 1 mdash (2119899 + 1) mdash mdash 119905NOT

CPA 1 (2119899 + 1) mdash mdash mdash (4119899 + 2)119905FA

CSA 1 119873 mdash mdash mdash 119905FA

CSA 2 1 mdash mdash (119899 minus 1) 119905FA

OPU 2 mdash (2119899 + 1) mdash mdash 119905NOT

CSA 3 119873 mdash mdash mdash 119905FA

CSA 4 119873 mdash mdash mdash 119905FA

CSA 5 1 mdash mdash (119899 minus 1) 119905FA

CPA 2 119873 mdash mdash mdash (2119899)119905FA

OPU 3 mdash 119873 mdash mdash 119905NOT

119877minus CPA 119873 mdash mdash (2119899 + 1) (3119899 + 1)119905FA

Table 2 Area and Delay comparison

Reverse converter Area (119860FA) Delay (119905FA)[12] 8119899 + 2 12119899 + 5

[13] (51198992+ 43119899)6 + 16119899 minus 1 18119899 + 7

[14] 10119899 + 5 13119899 + 1

[15] 125119899 + 6 12119899 + 6

[16] 10119899 + 5 12119899 + 1

[17]-1 9119899 + 5 115119899 + 6

[17]-2 1198992+ 12119899 + 12 16119899 + 22

[17]-3 9119899 + 10 11119899 + 14

[18] 11989922 + 11119899 + 14 11119899 + 8

[19]-CICE 251198992+ 255119899 + 12 18119899 + 23

[19]-CIHS 251198992+ 375119899 + 28 12119899 + 15

[19]-C2CE 20119899 + 17 13119899 + 22

[19]-C3CE 23119899 + 11 16119899 + 14

Proposed 7119899 + 3 9119899 + 8

the effectiveness of the employed ldquoerror correctionrdquo approachIn general an error control technique is divided into twoparts ldquoerror detectionrdquo and ldquoerror detection and correctionrdquoFor simplicityrsquos sake here we refer to ldquoerror correctionrdquo tomean both error detection and correction noting that errorbits must first be detected and located before they can becorrected Referring to the residue number system one of itsfeatures is that it can correct ldquoburst errorsrdquo

This means that if error bits are residing in one modulothe error control algorithm can easily detect and correctthem However when error bits are located in more thanone modulo they cannot be corrected although it may bepossible to detect them So the aim now is to discover whatthe average percentage of error detection is when error bitsreside in more than one modulo by employing the proposedRNS based solution

In the proposedmoduli set 22119899+1 22119899+1minus1 2119899minus1 23119899+1minus1 24119899+1

minus 1 22119899+1 22119899+1 minus 1 2119899minus 1 are the main three and

23119899+1

minus 1 24119899+1

minus 1 are the redundant moduli respectivelyNow the first second and third main moduli are (2119899 +

1) (2119899+1) and (119899) bits respectively Given this architecturethe error bits can only be detected and corrected if (a) they are

International Journal of Distributed Sensor Networks 7

Table 3 Area and delay comparison

119873 Main modulus Redundant Modulus Maximum error correction Error detection capabilityError bits in one modulo Error bits in two modulus

2 32 31 3 127 511 5 bits 100 99373 128 127 7 1023 8191 7 bits 100 1004 512 511 15 8191 131071 9 bits 100 100

placed either in the first the second or the third modulo (b)maximum error bit count does not exceed (2119899 + 1) (2119899 + 1)and (119899) respectively Hence the maximum achievable errorcorrection capability is equal to (2119899 + 1) error bits occurringin the first or the second modulo On the other hand theminimum correction capability that can be achieved usingthe proposed modulus set is equal to one error bit within anymodulo of the received packet

In the proposed error control method first sensed dataare divided by the proposed moduli set and then the residuesare computed Next the nodes transmit the residues insteadof sensed data After receiving residues sink computes theoriginal data using 3mainmoduli and their received residuesWhen the residue of the computed number has been dividedby redundant moduli and the received residues for thoseredundantmoduli are not equal an error is detected and errorcorrection procedure is called for it Sink can reconstructthe original data using 3 residues out of the 5 residues andMRC reverse converterThere are only 10 possible conditionsfor selecting 3 residues out of 5 residues (1198625

3= ( 53) =

(5(2 lowast 3)) = 10) Sink computes the original data forall of these possible conditions Given the fact that duringdata transfer some residuesmay have contained errors not allsink computed numbers are accurate and equalThus amongthese 10 numbers those out of dynamic range are removedAfter a voting process those numbers that have received thegreatest votes are selected as correct numbers

In order to gauge the error detection capability of theproposed set in a situation where errors occur in morethan one modulo and where therefore no correction ispossible we simulated the behavior of the error controlalgorithm using C++ programming language The experi-ment runs 3010158400001015840000 different error bit states by setting119899 = 2 3 4 Substituting these values for 119899 in the setwe obtain 32 31 3 127 511 128 127 7 1023 8191 and512 511 15 8191 131071 respectively The test results aredisplayed in Table 3 Note that themaximum error correctionis equal to (2119899 + 1) bits as was mentioned before and thethree error states considered are bits which are located in oneof the main modulus (correction is possible and detection is100) bits which are located in two moduli and finally thecase where bits are resided in three moduli

With reference to Table 3 there are several individualconditions for error detection among the 5 received residuesonly 1 residue contains error 2 residues contain error 3residues contain error Since 2 redundant moduli have beenconsidered for this moduli set error correction of a receivedresidue is possible It makes no difference whether just oneor all bits of the modulo are damaged this can be correctedBased on the damaged bits of the residues we will have

different conditions (eg it is possible that the first andsecond bits the first and third bits or any other combinationof bits are damaged) simulation in C++ language considersall these conditions All possible conditions are simulatedfor 119899 = 2 (ie moduli set 32 31 3 127 511) for 119899 = 3

(ie moduli set 128 127 7 1023 8191) and for 119899 = 4 (iemoduli set 512 511 15 8191 131071 and each time a partof data was damaged intentionally to investigate detectionand correction capability of the method Table 3 displayserror detection percentage for different values of 119899 It alsogives the most number of bits of a modulus that are correctedfor various 119899 values

We evaluated the proposed scheme throughNS-2 simula-tion tool [35] We considered a randomly deployed networkthat is one hundred nodes that were initially spread over anarea of 100 square meters in a random manner The radiocoverage of each sensor node and sink was assumed to bea circular area of 100m in diameter The antenna modeldeployed was omnidirectional Also the initial energy ofsensor nodes set to 01 Joule

The proposed scheme was analyzed in terms of energyconsumption end-to-end delay and network lifetime usingSTCP [21] DTSN [22] TCP and Reed Solomon Table 4shows the simulation parameters

All simulations were repeated 10 times before calculatingthe average of the results As illustrated in Figure 2 the sim-ulation results confirm that the proposed scheme consumessignificantly less energy than the other schemes investigatedIn Figure 3 end-to-end delay is examined where it can beseen that the proposed scheme generates less network delayFinally in Figure 4 it is easy to see that the proposed schemeoutperforms its counterparts in terms of network lifetime

6 Conclusion

In this paper authors unveiled an innovative energy-efficientalgorithm for real time wireless sensor networks that wasbased on a new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1 By

exploiting the MRC technique an efficient reverse converterwas also designed which overcame two-key constraintsnamely component space and high speed operation In orderto take full advantage of the error controllability property ofthe proposed solution two-redundant-moduli sets were thenadded to the initial three main sets resulting in a combinedset 22119899+1 22119899+1 minus 1 2

119899minus 1 23119899+1

minus 1 24119899+1

minus 1

The new methodrsquos error correction capability was foundto be (2119899 + 1) bits under the ideal condition and errordetection improvement reached a figure of 9901 under theworst case scenario condition and 100 when (119899 ge 3)

8 International Journal of Distributed Sensor Networks

0

05

1

15

2

25

3

TCP STCP DTSN RS(15 9 7) Proposedmethod

Tota

l ene

rgy

cons

umpt

ion

(J)

Figure 2 Total energy consumption

250260270280290300310320330340

TCP STCP DTSN RS(15 9 7) Proposedmethod

End-

to-e

nd d

elay

(s)

Figure 3 End-to-end delay

Table 4 Simulation parameters

Area of sensor field 100 lowast 100m2

Antenna model OmnidirectionalSimulation time 1000 SRadio range of a sensor node 100mNumber of sensor nodes 100Initial energy 01 JInterface queue type DroptailInterface queue (IFQ) length 50 PacketsEnergy model Battery

By simulating the proposed error control scheme usingan ns-2 network simulation tool and making comparisonsagainst some popular methods outperformance in terms ofreductions of energy consumption and end-to-end delay aswell as extension of network lifetime was clearly evidentThese advantages therefore make the proposed methodmoredesirable for real-time wireless sensor network applicationswhere reliability low energy consumption and high speedoperations are absolute necessities

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

86889092949698

100102104106

TCP STCP DTSN RS(15 9 7) Proposedmethod

Aver

age l

ifetim

e (s)

Figure 4 Average network lifetime

References

[1] G Song Y Zhou F Ding and A Song ldquoA mobile sensornetwork system for monitoring of unfriendly environmentsrdquoSensors vol 8 no 11 pp 7259ndash7274 2008

[2] J Lloret M Garcia D Bri and S Sendra ldquoA wireless sensornetwork deployment for rural and forest fire detection andverificationrdquo Sensors vol 9 no 11 pp 8722ndash8747 2009

[3] M Dunbabin and L Marques ldquoRobots for environmentalmonitoring significant advancements and applicationsrdquo IEEERobotics and Automation Magazine vol 19 no 1 pp 24ndash392012

[4] P Kumar S-G Lee and H-J Lee ldquoE-SAP efficient-strongauthentication protocol for healthcare applications using wire-less medical sensor networksrdquo Sensors vol 12 no 2 pp 1625ndash1647 2012

[5] Y-M Hong H-C Lin and Y-C Kan ldquoUsing wireless sensornetwork on real-time remote monitoring of the load cell forlandsliderdquo Sensor Letters vol 9 no 5 pp 1911ndash1915 2011

[6] S Khodadoustan F Jalali and A Ejlali ldquoReliabilityenergytrade-off in Bluetooth error control schemesrdquo MicroelectronicsReliability vol 51 no 8 pp 1398ndash1412 2011

[7] J Yick B Mukherjee and D Ghosal ldquoWireless sensor networksurveyrdquoComputerNetworks vol 52 no 12 pp 2292ndash2330 2008

[8] Z Guo B Wang P Xie W Zeng and J-H Cui ldquoEfficient errorrecovery with network coding in underwater sensor networksrdquoAd Hoc Networks vol 7 no 4 pp 791ndash802 2009

[9] I F Akyildiz and M C Vuran Wireless Sensor Networks JohnWiley amp Sons Chichester UK 2010

[10] E Cayırcı and C Rong Security in Wireless Ad Hoc and SensorNetworks John Wiley amp Sons Chichester UK 2009

[11] J H Kleinschmidt W C Borelli and M E Pellenz ldquoAnenergy efficiency model for adaptive and custom error controlschemes in Bluetooth sensor networksrdquo International Journal ofElectronics and Communications (AEU) vol 63 no 3 pp 188ndash199 2009

[12] A S Molahosseini K Navi C Dadkhah O Kavehei and STimarchi ldquoEfficient reverse converter designs for the new 4-moduli sets 2

119899minus 1 2

119899 2119899+ 1 2

2119899+1minus 1 and 2

119899minus 1 2

119899+

1 22119899 22119899+1 based onnewCRTsrdquo IEEETransactions onCircuits

and Systems I vol 57 no 4 pp 823ndash835 2010[13] B Cao C-H Chang and T Srikanthan ldquoA residue-to-binary

converter for a new five-moduli setrdquo IEEE Transactions onCircuits and Systems I vol 54 no 5 pp 1041ndash1049 2007

[14] A S Molahosseini C Dadkhah and K Navi ldquoA new five-moduli set for efficient hardware implementation of the reverse

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

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Journal ofEngineeringVolume 2014

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Shock and Vibration

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Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

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Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

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Advances inOptoElectronics

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Chemical EngineeringInternational Journal of

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Control Scienceand Engineering

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Antennas andPropagation

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Navigation and Observation

International Journal of

International Journal of Distributed Sensor Networks 3

it provides two levels of reliability for data flows for event-driven and continuous data flow applications When packetsare transmitted for event-driven applications and continuousdata flow applications ACK packets and NACK packets areused to indicate that the packets have reached the destinationrespectively Before transporting packets over STCP sensornodes transmit a Session Initiation packet to the base stationThis Session Initiation packet sends data such as the type ofdata flow transmission rate and number of flows to the basestationThe base station then stores this packet and sets timerand other parameters of this data flowWhen data is receivedthe base station sends a ACK message to make connectionWhen sensor node receives ACK it starts to transmit dataThe base station transmits ACK or NACK message basedon the type of the flow STCP transfers packets according tothe size of the window Also this method has a congestiondetection mechanism and employs occupancy monitoringof the queue of intermediate nodes The assumption in thispaper is that all network intermediate nodes have clockswhich are synchronized by sink

Marchi et al in [22] suggested a reliable transport proto-col called DTSNThis method provides two levels of reliabil-ity and is based on full reliability and differential reliabilityIf it is required that all packets are received at the destina-tion accurately full reliability is used otherwise differentialreliability is employed DTSN relies on Selective Repeat ARQand uses ACK and NACK to provide full reliability Packetstransmit data packets to destination in accordance withthe size of Acknowledgment Window (AW) Then ExplicitAcknowledgement Request is transmitted to destination Ifthe destination has received all the packets ACK packetwill be sent otherwise NACK packet will be sent DTSNprotocol adds Forward Error Correction (FEC) mechanismto provide differential reliability In this method a sessionis a sourcedestination relationship univocally identified bythe tuple ⟨source address destination address applicationidentifier session number⟩ designated the session identifierThe number of the session is selected randomly and thepackets of a session are numbered continuously Intermediatenodes store packets in their buffers and then transmit themso they are able to transmit them repeatedly if necessaryHowever when a large volume of data is transmitted a largememory is needed which is a problem

In all of the aforesaid schemes there is the need fordata decryption and encryption during the aggregation phaseusing secret key Thus these algorithms are very energy andtime deficient Moreover the security and confidentiality ofdata are in great peril because of decryption of the receivedpacket in each aggregator aggregation of the recovered mes-sagewith the new data and finally encryption of the new databy the aggregator that is to be sent to the sink In the proposedscheme security is preserved in each aggregator and there isno need to decrypt and then encrypt the data again in eachaggregator which results in notable conservation of energyand reduction of transmission time

In addition to these none of the above schemes consid-ered the ldquodelayrdquo parameter Although WSNs are immenselypopular but for real-time applications end-to-end delaybecomes a critical design issue In such circumstances if

delay turns out to be more than a fixed value the results andinformation will be useless It is clear therefore that methodspresented in [1 6 8 20] could not be adopted effectively andagain the technique explored in this paper is the one thatmeets the requirement for high speed operations

3 The Proposed Scheme

Minimizing energy dissipation and maximizing networklifetime are among the central concerns when designingapplications and protocols for sensor networks Clusteringhas been proven to be energy efficient in sensor networkssince data routing and relaying are only operated by clusterheads Besides cluster heads can process filter and aggregatedata sent by clustermembers and thus reducing network loadand alleviating the bandwidth

Residue number system is a nonweighted system thatemploys residue of numbers divided by several specificmoduli to represent them [23ndash25] Residue number systemcan be used for computational applications that need real-time processing such as digital signal processing [26] digitalfiltering [27] image processing [28] RSA encryption algo-rithm [29] and digital communications [30]

A residue number system is defined in terms of relativelyprime modulus set 119875

1 1198752 119875

119899 whose gcd(119875

119894 119875119895) = 1

for (119894 = 119895) In this system a weighted number 119883 can berepresented as (119909

1 1199092 119909

119899) where

119909119894= 119883 mod 119875

119894= |119883|119875119894 0 le 119909

119894lt 119875119894 (1)

Such a representation is unique for any integer 119883 in therange [0M) where119872 = prod

119899

119894=1119875119894is the dynamic range of the

modulus set 1198751 1198752 119875

119899 [31]

Redundant Residue Number system is specified bymoduli set 119898

1 1198982 1198983 119898

ℎ 119898ℎ+1

119898ℎ+119903

and 119898119894

gt

119898119894minus1

for 119894 = 2 3 ℎ + 119903 If all the moduli are set pair wiseprime the dynamic range of the system is [0119872 = prod

ℎ+119903

119894=1119898119894)

In the Redundant Residue Number system with ℎ + 119903

modulo 119883 where 120572 le 119883 lt 120572 + 119872 with ℎ + 119903 residue isrepresented as (119909

1 1199092 119909

ℎ 119909ℎ+1

119909ℎ+119903

) [32ndash34]Having studied a variety of literature on the issue of

error control in WSNs and the challenges it poses theproposed scheme has come upwith a solution that is based onRedundant Residue Number System (RRNS) The algorithmoffers many advantages and overcomes the weakness seen inother approaches Here each sensor in a cluster computesremainders of the sensed data using a predefinedmodulus setand sends the result that is data which is a smaller numbercompared to original data to the cluster head where thereceived numbers are then aggregated It is clear that sinceaggregation is being performed on remainders rather than onthe entire sensed data it allows for more compact processingunits to be utilized at reduced power consumption in clusterheads and also given that all aggregation operations takeplace in parallel this has the benefit of increasing the speednoticeably It should also be noted that unlike other methodsstudied where preaggregation decoding and postencodingare required in the proposed scheme these processes areunnecessary and only cluster head aggregation operation is

4 International Journal of Distributed Sensor Networks

Sink Cluster headSensor node

5 = ⟨2 | 1 | 0⟩

6 = ⟨0 | 2 | 1⟩ 7 = ⟨1 | 3 | 2⟩

16 = ⟨1 | 0 | 1⟩

12 = ⟨0 | 0 | 2⟩ 10 = ⟨1 | 2 | 0⟩

= ⟨5 | 8 | 6⟩RemaindersModuli set = 3 4 5

Resultoriginal message

| |||2 1 0

0 2 1

1 3 2

3 6 3

2 2 3

| ⟩⟩3 6 3|| ⟩⟩ | |

2 1 0

0 0 2

1 0 1| ⟩⟩2 2 3|| ⟩⟩

|⟨ ⟨5 8 6|| ⟩⟩

+

+

Figure 1 An example of data aggregation functionality using the proposed scheme

required It is therefore seen that this solution results in asignificant drop in end-to-end delay which makes it suitablefor real-time wireless sensor network applications

The proposed method for error control could be appliedto tree-like network topologies and cluster based networktopologies In tree-like network children transmit the residueof their sensed data that has been divided by the moduli setto their parent and their parent will aggregate the receivedresidues and his own residues Next the parent transmits theresult to his own parent This will continue until the residuesreach sink In a cluster-based network the members of thecluster transmit the residue of their sensed data divided bymoduli set to head cluster Then the head cluster aggregatesthe received residues and its own residues and transmits theresult to the next head clusters

In this study we considered 5 moduli 3 main and2 redundant Since wireless sensor networks are limitedin terms of energy processing power size memory selection of the number and value of moduli was madein a way that their reverse converters led to the lowestenergy consumption and delay How we select the mainmoduli determines the value of dynamic range (obtained byproduct of main moduli) In fact if we increase the dynamicrange it will allow us to represent larger numbers usingthe proposed method On the other hand increasing thenumber of redundant moduli results in higher capability oferror detection and correction Thus if 119905 redundant modulois considered 119905 modulo containing error can be detectedand lfloor1199052rfloor residue can be corrected However the increasein the number of the moduli leads to an increase in reverseconverter cost

An example illustrating the basic theme of the proposedscheme is shown below consisting of six sensors located intwo clusters Each cluster has three sensors and a cluster head

In this example aggregation is a summation operation wherethe remainders of 5 based on the moduli 3 4 5 are 2 1 0and the remainders of other sensed data are calculated inthe same way In the aggregators where summation takesplace all of the results received from the first modulo areadded together also as all of the results from the secondmodulo and so on for the thirdmoduloThis feature offers theadded advantage of requiring lower space for the arithmeticblock As can be seen in the sink node the final decryptedremainders are 5 8 6 and the modulus set is 3 4 5

Now in order to achieve a lower power consumptionand as compact a design as possible a new moduli set22119899+1

22119899+1

minus1 2119899minus1 replaces 3 4 5 in Figure 1 Moreover

the sink node using a reverse converter can decode themessage and recover the original data

Hence an efficient reverse converter is needed Thereare two basic approaches that convert a number from RNSto its binary equivalent These are the Chinese ReminderTheorem (CRT) and Mixed Radix Conversion (MRC) [6]with MRC algorithm being the preferred choice in thispaper Considering also that reliability in data delivery isan important issue in almost all wireless sensor networkapplications two-redundant-moduli set 23119899+1 minus 1 2

4119899+1minus 1

is added to the new 3-moduli set 22119899+1 22119899+1 minus 1 2119899minus 1

to further enhance error control capability of the proposedscheme It should be pointed out that the proposedmoduli setacts as secret key which is used by the sink node to decryptthe received remainders and obtain the original message Ifan adversary that has no knowledge of the moduli set couldacquire the transmitted packet it would not be able to decryptthe message It is clear that redundant residue number allowstransmit data to be encrypted by employing symmetric keyand thus provides a powerful tool for error bit detection aswell as an effective means for data correction

International Journal of Distributed Sensor Networks 5

4 Design and Implementation of ProposedResidue to Binary Converter

Various methods can be used to design a reverse converterThe most popular methods are MCR and CRT The use ofCRTorMRCdepends on selectedmoduli sincemultiplicativeinverse should be computed in both methods Computationof multiplicative inverse is the most difficult part of reverseconverterTherefore it is important to look for multiplicativeinverses that allow the formulation of the most simpleequations Certain moduli set can be designed well and atless cost by employingMCR since their multiplicative inverseis computed more easily through simplified (less complex)equations As a result the volume of required hardwareand consumption of energy as well as network delay are allreduced In this study we applied MRC Using this methodthe values of multiplicative inverse become so simpler andthe design of the reverse converter costs so much less

The residue to binary conversion can be performed usingthe MRC algorithm as follows

119883 = 119881119899

119899

prod119894=1

119875119894+ sdot sdot sdot + 119881

311987521198751+ 11988121198751+ 1198811 (2)

The coefficients V119894119875 can be obtained from residues by

1198811= 1199091

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752

(3)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753 (4)

In the general case we have

119881119899= (((119909

119899minus 1198811)10038161003816100381610038161003816119875minus1

1

10038161003816100381610038161003816119875119899minus 1198812)10038161003816100381610038161003816119875minus1

2

10038161003816100381610038161003816119875119899

minus sdot sdot sdot minus 119881119899minus1

)10038161003816100381610038161003816119875minus1

119899minus1|119875119899

10038161003816100381610038161003816119875119899

(5)

where |119875minus1119894|119875119895denotes the multiplicative inverse of 119875

119894modulo

119875119895 In mathematics a multiplicative inverse for a number119883 is

a number that when multiplied by119883 yields the multiplicativeidentity 1 The modular multiplicative inverse of a modulo119898can be derived from the extended Euclidean algorithm

According to (2)ndash(5) the proposed reverse converter canbe designed for the new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1

as followsConsider the 3-moduli set 119875

1 1198752 1198753 = 2

2119899+1 22119899+1

minus

1 2119899minus 1 with three corresponding residues (119909

1 1199092 1199093) In

order to design a residue to binary converter we first need toobtain the multiplicative inverse values and substitute thesevalues with the modulus set in the conversion algorithmformulas The resultant equations should then be simplifiedby using the arithmetic propertiesThe final conversion stageinvolves the implementation of these simplified equationsusing hardware components such as full adders and logicgatesThe following propositions are used to obtain the closedform expressions which will be the means to compute themultiplicative inverses based on the MRC algorithm

Proposition 1 The multiplicative inverse of (22119899+1) modulo(22119899+1

minus 1) is 1198961= 1

Proof One has1003816100381610038161003816100381622119899+11003816100381610038161003816100381622119899+1minus1

= 1 (6)

Proposition 2 The multiplicative inverse of (22119899+1) modulo(2119899minus 1) is 119896

2= 2119899minus1

Proof One has100381610038161003816100381610038162119899minus1

times 22119899+1100381610038161003816100381610038162119899minus1

=1003816100381610038161003816100381623119899100381610038161003816100381610038162119899minus1

= 1 (7)

Proposition 3 The multiplicative inverse of (22119899+1

minus 1)

modulo (2119899 minus 1) is 1198963= 1

Proof One has1003816100381610038161003816100381622119899+1

minus 1100381610038161003816100381610038162119899minus1

= 1 (8)

Therefore let the values lt 1198961= 1 119896

2= 2119899minus1

1198963

=

1 1198751= (22119899+1

) 1198752= (22119899+1

minus 1) and 1198753= (2119899minus 1) gt in

(2)ndash(4) and thus we have119883 = 119909

1+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)

(9)

1198811= 1199091 (10)

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1 (11)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753

=100381610038161003816100381610038162119899minus1

times ((1199093minus 1199091) + (minus119881

2))100381610038161003816100381610038162119899minus1

(12)

In order to design an efficient reverse converter expres-sions (9) and (11)-(12) can be rewritten as follows

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 +1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 11988121+ 11988122

(13)

where11988121

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 = 11990922119899

11990922119899minus1

sdot sdot sdot 11990920⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

11988122

=1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 12119899

12119899minus1

sdot sdot sdot 10⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

(14)

Now in order to implement 1198813on the basis of (12) we

have

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

100381610038161003816100381610038161003816P3

=100381610038161003816100381610038162119899minus1

times (1199093minus 1199091) minus 119881

2

100381610038161003816100381610038162119899minus1

= V31+ 11988132+ 11988133

(15)

6 International Journal of Distributed Sensor Networks

where

11988131

=100381610038161003816100381610038162119899minus1

times 1199093

100381610038161003816100381610038162119899minus1= 11990930⏟⏟⏟⏟⏟⏟⏟1bit

1199093119899minus1

sdot sdot sdot 11990931⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(119899minus1)bits

11988132

=10038161003816100381610038161003816minus2119899minus1

times 1199091

100381610038161003816100381610038162119899minus1=

10

1119899minus1

sdot sdot sdot 11

1119899

12119899minus1

sdot sdot sdot 1119899+1

+

12119899⏟⏟⏟⏟⏟⏟⏟1bit

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

11988133

=1003816100381610038161003816minus1198812

10038161003816100381610038162119899minus1 =

2119899minus1

sdot sdot sdot 2120

22119899minus1

sdot sdot sdot 2119899+1

2119899+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

22119899⏟⏟⏟⏟⏟⏟⏟1bit

(16)

Finally to obtain119883 based on (9) we have

119883 = 1199091+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119862

= 1199091+ (22119899+1

) 119862

119862 = 1198812+ (22119899+1

minus 1)1198813

119862 =

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞1198813119899minus1

sdot sdot sdot 11988130

(119899+1)bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞11988122119899

11988122119899minus1

sdot sdot sdot 1198812119899

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞3119899minus1

sdot sdot sdot 30

+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(2119899+1)bits

1198812119899minus1

sdot sdot sdot 11988120⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119899bits

119883 = 1199091+ (22119899+1

) 119862 = Concatenation (1199091 119862)

(17)

The area and delay specifications for the proposed reverseconverter are shown in Table 1

From this Table we have

Total area = (7119899 + 3)119860FA + (5119899 + 2)119860NOT

+ (4119899 minus 1)119860OR + (4119899 minus 1)119860XNOR

Total delay = (9119899 + 8) 119905FA + 3119905NOT

(18)

Now let us discuss comparison of the proposed reverseconverterrsquos performance for the newmoduli set 22119899+1 22119899+1minus1 2119899minus1 against competing models that have either the same

or a lower dynamic range in terms of hardware requirementand speed of operations It should be noted that in any reverseconverter most of the delay is associated with full adderswhich also occupy the largest area allocated to componentsassembly Thus for the sake of comparison it is sufficient toinvestigate only 119860FA and 119905FA see Table 2

5 Performance Evaluation

In this section the performance of the proposed moduli set22119899+1

22119899+1

minus1 2119899minus1 23119899+1

minus1 24119899+1

minus1 is evaluated in termsof error detection and error correction capabilities Evalua-tion of the error control capability requires an investigation of

Table 1 Characterization of each part of the proposed reverseconverter

Parts FA NOT ANDXOR ORXNOR DelayOPU 1 mdash (2119899 + 1) mdash mdash 119905NOT

CPA 1 (2119899 + 1) mdash mdash mdash (4119899 + 2)119905FA

CSA 1 119873 mdash mdash mdash 119905FA

CSA 2 1 mdash mdash (119899 minus 1) 119905FA

OPU 2 mdash (2119899 + 1) mdash mdash 119905NOT

CSA 3 119873 mdash mdash mdash 119905FA

CSA 4 119873 mdash mdash mdash 119905FA

CSA 5 1 mdash mdash (119899 minus 1) 119905FA

CPA 2 119873 mdash mdash mdash (2119899)119905FA

OPU 3 mdash 119873 mdash mdash 119905NOT

119877minus CPA 119873 mdash mdash (2119899 + 1) (3119899 + 1)119905FA

Table 2 Area and Delay comparison

Reverse converter Area (119860FA) Delay (119905FA)[12] 8119899 + 2 12119899 + 5

[13] (51198992+ 43119899)6 + 16119899 minus 1 18119899 + 7

[14] 10119899 + 5 13119899 + 1

[15] 125119899 + 6 12119899 + 6

[16] 10119899 + 5 12119899 + 1

[17]-1 9119899 + 5 115119899 + 6

[17]-2 1198992+ 12119899 + 12 16119899 + 22

[17]-3 9119899 + 10 11119899 + 14

[18] 11989922 + 11119899 + 14 11119899 + 8

[19]-CICE 251198992+ 255119899 + 12 18119899 + 23

[19]-CIHS 251198992+ 375119899 + 28 12119899 + 15

[19]-C2CE 20119899 + 17 13119899 + 22

[19]-C3CE 23119899 + 11 16119899 + 14

Proposed 7119899 + 3 9119899 + 8

the effectiveness of the employed ldquoerror correctionrdquo approachIn general an error control technique is divided into twoparts ldquoerror detectionrdquo and ldquoerror detection and correctionrdquoFor simplicityrsquos sake here we refer to ldquoerror correctionrdquo tomean both error detection and correction noting that errorbits must first be detected and located before they can becorrected Referring to the residue number system one of itsfeatures is that it can correct ldquoburst errorsrdquo

This means that if error bits are residing in one modulothe error control algorithm can easily detect and correctthem However when error bits are located in more thanone modulo they cannot be corrected although it may bepossible to detect them So the aim now is to discover whatthe average percentage of error detection is when error bitsreside in more than one modulo by employing the proposedRNS based solution

In the proposedmoduli set 22119899+1 22119899+1minus1 2119899minus1 23119899+1minus1 24119899+1

minus 1 22119899+1 22119899+1 minus 1 2119899minus 1 are the main three and

23119899+1

minus 1 24119899+1

minus 1 are the redundant moduli respectivelyNow the first second and third main moduli are (2119899 +

1) (2119899+1) and (119899) bits respectively Given this architecturethe error bits can only be detected and corrected if (a) they are

International Journal of Distributed Sensor Networks 7

Table 3 Area and delay comparison

119873 Main modulus Redundant Modulus Maximum error correction Error detection capabilityError bits in one modulo Error bits in two modulus

2 32 31 3 127 511 5 bits 100 99373 128 127 7 1023 8191 7 bits 100 1004 512 511 15 8191 131071 9 bits 100 100

placed either in the first the second or the third modulo (b)maximum error bit count does not exceed (2119899 + 1) (2119899 + 1)and (119899) respectively Hence the maximum achievable errorcorrection capability is equal to (2119899 + 1) error bits occurringin the first or the second modulo On the other hand theminimum correction capability that can be achieved usingthe proposed modulus set is equal to one error bit within anymodulo of the received packet

In the proposed error control method first sensed dataare divided by the proposed moduli set and then the residuesare computed Next the nodes transmit the residues insteadof sensed data After receiving residues sink computes theoriginal data using 3mainmoduli and their received residuesWhen the residue of the computed number has been dividedby redundant moduli and the received residues for thoseredundantmoduli are not equal an error is detected and errorcorrection procedure is called for it Sink can reconstructthe original data using 3 residues out of the 5 residues andMRC reverse converterThere are only 10 possible conditionsfor selecting 3 residues out of 5 residues (1198625

3= ( 53) =

(5(2 lowast 3)) = 10) Sink computes the original data forall of these possible conditions Given the fact that duringdata transfer some residuesmay have contained errors not allsink computed numbers are accurate and equalThus amongthese 10 numbers those out of dynamic range are removedAfter a voting process those numbers that have received thegreatest votes are selected as correct numbers

In order to gauge the error detection capability of theproposed set in a situation where errors occur in morethan one modulo and where therefore no correction ispossible we simulated the behavior of the error controlalgorithm using C++ programming language The experi-ment runs 3010158400001015840000 different error bit states by setting119899 = 2 3 4 Substituting these values for 119899 in the setwe obtain 32 31 3 127 511 128 127 7 1023 8191 and512 511 15 8191 131071 respectively The test results aredisplayed in Table 3 Note that themaximum error correctionis equal to (2119899 + 1) bits as was mentioned before and thethree error states considered are bits which are located in oneof the main modulus (correction is possible and detection is100) bits which are located in two moduli and finally thecase where bits are resided in three moduli

With reference to Table 3 there are several individualconditions for error detection among the 5 received residuesonly 1 residue contains error 2 residues contain error 3residues contain error Since 2 redundant moduli have beenconsidered for this moduli set error correction of a receivedresidue is possible It makes no difference whether just oneor all bits of the modulo are damaged this can be correctedBased on the damaged bits of the residues we will have

different conditions (eg it is possible that the first andsecond bits the first and third bits or any other combinationof bits are damaged) simulation in C++ language considersall these conditions All possible conditions are simulatedfor 119899 = 2 (ie moduli set 32 31 3 127 511) for 119899 = 3

(ie moduli set 128 127 7 1023 8191) and for 119899 = 4 (iemoduli set 512 511 15 8191 131071 and each time a partof data was damaged intentionally to investigate detectionand correction capability of the method Table 3 displayserror detection percentage for different values of 119899 It alsogives the most number of bits of a modulus that are correctedfor various 119899 values

We evaluated the proposed scheme throughNS-2 simula-tion tool [35] We considered a randomly deployed networkthat is one hundred nodes that were initially spread over anarea of 100 square meters in a random manner The radiocoverage of each sensor node and sink was assumed to bea circular area of 100m in diameter The antenna modeldeployed was omnidirectional Also the initial energy ofsensor nodes set to 01 Joule

The proposed scheme was analyzed in terms of energyconsumption end-to-end delay and network lifetime usingSTCP [21] DTSN [22] TCP and Reed Solomon Table 4shows the simulation parameters

All simulations were repeated 10 times before calculatingthe average of the results As illustrated in Figure 2 the sim-ulation results confirm that the proposed scheme consumessignificantly less energy than the other schemes investigatedIn Figure 3 end-to-end delay is examined where it can beseen that the proposed scheme generates less network delayFinally in Figure 4 it is easy to see that the proposed schemeoutperforms its counterparts in terms of network lifetime

6 Conclusion

In this paper authors unveiled an innovative energy-efficientalgorithm for real time wireless sensor networks that wasbased on a new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1 By

exploiting the MRC technique an efficient reverse converterwas also designed which overcame two-key constraintsnamely component space and high speed operation In orderto take full advantage of the error controllability property ofthe proposed solution two-redundant-moduli sets were thenadded to the initial three main sets resulting in a combinedset 22119899+1 22119899+1 minus 1 2

119899minus 1 23119899+1

minus 1 24119899+1

minus 1

The new methodrsquos error correction capability was foundto be (2119899 + 1) bits under the ideal condition and errordetection improvement reached a figure of 9901 under theworst case scenario condition and 100 when (119899 ge 3)

8 International Journal of Distributed Sensor Networks

0

05

1

15

2

25

3

TCP STCP DTSN RS(15 9 7) Proposedmethod

Tota

l ene

rgy

cons

umpt

ion

(J)

Figure 2 Total energy consumption

250260270280290300310320330340

TCP STCP DTSN RS(15 9 7) Proposedmethod

End-

to-e

nd d

elay

(s)

Figure 3 End-to-end delay

Table 4 Simulation parameters

Area of sensor field 100 lowast 100m2

Antenna model OmnidirectionalSimulation time 1000 SRadio range of a sensor node 100mNumber of sensor nodes 100Initial energy 01 JInterface queue type DroptailInterface queue (IFQ) length 50 PacketsEnergy model Battery

By simulating the proposed error control scheme usingan ns-2 network simulation tool and making comparisonsagainst some popular methods outperformance in terms ofreductions of energy consumption and end-to-end delay aswell as extension of network lifetime was clearly evidentThese advantages therefore make the proposed methodmoredesirable for real-time wireless sensor network applicationswhere reliability low energy consumption and high speedoperations are absolute necessities

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

86889092949698

100102104106

TCP STCP DTSN RS(15 9 7) Proposedmethod

Aver

age l

ifetim

e (s)

Figure 4 Average network lifetime

References

[1] G Song Y Zhou F Ding and A Song ldquoA mobile sensornetwork system for monitoring of unfriendly environmentsrdquoSensors vol 8 no 11 pp 7259ndash7274 2008

[2] J Lloret M Garcia D Bri and S Sendra ldquoA wireless sensornetwork deployment for rural and forest fire detection andverificationrdquo Sensors vol 9 no 11 pp 8722ndash8747 2009

[3] M Dunbabin and L Marques ldquoRobots for environmentalmonitoring significant advancements and applicationsrdquo IEEERobotics and Automation Magazine vol 19 no 1 pp 24ndash392012

[4] P Kumar S-G Lee and H-J Lee ldquoE-SAP efficient-strongauthentication protocol for healthcare applications using wire-less medical sensor networksrdquo Sensors vol 12 no 2 pp 1625ndash1647 2012

[5] Y-M Hong H-C Lin and Y-C Kan ldquoUsing wireless sensornetwork on real-time remote monitoring of the load cell forlandsliderdquo Sensor Letters vol 9 no 5 pp 1911ndash1915 2011

[6] S Khodadoustan F Jalali and A Ejlali ldquoReliabilityenergytrade-off in Bluetooth error control schemesrdquo MicroelectronicsReliability vol 51 no 8 pp 1398ndash1412 2011

[7] J Yick B Mukherjee and D Ghosal ldquoWireless sensor networksurveyrdquoComputerNetworks vol 52 no 12 pp 2292ndash2330 2008

[8] Z Guo B Wang P Xie W Zeng and J-H Cui ldquoEfficient errorrecovery with network coding in underwater sensor networksrdquoAd Hoc Networks vol 7 no 4 pp 791ndash802 2009

[9] I F Akyildiz and M C Vuran Wireless Sensor Networks JohnWiley amp Sons Chichester UK 2010

[10] E Cayırcı and C Rong Security in Wireless Ad Hoc and SensorNetworks John Wiley amp Sons Chichester UK 2009

[11] J H Kleinschmidt W C Borelli and M E Pellenz ldquoAnenergy efficiency model for adaptive and custom error controlschemes in Bluetooth sensor networksrdquo International Journal ofElectronics and Communications (AEU) vol 63 no 3 pp 188ndash199 2009

[12] A S Molahosseini K Navi C Dadkhah O Kavehei and STimarchi ldquoEfficient reverse converter designs for the new 4-moduli sets 2

119899minus 1 2

119899 2119899+ 1 2

2119899+1minus 1 and 2

119899minus 1 2

119899+

1 22119899 22119899+1 based onnewCRTsrdquo IEEETransactions onCircuits

and Systems I vol 57 no 4 pp 823ndash835 2010[13] B Cao C-H Chang and T Srikanthan ldquoA residue-to-binary

converter for a new five-moduli setrdquo IEEE Transactions onCircuits and Systems I vol 54 no 5 pp 1041ndash1049 2007

[14] A S Molahosseini C Dadkhah and K Navi ldquoA new five-moduli set for efficient hardware implementation of the reverse

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

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Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

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Navigation and Observation

International Journal of

4 International Journal of Distributed Sensor Networks

Sink Cluster headSensor node

5 = ⟨2 | 1 | 0⟩

6 = ⟨0 | 2 | 1⟩ 7 = ⟨1 | 3 | 2⟩

16 = ⟨1 | 0 | 1⟩

12 = ⟨0 | 0 | 2⟩ 10 = ⟨1 | 2 | 0⟩

= ⟨5 | 8 | 6⟩RemaindersModuli set = 3 4 5

Resultoriginal message

| |||2 1 0

0 2 1

1 3 2

3 6 3

2 2 3

| ⟩⟩3 6 3|| ⟩⟩ | |

2 1 0

0 0 2

1 0 1| ⟩⟩2 2 3|| ⟩⟩

|⟨ ⟨5 8 6|| ⟩⟩

+

+

Figure 1 An example of data aggregation functionality using the proposed scheme

required It is therefore seen that this solution results in asignificant drop in end-to-end delay which makes it suitablefor real-time wireless sensor network applications

The proposed method for error control could be appliedto tree-like network topologies and cluster based networktopologies In tree-like network children transmit the residueof their sensed data that has been divided by the moduli setto their parent and their parent will aggregate the receivedresidues and his own residues Next the parent transmits theresult to his own parent This will continue until the residuesreach sink In a cluster-based network the members of thecluster transmit the residue of their sensed data divided bymoduli set to head cluster Then the head cluster aggregatesthe received residues and its own residues and transmits theresult to the next head clusters

In this study we considered 5 moduli 3 main and2 redundant Since wireless sensor networks are limitedin terms of energy processing power size memory selection of the number and value of moduli was madein a way that their reverse converters led to the lowestenergy consumption and delay How we select the mainmoduli determines the value of dynamic range (obtained byproduct of main moduli) In fact if we increase the dynamicrange it will allow us to represent larger numbers usingthe proposed method On the other hand increasing thenumber of redundant moduli results in higher capability oferror detection and correction Thus if 119905 redundant modulois considered 119905 modulo containing error can be detectedand lfloor1199052rfloor residue can be corrected However the increasein the number of the moduli leads to an increase in reverseconverter cost

An example illustrating the basic theme of the proposedscheme is shown below consisting of six sensors located intwo clusters Each cluster has three sensors and a cluster head

In this example aggregation is a summation operation wherethe remainders of 5 based on the moduli 3 4 5 are 2 1 0and the remainders of other sensed data are calculated inthe same way In the aggregators where summation takesplace all of the results received from the first modulo areadded together also as all of the results from the secondmodulo and so on for the thirdmoduloThis feature offers theadded advantage of requiring lower space for the arithmeticblock As can be seen in the sink node the final decryptedremainders are 5 8 6 and the modulus set is 3 4 5

Now in order to achieve a lower power consumptionand as compact a design as possible a new moduli set22119899+1

22119899+1

minus1 2119899minus1 replaces 3 4 5 in Figure 1 Moreover

the sink node using a reverse converter can decode themessage and recover the original data

Hence an efficient reverse converter is needed Thereare two basic approaches that convert a number from RNSto its binary equivalent These are the Chinese ReminderTheorem (CRT) and Mixed Radix Conversion (MRC) [6]with MRC algorithm being the preferred choice in thispaper Considering also that reliability in data delivery isan important issue in almost all wireless sensor networkapplications two-redundant-moduli set 23119899+1 minus 1 2

4119899+1minus 1

is added to the new 3-moduli set 22119899+1 22119899+1 minus 1 2119899minus 1

to further enhance error control capability of the proposedscheme It should be pointed out that the proposedmoduli setacts as secret key which is used by the sink node to decryptthe received remainders and obtain the original message Ifan adversary that has no knowledge of the moduli set couldacquire the transmitted packet it would not be able to decryptthe message It is clear that redundant residue number allowstransmit data to be encrypted by employing symmetric keyand thus provides a powerful tool for error bit detection aswell as an effective means for data correction

International Journal of Distributed Sensor Networks 5

4 Design and Implementation of ProposedResidue to Binary Converter

Various methods can be used to design a reverse converterThe most popular methods are MCR and CRT The use ofCRTorMRCdepends on selectedmoduli sincemultiplicativeinverse should be computed in both methods Computationof multiplicative inverse is the most difficult part of reverseconverterTherefore it is important to look for multiplicativeinverses that allow the formulation of the most simpleequations Certain moduli set can be designed well and atless cost by employingMCR since their multiplicative inverseis computed more easily through simplified (less complex)equations As a result the volume of required hardwareand consumption of energy as well as network delay are allreduced In this study we applied MRC Using this methodthe values of multiplicative inverse become so simpler andthe design of the reverse converter costs so much less

The residue to binary conversion can be performed usingthe MRC algorithm as follows

119883 = 119881119899

119899

prod119894=1

119875119894+ sdot sdot sdot + 119881

311987521198751+ 11988121198751+ 1198811 (2)

The coefficients V119894119875 can be obtained from residues by

1198811= 1199091

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752

(3)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753 (4)

In the general case we have

119881119899= (((119909

119899minus 1198811)10038161003816100381610038161003816119875minus1

1

10038161003816100381610038161003816119875119899minus 1198812)10038161003816100381610038161003816119875minus1

2

10038161003816100381610038161003816119875119899

minus sdot sdot sdot minus 119881119899minus1

)10038161003816100381610038161003816119875minus1

119899minus1|119875119899

10038161003816100381610038161003816119875119899

(5)

where |119875minus1119894|119875119895denotes the multiplicative inverse of 119875

119894modulo

119875119895 In mathematics a multiplicative inverse for a number119883 is

a number that when multiplied by119883 yields the multiplicativeidentity 1 The modular multiplicative inverse of a modulo119898can be derived from the extended Euclidean algorithm

According to (2)ndash(5) the proposed reverse converter canbe designed for the new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1

as followsConsider the 3-moduli set 119875

1 1198752 1198753 = 2

2119899+1 22119899+1

minus

1 2119899minus 1 with three corresponding residues (119909

1 1199092 1199093) In

order to design a residue to binary converter we first need toobtain the multiplicative inverse values and substitute thesevalues with the modulus set in the conversion algorithmformulas The resultant equations should then be simplifiedby using the arithmetic propertiesThe final conversion stageinvolves the implementation of these simplified equationsusing hardware components such as full adders and logicgatesThe following propositions are used to obtain the closedform expressions which will be the means to compute themultiplicative inverses based on the MRC algorithm

Proposition 1 The multiplicative inverse of (22119899+1) modulo(22119899+1

minus 1) is 1198961= 1

Proof One has1003816100381610038161003816100381622119899+11003816100381610038161003816100381622119899+1minus1

= 1 (6)

Proposition 2 The multiplicative inverse of (22119899+1) modulo(2119899minus 1) is 119896

2= 2119899minus1

Proof One has100381610038161003816100381610038162119899minus1

times 22119899+1100381610038161003816100381610038162119899minus1

=1003816100381610038161003816100381623119899100381610038161003816100381610038162119899minus1

= 1 (7)

Proposition 3 The multiplicative inverse of (22119899+1

minus 1)

modulo (2119899 minus 1) is 1198963= 1

Proof One has1003816100381610038161003816100381622119899+1

minus 1100381610038161003816100381610038162119899minus1

= 1 (8)

Therefore let the values lt 1198961= 1 119896

2= 2119899minus1

1198963

=

1 1198751= (22119899+1

) 1198752= (22119899+1

minus 1) and 1198753= (2119899minus 1) gt in

(2)ndash(4) and thus we have119883 = 119909

1+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)

(9)

1198811= 1199091 (10)

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1 (11)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753

=100381610038161003816100381610038162119899minus1

times ((1199093minus 1199091) + (minus119881

2))100381610038161003816100381610038162119899minus1

(12)

In order to design an efficient reverse converter expres-sions (9) and (11)-(12) can be rewritten as follows

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 +1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 11988121+ 11988122

(13)

where11988121

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 = 11990922119899

11990922119899minus1

sdot sdot sdot 11990920⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

11988122

=1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 12119899

12119899minus1

sdot sdot sdot 10⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

(14)

Now in order to implement 1198813on the basis of (12) we

have

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

100381610038161003816100381610038161003816P3

=100381610038161003816100381610038162119899minus1

times (1199093minus 1199091) minus 119881

2

100381610038161003816100381610038162119899minus1

= V31+ 11988132+ 11988133

(15)

6 International Journal of Distributed Sensor Networks

where

11988131

=100381610038161003816100381610038162119899minus1

times 1199093

100381610038161003816100381610038162119899minus1= 11990930⏟⏟⏟⏟⏟⏟⏟1bit

1199093119899minus1

sdot sdot sdot 11990931⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(119899minus1)bits

11988132

=10038161003816100381610038161003816minus2119899minus1

times 1199091

100381610038161003816100381610038162119899minus1=

10

1119899minus1

sdot sdot sdot 11

1119899

12119899minus1

sdot sdot sdot 1119899+1

+

12119899⏟⏟⏟⏟⏟⏟⏟1bit

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

11988133

=1003816100381610038161003816minus1198812

10038161003816100381610038162119899minus1 =

2119899minus1

sdot sdot sdot 2120

22119899minus1

sdot sdot sdot 2119899+1

2119899+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

22119899⏟⏟⏟⏟⏟⏟⏟1bit

(16)

Finally to obtain119883 based on (9) we have

119883 = 1199091+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119862

= 1199091+ (22119899+1

) 119862

119862 = 1198812+ (22119899+1

minus 1)1198813

119862 =

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞1198813119899minus1

sdot sdot sdot 11988130

(119899+1)bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞11988122119899

11988122119899minus1

sdot sdot sdot 1198812119899

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞3119899minus1

sdot sdot sdot 30

+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(2119899+1)bits

1198812119899minus1

sdot sdot sdot 11988120⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119899bits

119883 = 1199091+ (22119899+1

) 119862 = Concatenation (1199091 119862)

(17)

The area and delay specifications for the proposed reverseconverter are shown in Table 1

From this Table we have

Total area = (7119899 + 3)119860FA + (5119899 + 2)119860NOT

+ (4119899 minus 1)119860OR + (4119899 minus 1)119860XNOR

Total delay = (9119899 + 8) 119905FA + 3119905NOT

(18)

Now let us discuss comparison of the proposed reverseconverterrsquos performance for the newmoduli set 22119899+1 22119899+1minus1 2119899minus1 against competing models that have either the same

or a lower dynamic range in terms of hardware requirementand speed of operations It should be noted that in any reverseconverter most of the delay is associated with full adderswhich also occupy the largest area allocated to componentsassembly Thus for the sake of comparison it is sufficient toinvestigate only 119860FA and 119905FA see Table 2

5 Performance Evaluation

In this section the performance of the proposed moduli set22119899+1

22119899+1

minus1 2119899minus1 23119899+1

minus1 24119899+1

minus1 is evaluated in termsof error detection and error correction capabilities Evalua-tion of the error control capability requires an investigation of

Table 1 Characterization of each part of the proposed reverseconverter

Parts FA NOT ANDXOR ORXNOR DelayOPU 1 mdash (2119899 + 1) mdash mdash 119905NOT

CPA 1 (2119899 + 1) mdash mdash mdash (4119899 + 2)119905FA

CSA 1 119873 mdash mdash mdash 119905FA

CSA 2 1 mdash mdash (119899 minus 1) 119905FA

OPU 2 mdash (2119899 + 1) mdash mdash 119905NOT

CSA 3 119873 mdash mdash mdash 119905FA

CSA 4 119873 mdash mdash mdash 119905FA

CSA 5 1 mdash mdash (119899 minus 1) 119905FA

CPA 2 119873 mdash mdash mdash (2119899)119905FA

OPU 3 mdash 119873 mdash mdash 119905NOT

119877minus CPA 119873 mdash mdash (2119899 + 1) (3119899 + 1)119905FA

Table 2 Area and Delay comparison

Reverse converter Area (119860FA) Delay (119905FA)[12] 8119899 + 2 12119899 + 5

[13] (51198992+ 43119899)6 + 16119899 minus 1 18119899 + 7

[14] 10119899 + 5 13119899 + 1

[15] 125119899 + 6 12119899 + 6

[16] 10119899 + 5 12119899 + 1

[17]-1 9119899 + 5 115119899 + 6

[17]-2 1198992+ 12119899 + 12 16119899 + 22

[17]-3 9119899 + 10 11119899 + 14

[18] 11989922 + 11119899 + 14 11119899 + 8

[19]-CICE 251198992+ 255119899 + 12 18119899 + 23

[19]-CIHS 251198992+ 375119899 + 28 12119899 + 15

[19]-C2CE 20119899 + 17 13119899 + 22

[19]-C3CE 23119899 + 11 16119899 + 14

Proposed 7119899 + 3 9119899 + 8

the effectiveness of the employed ldquoerror correctionrdquo approachIn general an error control technique is divided into twoparts ldquoerror detectionrdquo and ldquoerror detection and correctionrdquoFor simplicityrsquos sake here we refer to ldquoerror correctionrdquo tomean both error detection and correction noting that errorbits must first be detected and located before they can becorrected Referring to the residue number system one of itsfeatures is that it can correct ldquoburst errorsrdquo

This means that if error bits are residing in one modulothe error control algorithm can easily detect and correctthem However when error bits are located in more thanone modulo they cannot be corrected although it may bepossible to detect them So the aim now is to discover whatthe average percentage of error detection is when error bitsreside in more than one modulo by employing the proposedRNS based solution

In the proposedmoduli set 22119899+1 22119899+1minus1 2119899minus1 23119899+1minus1 24119899+1

minus 1 22119899+1 22119899+1 minus 1 2119899minus 1 are the main three and

23119899+1

minus 1 24119899+1

minus 1 are the redundant moduli respectivelyNow the first second and third main moduli are (2119899 +

1) (2119899+1) and (119899) bits respectively Given this architecturethe error bits can only be detected and corrected if (a) they are

International Journal of Distributed Sensor Networks 7

Table 3 Area and delay comparison

119873 Main modulus Redundant Modulus Maximum error correction Error detection capabilityError bits in one modulo Error bits in two modulus

2 32 31 3 127 511 5 bits 100 99373 128 127 7 1023 8191 7 bits 100 1004 512 511 15 8191 131071 9 bits 100 100

placed either in the first the second or the third modulo (b)maximum error bit count does not exceed (2119899 + 1) (2119899 + 1)and (119899) respectively Hence the maximum achievable errorcorrection capability is equal to (2119899 + 1) error bits occurringin the first or the second modulo On the other hand theminimum correction capability that can be achieved usingthe proposed modulus set is equal to one error bit within anymodulo of the received packet

In the proposed error control method first sensed dataare divided by the proposed moduli set and then the residuesare computed Next the nodes transmit the residues insteadof sensed data After receiving residues sink computes theoriginal data using 3mainmoduli and their received residuesWhen the residue of the computed number has been dividedby redundant moduli and the received residues for thoseredundantmoduli are not equal an error is detected and errorcorrection procedure is called for it Sink can reconstructthe original data using 3 residues out of the 5 residues andMRC reverse converterThere are only 10 possible conditionsfor selecting 3 residues out of 5 residues (1198625

3= ( 53) =

(5(2 lowast 3)) = 10) Sink computes the original data forall of these possible conditions Given the fact that duringdata transfer some residuesmay have contained errors not allsink computed numbers are accurate and equalThus amongthese 10 numbers those out of dynamic range are removedAfter a voting process those numbers that have received thegreatest votes are selected as correct numbers

In order to gauge the error detection capability of theproposed set in a situation where errors occur in morethan one modulo and where therefore no correction ispossible we simulated the behavior of the error controlalgorithm using C++ programming language The experi-ment runs 3010158400001015840000 different error bit states by setting119899 = 2 3 4 Substituting these values for 119899 in the setwe obtain 32 31 3 127 511 128 127 7 1023 8191 and512 511 15 8191 131071 respectively The test results aredisplayed in Table 3 Note that themaximum error correctionis equal to (2119899 + 1) bits as was mentioned before and thethree error states considered are bits which are located in oneof the main modulus (correction is possible and detection is100) bits which are located in two moduli and finally thecase where bits are resided in three moduli

With reference to Table 3 there are several individualconditions for error detection among the 5 received residuesonly 1 residue contains error 2 residues contain error 3residues contain error Since 2 redundant moduli have beenconsidered for this moduli set error correction of a receivedresidue is possible It makes no difference whether just oneor all bits of the modulo are damaged this can be correctedBased on the damaged bits of the residues we will have

different conditions (eg it is possible that the first andsecond bits the first and third bits or any other combinationof bits are damaged) simulation in C++ language considersall these conditions All possible conditions are simulatedfor 119899 = 2 (ie moduli set 32 31 3 127 511) for 119899 = 3

(ie moduli set 128 127 7 1023 8191) and for 119899 = 4 (iemoduli set 512 511 15 8191 131071 and each time a partof data was damaged intentionally to investigate detectionand correction capability of the method Table 3 displayserror detection percentage for different values of 119899 It alsogives the most number of bits of a modulus that are correctedfor various 119899 values

We evaluated the proposed scheme throughNS-2 simula-tion tool [35] We considered a randomly deployed networkthat is one hundred nodes that were initially spread over anarea of 100 square meters in a random manner The radiocoverage of each sensor node and sink was assumed to bea circular area of 100m in diameter The antenna modeldeployed was omnidirectional Also the initial energy ofsensor nodes set to 01 Joule

The proposed scheme was analyzed in terms of energyconsumption end-to-end delay and network lifetime usingSTCP [21] DTSN [22] TCP and Reed Solomon Table 4shows the simulation parameters

All simulations were repeated 10 times before calculatingthe average of the results As illustrated in Figure 2 the sim-ulation results confirm that the proposed scheme consumessignificantly less energy than the other schemes investigatedIn Figure 3 end-to-end delay is examined where it can beseen that the proposed scheme generates less network delayFinally in Figure 4 it is easy to see that the proposed schemeoutperforms its counterparts in terms of network lifetime

6 Conclusion

In this paper authors unveiled an innovative energy-efficientalgorithm for real time wireless sensor networks that wasbased on a new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1 By

exploiting the MRC technique an efficient reverse converterwas also designed which overcame two-key constraintsnamely component space and high speed operation In orderto take full advantage of the error controllability property ofthe proposed solution two-redundant-moduli sets were thenadded to the initial three main sets resulting in a combinedset 22119899+1 22119899+1 minus 1 2

119899minus 1 23119899+1

minus 1 24119899+1

minus 1

The new methodrsquos error correction capability was foundto be (2119899 + 1) bits under the ideal condition and errordetection improvement reached a figure of 9901 under theworst case scenario condition and 100 when (119899 ge 3)

8 International Journal of Distributed Sensor Networks

0

05

1

15

2

25

3

TCP STCP DTSN RS(15 9 7) Proposedmethod

Tota

l ene

rgy

cons

umpt

ion

(J)

Figure 2 Total energy consumption

250260270280290300310320330340

TCP STCP DTSN RS(15 9 7) Proposedmethod

End-

to-e

nd d

elay

(s)

Figure 3 End-to-end delay

Table 4 Simulation parameters

Area of sensor field 100 lowast 100m2

Antenna model OmnidirectionalSimulation time 1000 SRadio range of a sensor node 100mNumber of sensor nodes 100Initial energy 01 JInterface queue type DroptailInterface queue (IFQ) length 50 PacketsEnergy model Battery

By simulating the proposed error control scheme usingan ns-2 network simulation tool and making comparisonsagainst some popular methods outperformance in terms ofreductions of energy consumption and end-to-end delay aswell as extension of network lifetime was clearly evidentThese advantages therefore make the proposed methodmoredesirable for real-time wireless sensor network applicationswhere reliability low energy consumption and high speedoperations are absolute necessities

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

86889092949698

100102104106

TCP STCP DTSN RS(15 9 7) Proposedmethod

Aver

age l

ifetim

e (s)

Figure 4 Average network lifetime

References

[1] G Song Y Zhou F Ding and A Song ldquoA mobile sensornetwork system for monitoring of unfriendly environmentsrdquoSensors vol 8 no 11 pp 7259ndash7274 2008

[2] J Lloret M Garcia D Bri and S Sendra ldquoA wireless sensornetwork deployment for rural and forest fire detection andverificationrdquo Sensors vol 9 no 11 pp 8722ndash8747 2009

[3] M Dunbabin and L Marques ldquoRobots for environmentalmonitoring significant advancements and applicationsrdquo IEEERobotics and Automation Magazine vol 19 no 1 pp 24ndash392012

[4] P Kumar S-G Lee and H-J Lee ldquoE-SAP efficient-strongauthentication protocol for healthcare applications using wire-less medical sensor networksrdquo Sensors vol 12 no 2 pp 1625ndash1647 2012

[5] Y-M Hong H-C Lin and Y-C Kan ldquoUsing wireless sensornetwork on real-time remote monitoring of the load cell forlandsliderdquo Sensor Letters vol 9 no 5 pp 1911ndash1915 2011

[6] S Khodadoustan F Jalali and A Ejlali ldquoReliabilityenergytrade-off in Bluetooth error control schemesrdquo MicroelectronicsReliability vol 51 no 8 pp 1398ndash1412 2011

[7] J Yick B Mukherjee and D Ghosal ldquoWireless sensor networksurveyrdquoComputerNetworks vol 52 no 12 pp 2292ndash2330 2008

[8] Z Guo B Wang P Xie W Zeng and J-H Cui ldquoEfficient errorrecovery with network coding in underwater sensor networksrdquoAd Hoc Networks vol 7 no 4 pp 791ndash802 2009

[9] I F Akyildiz and M C Vuran Wireless Sensor Networks JohnWiley amp Sons Chichester UK 2010

[10] E Cayırcı and C Rong Security in Wireless Ad Hoc and SensorNetworks John Wiley amp Sons Chichester UK 2009

[11] J H Kleinschmidt W C Borelli and M E Pellenz ldquoAnenergy efficiency model for adaptive and custom error controlschemes in Bluetooth sensor networksrdquo International Journal ofElectronics and Communications (AEU) vol 63 no 3 pp 188ndash199 2009

[12] A S Molahosseini K Navi C Dadkhah O Kavehei and STimarchi ldquoEfficient reverse converter designs for the new 4-moduli sets 2

119899minus 1 2

119899 2119899+ 1 2

2119899+1minus 1 and 2

119899minus 1 2

119899+

1 22119899 22119899+1 based onnewCRTsrdquo IEEETransactions onCircuits

and Systems I vol 57 no 4 pp 823ndash835 2010[13] B Cao C-H Chang and T Srikanthan ldquoA residue-to-binary

converter for a new five-moduli setrdquo IEEE Transactions onCircuits and Systems I vol 54 no 5 pp 1041ndash1049 2007

[14] A S Molahosseini C Dadkhah and K Navi ldquoA new five-moduli set for efficient hardware implementation of the reverse

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

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Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

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Journal ofEngineeringVolume 2014

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Shock and Vibration

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Mechanical Engineering

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Electrical and Computer Engineering

Journal of

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Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

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Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

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Advances inOptoElectronics

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Chemical EngineeringInternational Journal of

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Control Scienceand Engineering

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Antennas andPropagation

International Journal of

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Navigation and Observation

International Journal of

International Journal of Distributed Sensor Networks 5

4 Design and Implementation of ProposedResidue to Binary Converter

Various methods can be used to design a reverse converterThe most popular methods are MCR and CRT The use ofCRTorMRCdepends on selectedmoduli sincemultiplicativeinverse should be computed in both methods Computationof multiplicative inverse is the most difficult part of reverseconverterTherefore it is important to look for multiplicativeinverses that allow the formulation of the most simpleequations Certain moduli set can be designed well and atless cost by employingMCR since their multiplicative inverseis computed more easily through simplified (less complex)equations As a result the volume of required hardwareand consumption of energy as well as network delay are allreduced In this study we applied MRC Using this methodthe values of multiplicative inverse become so simpler andthe design of the reverse converter costs so much less

The residue to binary conversion can be performed usingthe MRC algorithm as follows

119883 = 119881119899

119899

prod119894=1

119875119894+ sdot sdot sdot + 119881

311987521198751+ 11988121198751+ 1198811 (2)

The coefficients V119894119875 can be obtained from residues by

1198811= 1199091

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752

(3)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753 (4)

In the general case we have

119881119899= (((119909

119899minus 1198811)10038161003816100381610038161003816119875minus1

1

10038161003816100381610038161003816119875119899minus 1198812)10038161003816100381610038161003816119875minus1

2

10038161003816100381610038161003816119875119899

minus sdot sdot sdot minus 119881119899minus1

)10038161003816100381610038161003816119875minus1

119899minus1|119875119899

10038161003816100381610038161003816119875119899

(5)

where |119875minus1119894|119875119895denotes the multiplicative inverse of 119875

119894modulo

119875119895 In mathematics a multiplicative inverse for a number119883 is

a number that when multiplied by119883 yields the multiplicativeidentity 1 The modular multiplicative inverse of a modulo119898can be derived from the extended Euclidean algorithm

According to (2)ndash(5) the proposed reverse converter canbe designed for the new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1

as followsConsider the 3-moduli set 119875

1 1198752 1198753 = 2

2119899+1 22119899+1

minus

1 2119899minus 1 with three corresponding residues (119909

1 1199092 1199093) In

order to design a residue to binary converter we first need toobtain the multiplicative inverse values and substitute thesevalues with the modulus set in the conversion algorithmformulas The resultant equations should then be simplifiedby using the arithmetic propertiesThe final conversion stageinvolves the implementation of these simplified equationsusing hardware components such as full adders and logicgatesThe following propositions are used to obtain the closedform expressions which will be the means to compute themultiplicative inverses based on the MRC algorithm

Proposition 1 The multiplicative inverse of (22119899+1) modulo(22119899+1

minus 1) is 1198961= 1

Proof One has1003816100381610038161003816100381622119899+11003816100381610038161003816100381622119899+1minus1

= 1 (6)

Proposition 2 The multiplicative inverse of (22119899+1) modulo(2119899minus 1) is 119896

2= 2119899minus1

Proof One has100381610038161003816100381610038162119899minus1

times 22119899+1100381610038161003816100381610038162119899minus1

=1003816100381610038161003816100381623119899100381610038161003816100381610038162119899minus1

= 1 (7)

Proposition 3 The multiplicative inverse of (22119899+1

minus 1)

modulo (2119899 minus 1) is 1198963= 1

Proof One has1003816100381610038161003816100381622119899+1

minus 1100381610038161003816100381610038162119899minus1

= 1 (8)

Therefore let the values lt 1198961= 1 119896

2= 2119899minus1

1198963

=

1 1198751= (22119899+1

) 1198752= (22119899+1

minus 1) and 1198753= (2119899minus 1) gt in

(2)ndash(4) and thus we have119883 = 119909

1+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)

(9)

1198811= 1199091 (10)

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1 (11)

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

1003816100381610038161003816100381610038161198753

=100381610038161003816100381610038162119899minus1

times ((1199093minus 1199091) + (minus119881

2))100381610038161003816100381610038162119899minus1

(12)

In order to design an efficient reverse converter expres-sions (9) and (11)-(12) can be rewritten as follows

1198812=100381610038161003816100381610038161003816(1199092minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198752

1003816100381610038161003816100381610038161198752=10038161003816100381610038161199092 minus 119909

1

100381610038161003816100381622119899+1minus1

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 +1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 11988121+ 11988122

(13)

where11988121

=10038161003816100381610038161199092

100381610038161003816100381622119899+1minus1 = 11990922119899

11990922119899minus1

sdot sdot sdot 11990920⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

11988122

=1003816100381610038161003816minus1199091

100381610038161003816100381622119899+1minus1 = 12119899

12119899minus1

sdot sdot sdot 10⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(2119899+1)bits

(14)

Now in order to implement 1198813on the basis of (12) we

have

1198813=100381610038161003816100381610038161003816((1199093minus 1199091)10038161003816100381610038161003816119875minus1

1

100381610038161003816100381610038161198753minus 1198812)10038161003816100381610038161003816119875minus1

2

100381610038161003816100381610038161198753

100381610038161003816100381610038161003816P3

=100381610038161003816100381610038162119899minus1

times (1199093minus 1199091) minus 119881

2

100381610038161003816100381610038162119899minus1

= V31+ 11988132+ 11988133

(15)

6 International Journal of Distributed Sensor Networks

where

11988131

=100381610038161003816100381610038162119899minus1

times 1199093

100381610038161003816100381610038162119899minus1= 11990930⏟⏟⏟⏟⏟⏟⏟1bit

1199093119899minus1

sdot sdot sdot 11990931⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(119899minus1)bits

11988132

=10038161003816100381610038161003816minus2119899minus1

times 1199091

100381610038161003816100381610038162119899minus1=

10

1119899minus1

sdot sdot sdot 11

1119899

12119899minus1

sdot sdot sdot 1119899+1

+

12119899⏟⏟⏟⏟⏟⏟⏟1bit

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

11988133

=1003816100381610038161003816minus1198812

10038161003816100381610038162119899minus1 =

2119899minus1

sdot sdot sdot 2120

22119899minus1

sdot sdot sdot 2119899+1

2119899+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

22119899⏟⏟⏟⏟⏟⏟⏟1bit

(16)

Finally to obtain119883 based on (9) we have

119883 = 1199091+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119862

= 1199091+ (22119899+1

) 119862

119862 = 1198812+ (22119899+1

minus 1)1198813

119862 =

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞1198813119899minus1

sdot sdot sdot 11988130

(119899+1)bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞11988122119899

11988122119899minus1

sdot sdot sdot 1198812119899

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞3119899minus1

sdot sdot sdot 30

+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(2119899+1)bits

1198812119899minus1

sdot sdot sdot 11988120⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119899bits

119883 = 1199091+ (22119899+1

) 119862 = Concatenation (1199091 119862)

(17)

The area and delay specifications for the proposed reverseconverter are shown in Table 1

From this Table we have

Total area = (7119899 + 3)119860FA + (5119899 + 2)119860NOT

+ (4119899 minus 1)119860OR + (4119899 minus 1)119860XNOR

Total delay = (9119899 + 8) 119905FA + 3119905NOT

(18)

Now let us discuss comparison of the proposed reverseconverterrsquos performance for the newmoduli set 22119899+1 22119899+1minus1 2119899minus1 against competing models that have either the same

or a lower dynamic range in terms of hardware requirementand speed of operations It should be noted that in any reverseconverter most of the delay is associated with full adderswhich also occupy the largest area allocated to componentsassembly Thus for the sake of comparison it is sufficient toinvestigate only 119860FA and 119905FA see Table 2

5 Performance Evaluation

In this section the performance of the proposed moduli set22119899+1

22119899+1

minus1 2119899minus1 23119899+1

minus1 24119899+1

minus1 is evaluated in termsof error detection and error correction capabilities Evalua-tion of the error control capability requires an investigation of

Table 1 Characterization of each part of the proposed reverseconverter

Parts FA NOT ANDXOR ORXNOR DelayOPU 1 mdash (2119899 + 1) mdash mdash 119905NOT

CPA 1 (2119899 + 1) mdash mdash mdash (4119899 + 2)119905FA

CSA 1 119873 mdash mdash mdash 119905FA

CSA 2 1 mdash mdash (119899 minus 1) 119905FA

OPU 2 mdash (2119899 + 1) mdash mdash 119905NOT

CSA 3 119873 mdash mdash mdash 119905FA

CSA 4 119873 mdash mdash mdash 119905FA

CSA 5 1 mdash mdash (119899 minus 1) 119905FA

CPA 2 119873 mdash mdash mdash (2119899)119905FA

OPU 3 mdash 119873 mdash mdash 119905NOT

119877minus CPA 119873 mdash mdash (2119899 + 1) (3119899 + 1)119905FA

Table 2 Area and Delay comparison

Reverse converter Area (119860FA) Delay (119905FA)[12] 8119899 + 2 12119899 + 5

[13] (51198992+ 43119899)6 + 16119899 minus 1 18119899 + 7

[14] 10119899 + 5 13119899 + 1

[15] 125119899 + 6 12119899 + 6

[16] 10119899 + 5 12119899 + 1

[17]-1 9119899 + 5 115119899 + 6

[17]-2 1198992+ 12119899 + 12 16119899 + 22

[17]-3 9119899 + 10 11119899 + 14

[18] 11989922 + 11119899 + 14 11119899 + 8

[19]-CICE 251198992+ 255119899 + 12 18119899 + 23

[19]-CIHS 251198992+ 375119899 + 28 12119899 + 15

[19]-C2CE 20119899 + 17 13119899 + 22

[19]-C3CE 23119899 + 11 16119899 + 14

Proposed 7119899 + 3 9119899 + 8

the effectiveness of the employed ldquoerror correctionrdquo approachIn general an error control technique is divided into twoparts ldquoerror detectionrdquo and ldquoerror detection and correctionrdquoFor simplicityrsquos sake here we refer to ldquoerror correctionrdquo tomean both error detection and correction noting that errorbits must first be detected and located before they can becorrected Referring to the residue number system one of itsfeatures is that it can correct ldquoburst errorsrdquo

This means that if error bits are residing in one modulothe error control algorithm can easily detect and correctthem However when error bits are located in more thanone modulo they cannot be corrected although it may bepossible to detect them So the aim now is to discover whatthe average percentage of error detection is when error bitsreside in more than one modulo by employing the proposedRNS based solution

In the proposedmoduli set 22119899+1 22119899+1minus1 2119899minus1 23119899+1minus1 24119899+1

minus 1 22119899+1 22119899+1 minus 1 2119899minus 1 are the main three and

23119899+1

minus 1 24119899+1

minus 1 are the redundant moduli respectivelyNow the first second and third main moduli are (2119899 +

1) (2119899+1) and (119899) bits respectively Given this architecturethe error bits can only be detected and corrected if (a) they are

International Journal of Distributed Sensor Networks 7

Table 3 Area and delay comparison

119873 Main modulus Redundant Modulus Maximum error correction Error detection capabilityError bits in one modulo Error bits in two modulus

2 32 31 3 127 511 5 bits 100 99373 128 127 7 1023 8191 7 bits 100 1004 512 511 15 8191 131071 9 bits 100 100

placed either in the first the second or the third modulo (b)maximum error bit count does not exceed (2119899 + 1) (2119899 + 1)and (119899) respectively Hence the maximum achievable errorcorrection capability is equal to (2119899 + 1) error bits occurringin the first or the second modulo On the other hand theminimum correction capability that can be achieved usingthe proposed modulus set is equal to one error bit within anymodulo of the received packet

In the proposed error control method first sensed dataare divided by the proposed moduli set and then the residuesare computed Next the nodes transmit the residues insteadof sensed data After receiving residues sink computes theoriginal data using 3mainmoduli and their received residuesWhen the residue of the computed number has been dividedby redundant moduli and the received residues for thoseredundantmoduli are not equal an error is detected and errorcorrection procedure is called for it Sink can reconstructthe original data using 3 residues out of the 5 residues andMRC reverse converterThere are only 10 possible conditionsfor selecting 3 residues out of 5 residues (1198625

3= ( 53) =

(5(2 lowast 3)) = 10) Sink computes the original data forall of these possible conditions Given the fact that duringdata transfer some residuesmay have contained errors not allsink computed numbers are accurate and equalThus amongthese 10 numbers those out of dynamic range are removedAfter a voting process those numbers that have received thegreatest votes are selected as correct numbers

In order to gauge the error detection capability of theproposed set in a situation where errors occur in morethan one modulo and where therefore no correction ispossible we simulated the behavior of the error controlalgorithm using C++ programming language The experi-ment runs 3010158400001015840000 different error bit states by setting119899 = 2 3 4 Substituting these values for 119899 in the setwe obtain 32 31 3 127 511 128 127 7 1023 8191 and512 511 15 8191 131071 respectively The test results aredisplayed in Table 3 Note that themaximum error correctionis equal to (2119899 + 1) bits as was mentioned before and thethree error states considered are bits which are located in oneof the main modulus (correction is possible and detection is100) bits which are located in two moduli and finally thecase where bits are resided in three moduli

With reference to Table 3 there are several individualconditions for error detection among the 5 received residuesonly 1 residue contains error 2 residues contain error 3residues contain error Since 2 redundant moduli have beenconsidered for this moduli set error correction of a receivedresidue is possible It makes no difference whether just oneor all bits of the modulo are damaged this can be correctedBased on the damaged bits of the residues we will have

different conditions (eg it is possible that the first andsecond bits the first and third bits or any other combinationof bits are damaged) simulation in C++ language considersall these conditions All possible conditions are simulatedfor 119899 = 2 (ie moduli set 32 31 3 127 511) for 119899 = 3

(ie moduli set 128 127 7 1023 8191) and for 119899 = 4 (iemoduli set 512 511 15 8191 131071 and each time a partof data was damaged intentionally to investigate detectionand correction capability of the method Table 3 displayserror detection percentage for different values of 119899 It alsogives the most number of bits of a modulus that are correctedfor various 119899 values

We evaluated the proposed scheme throughNS-2 simula-tion tool [35] We considered a randomly deployed networkthat is one hundred nodes that were initially spread over anarea of 100 square meters in a random manner The radiocoverage of each sensor node and sink was assumed to bea circular area of 100m in diameter The antenna modeldeployed was omnidirectional Also the initial energy ofsensor nodes set to 01 Joule

The proposed scheme was analyzed in terms of energyconsumption end-to-end delay and network lifetime usingSTCP [21] DTSN [22] TCP and Reed Solomon Table 4shows the simulation parameters

All simulations were repeated 10 times before calculatingthe average of the results As illustrated in Figure 2 the sim-ulation results confirm that the proposed scheme consumessignificantly less energy than the other schemes investigatedIn Figure 3 end-to-end delay is examined where it can beseen that the proposed scheme generates less network delayFinally in Figure 4 it is easy to see that the proposed schemeoutperforms its counterparts in terms of network lifetime

6 Conclusion

In this paper authors unveiled an innovative energy-efficientalgorithm for real time wireless sensor networks that wasbased on a new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1 By

exploiting the MRC technique an efficient reverse converterwas also designed which overcame two-key constraintsnamely component space and high speed operation In orderto take full advantage of the error controllability property ofthe proposed solution two-redundant-moduli sets were thenadded to the initial three main sets resulting in a combinedset 22119899+1 22119899+1 minus 1 2

119899minus 1 23119899+1

minus 1 24119899+1

minus 1

The new methodrsquos error correction capability was foundto be (2119899 + 1) bits under the ideal condition and errordetection improvement reached a figure of 9901 under theworst case scenario condition and 100 when (119899 ge 3)

8 International Journal of Distributed Sensor Networks

0

05

1

15

2

25

3

TCP STCP DTSN RS(15 9 7) Proposedmethod

Tota

l ene

rgy

cons

umpt

ion

(J)

Figure 2 Total energy consumption

250260270280290300310320330340

TCP STCP DTSN RS(15 9 7) Proposedmethod

End-

to-e

nd d

elay

(s)

Figure 3 End-to-end delay

Table 4 Simulation parameters

Area of sensor field 100 lowast 100m2

Antenna model OmnidirectionalSimulation time 1000 SRadio range of a sensor node 100mNumber of sensor nodes 100Initial energy 01 JInterface queue type DroptailInterface queue (IFQ) length 50 PacketsEnergy model Battery

By simulating the proposed error control scheme usingan ns-2 network simulation tool and making comparisonsagainst some popular methods outperformance in terms ofreductions of energy consumption and end-to-end delay aswell as extension of network lifetime was clearly evidentThese advantages therefore make the proposed methodmoredesirable for real-time wireless sensor network applicationswhere reliability low energy consumption and high speedoperations are absolute necessities

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

86889092949698

100102104106

TCP STCP DTSN RS(15 9 7) Proposedmethod

Aver

age l

ifetim

e (s)

Figure 4 Average network lifetime

References

[1] G Song Y Zhou F Ding and A Song ldquoA mobile sensornetwork system for monitoring of unfriendly environmentsrdquoSensors vol 8 no 11 pp 7259ndash7274 2008

[2] J Lloret M Garcia D Bri and S Sendra ldquoA wireless sensornetwork deployment for rural and forest fire detection andverificationrdquo Sensors vol 9 no 11 pp 8722ndash8747 2009

[3] M Dunbabin and L Marques ldquoRobots for environmentalmonitoring significant advancements and applicationsrdquo IEEERobotics and Automation Magazine vol 19 no 1 pp 24ndash392012

[4] P Kumar S-G Lee and H-J Lee ldquoE-SAP efficient-strongauthentication protocol for healthcare applications using wire-less medical sensor networksrdquo Sensors vol 12 no 2 pp 1625ndash1647 2012

[5] Y-M Hong H-C Lin and Y-C Kan ldquoUsing wireless sensornetwork on real-time remote monitoring of the load cell forlandsliderdquo Sensor Letters vol 9 no 5 pp 1911ndash1915 2011

[6] S Khodadoustan F Jalali and A Ejlali ldquoReliabilityenergytrade-off in Bluetooth error control schemesrdquo MicroelectronicsReliability vol 51 no 8 pp 1398ndash1412 2011

[7] J Yick B Mukherjee and D Ghosal ldquoWireless sensor networksurveyrdquoComputerNetworks vol 52 no 12 pp 2292ndash2330 2008

[8] Z Guo B Wang P Xie W Zeng and J-H Cui ldquoEfficient errorrecovery with network coding in underwater sensor networksrdquoAd Hoc Networks vol 7 no 4 pp 791ndash802 2009

[9] I F Akyildiz and M C Vuran Wireless Sensor Networks JohnWiley amp Sons Chichester UK 2010

[10] E Cayırcı and C Rong Security in Wireless Ad Hoc and SensorNetworks John Wiley amp Sons Chichester UK 2009

[11] J H Kleinschmidt W C Borelli and M E Pellenz ldquoAnenergy efficiency model for adaptive and custom error controlschemes in Bluetooth sensor networksrdquo International Journal ofElectronics and Communications (AEU) vol 63 no 3 pp 188ndash199 2009

[12] A S Molahosseini K Navi C Dadkhah O Kavehei and STimarchi ldquoEfficient reverse converter designs for the new 4-moduli sets 2

119899minus 1 2

119899 2119899+ 1 2

2119899+1minus 1 and 2

119899minus 1 2

119899+

1 22119899 22119899+1 based onnewCRTsrdquo IEEETransactions onCircuits

and Systems I vol 57 no 4 pp 823ndash835 2010[13] B Cao C-H Chang and T Srikanthan ldquoA residue-to-binary

converter for a new five-moduli setrdquo IEEE Transactions onCircuits and Systems I vol 54 no 5 pp 1041ndash1049 2007

[14] A S Molahosseini C Dadkhah and K Navi ldquoA new five-moduli set for efficient hardware implementation of the reverse

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

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Journal ofEngineeringVolume 2014

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Shock and Vibration

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Mechanical Engineering

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Journal of

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Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

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Active and Passive Electronic Components

Advances inOptoElectronics

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Chemical EngineeringInternational Journal of

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Control Scienceand Engineering

Journal of

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Antennas andPropagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

6 International Journal of Distributed Sensor Networks

where

11988131

=100381610038161003816100381610038162119899minus1

times 1199093

100381610038161003816100381610038162119899minus1= 11990930⏟⏟⏟⏟⏟⏟⏟1bit

1199093119899minus1

sdot sdot sdot 11990931⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

(119899minus1)bits

11988132

=10038161003816100381610038161003816minus2119899minus1

times 1199091

100381610038161003816100381610038162119899minus1=

10

1119899minus1

sdot sdot sdot 11

1119899

12119899minus1

sdot sdot sdot 1119899+1

+

12119899⏟⏟⏟⏟⏟⏟⏟1bit

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

11988133

=1003816100381610038161003816minus1198812

10038161003816100381610038162119899minus1 =

2119899minus1

sdot sdot sdot 2120

22119899minus1

sdot sdot sdot 2119899+1

2119899+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(119899minus1)bits

22119899⏟⏟⏟⏟⏟⏟⏟1bit

(16)

Finally to obtain119883 based on (9) we have

119883 = 1199091+ 1198751(1198812+ 11988131198752)

= 1199091+ (22119899+1

) (1198812+ (22119899+1

minus 1)1198813)⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119862

= 1199091+ (22119899+1

) 119862

119862 = 1198812+ (22119899+1

minus 1)1198813

119862 =

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞1198813119899minus1

sdot sdot sdot 11988130

(119899+1)bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞11988122119899

11988122119899minus1

sdot sdot sdot 1198812119899

119899bits⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞3119899minus1

sdot sdot sdot 30

+

1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1 sdot sdot sdot 1⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟(2119899+1)bits

1198812119899minus1

sdot sdot sdot 11988120⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟

119899bits

119883 = 1199091+ (22119899+1

) 119862 = Concatenation (1199091 119862)

(17)

The area and delay specifications for the proposed reverseconverter are shown in Table 1

From this Table we have

Total area = (7119899 + 3)119860FA + (5119899 + 2)119860NOT

+ (4119899 minus 1)119860OR + (4119899 minus 1)119860XNOR

Total delay = (9119899 + 8) 119905FA + 3119905NOT

(18)

Now let us discuss comparison of the proposed reverseconverterrsquos performance for the newmoduli set 22119899+1 22119899+1minus1 2119899minus1 against competing models that have either the same

or a lower dynamic range in terms of hardware requirementand speed of operations It should be noted that in any reverseconverter most of the delay is associated with full adderswhich also occupy the largest area allocated to componentsassembly Thus for the sake of comparison it is sufficient toinvestigate only 119860FA and 119905FA see Table 2

5 Performance Evaluation

In this section the performance of the proposed moduli set22119899+1

22119899+1

minus1 2119899minus1 23119899+1

minus1 24119899+1

minus1 is evaluated in termsof error detection and error correction capabilities Evalua-tion of the error control capability requires an investigation of

Table 1 Characterization of each part of the proposed reverseconverter

Parts FA NOT ANDXOR ORXNOR DelayOPU 1 mdash (2119899 + 1) mdash mdash 119905NOT

CPA 1 (2119899 + 1) mdash mdash mdash (4119899 + 2)119905FA

CSA 1 119873 mdash mdash mdash 119905FA

CSA 2 1 mdash mdash (119899 minus 1) 119905FA

OPU 2 mdash (2119899 + 1) mdash mdash 119905NOT

CSA 3 119873 mdash mdash mdash 119905FA

CSA 4 119873 mdash mdash mdash 119905FA

CSA 5 1 mdash mdash (119899 minus 1) 119905FA

CPA 2 119873 mdash mdash mdash (2119899)119905FA

OPU 3 mdash 119873 mdash mdash 119905NOT

119877minus CPA 119873 mdash mdash (2119899 + 1) (3119899 + 1)119905FA

Table 2 Area and Delay comparison

Reverse converter Area (119860FA) Delay (119905FA)[12] 8119899 + 2 12119899 + 5

[13] (51198992+ 43119899)6 + 16119899 minus 1 18119899 + 7

[14] 10119899 + 5 13119899 + 1

[15] 125119899 + 6 12119899 + 6

[16] 10119899 + 5 12119899 + 1

[17]-1 9119899 + 5 115119899 + 6

[17]-2 1198992+ 12119899 + 12 16119899 + 22

[17]-3 9119899 + 10 11119899 + 14

[18] 11989922 + 11119899 + 14 11119899 + 8

[19]-CICE 251198992+ 255119899 + 12 18119899 + 23

[19]-CIHS 251198992+ 375119899 + 28 12119899 + 15

[19]-C2CE 20119899 + 17 13119899 + 22

[19]-C3CE 23119899 + 11 16119899 + 14

Proposed 7119899 + 3 9119899 + 8

the effectiveness of the employed ldquoerror correctionrdquo approachIn general an error control technique is divided into twoparts ldquoerror detectionrdquo and ldquoerror detection and correctionrdquoFor simplicityrsquos sake here we refer to ldquoerror correctionrdquo tomean both error detection and correction noting that errorbits must first be detected and located before they can becorrected Referring to the residue number system one of itsfeatures is that it can correct ldquoburst errorsrdquo

This means that if error bits are residing in one modulothe error control algorithm can easily detect and correctthem However when error bits are located in more thanone modulo they cannot be corrected although it may bepossible to detect them So the aim now is to discover whatthe average percentage of error detection is when error bitsreside in more than one modulo by employing the proposedRNS based solution

In the proposedmoduli set 22119899+1 22119899+1minus1 2119899minus1 23119899+1minus1 24119899+1

minus 1 22119899+1 22119899+1 minus 1 2119899minus 1 are the main three and

23119899+1

minus 1 24119899+1

minus 1 are the redundant moduli respectivelyNow the first second and third main moduli are (2119899 +

1) (2119899+1) and (119899) bits respectively Given this architecturethe error bits can only be detected and corrected if (a) they are

International Journal of Distributed Sensor Networks 7

Table 3 Area and delay comparison

119873 Main modulus Redundant Modulus Maximum error correction Error detection capabilityError bits in one modulo Error bits in two modulus

2 32 31 3 127 511 5 bits 100 99373 128 127 7 1023 8191 7 bits 100 1004 512 511 15 8191 131071 9 bits 100 100

placed either in the first the second or the third modulo (b)maximum error bit count does not exceed (2119899 + 1) (2119899 + 1)and (119899) respectively Hence the maximum achievable errorcorrection capability is equal to (2119899 + 1) error bits occurringin the first or the second modulo On the other hand theminimum correction capability that can be achieved usingthe proposed modulus set is equal to one error bit within anymodulo of the received packet

In the proposed error control method first sensed dataare divided by the proposed moduli set and then the residuesare computed Next the nodes transmit the residues insteadof sensed data After receiving residues sink computes theoriginal data using 3mainmoduli and their received residuesWhen the residue of the computed number has been dividedby redundant moduli and the received residues for thoseredundantmoduli are not equal an error is detected and errorcorrection procedure is called for it Sink can reconstructthe original data using 3 residues out of the 5 residues andMRC reverse converterThere are only 10 possible conditionsfor selecting 3 residues out of 5 residues (1198625

3= ( 53) =

(5(2 lowast 3)) = 10) Sink computes the original data forall of these possible conditions Given the fact that duringdata transfer some residuesmay have contained errors not allsink computed numbers are accurate and equalThus amongthese 10 numbers those out of dynamic range are removedAfter a voting process those numbers that have received thegreatest votes are selected as correct numbers

In order to gauge the error detection capability of theproposed set in a situation where errors occur in morethan one modulo and where therefore no correction ispossible we simulated the behavior of the error controlalgorithm using C++ programming language The experi-ment runs 3010158400001015840000 different error bit states by setting119899 = 2 3 4 Substituting these values for 119899 in the setwe obtain 32 31 3 127 511 128 127 7 1023 8191 and512 511 15 8191 131071 respectively The test results aredisplayed in Table 3 Note that themaximum error correctionis equal to (2119899 + 1) bits as was mentioned before and thethree error states considered are bits which are located in oneof the main modulus (correction is possible and detection is100) bits which are located in two moduli and finally thecase where bits are resided in three moduli

With reference to Table 3 there are several individualconditions for error detection among the 5 received residuesonly 1 residue contains error 2 residues contain error 3residues contain error Since 2 redundant moduli have beenconsidered for this moduli set error correction of a receivedresidue is possible It makes no difference whether just oneor all bits of the modulo are damaged this can be correctedBased on the damaged bits of the residues we will have

different conditions (eg it is possible that the first andsecond bits the first and third bits or any other combinationof bits are damaged) simulation in C++ language considersall these conditions All possible conditions are simulatedfor 119899 = 2 (ie moduli set 32 31 3 127 511) for 119899 = 3

(ie moduli set 128 127 7 1023 8191) and for 119899 = 4 (iemoduli set 512 511 15 8191 131071 and each time a partof data was damaged intentionally to investigate detectionand correction capability of the method Table 3 displayserror detection percentage for different values of 119899 It alsogives the most number of bits of a modulus that are correctedfor various 119899 values

We evaluated the proposed scheme throughNS-2 simula-tion tool [35] We considered a randomly deployed networkthat is one hundred nodes that were initially spread over anarea of 100 square meters in a random manner The radiocoverage of each sensor node and sink was assumed to bea circular area of 100m in diameter The antenna modeldeployed was omnidirectional Also the initial energy ofsensor nodes set to 01 Joule

The proposed scheme was analyzed in terms of energyconsumption end-to-end delay and network lifetime usingSTCP [21] DTSN [22] TCP and Reed Solomon Table 4shows the simulation parameters

All simulations were repeated 10 times before calculatingthe average of the results As illustrated in Figure 2 the sim-ulation results confirm that the proposed scheme consumessignificantly less energy than the other schemes investigatedIn Figure 3 end-to-end delay is examined where it can beseen that the proposed scheme generates less network delayFinally in Figure 4 it is easy to see that the proposed schemeoutperforms its counterparts in terms of network lifetime

6 Conclusion

In this paper authors unveiled an innovative energy-efficientalgorithm for real time wireless sensor networks that wasbased on a new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1 By

exploiting the MRC technique an efficient reverse converterwas also designed which overcame two-key constraintsnamely component space and high speed operation In orderto take full advantage of the error controllability property ofthe proposed solution two-redundant-moduli sets were thenadded to the initial three main sets resulting in a combinedset 22119899+1 22119899+1 minus 1 2

119899minus 1 23119899+1

minus 1 24119899+1

minus 1

The new methodrsquos error correction capability was foundto be (2119899 + 1) bits under the ideal condition and errordetection improvement reached a figure of 9901 under theworst case scenario condition and 100 when (119899 ge 3)

8 International Journal of Distributed Sensor Networks

0

05

1

15

2

25

3

TCP STCP DTSN RS(15 9 7) Proposedmethod

Tota

l ene

rgy

cons

umpt

ion

(J)

Figure 2 Total energy consumption

250260270280290300310320330340

TCP STCP DTSN RS(15 9 7) Proposedmethod

End-

to-e

nd d

elay

(s)

Figure 3 End-to-end delay

Table 4 Simulation parameters

Area of sensor field 100 lowast 100m2

Antenna model OmnidirectionalSimulation time 1000 SRadio range of a sensor node 100mNumber of sensor nodes 100Initial energy 01 JInterface queue type DroptailInterface queue (IFQ) length 50 PacketsEnergy model Battery

By simulating the proposed error control scheme usingan ns-2 network simulation tool and making comparisonsagainst some popular methods outperformance in terms ofreductions of energy consumption and end-to-end delay aswell as extension of network lifetime was clearly evidentThese advantages therefore make the proposed methodmoredesirable for real-time wireless sensor network applicationswhere reliability low energy consumption and high speedoperations are absolute necessities

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

86889092949698

100102104106

TCP STCP DTSN RS(15 9 7) Proposedmethod

Aver

age l

ifetim

e (s)

Figure 4 Average network lifetime

References

[1] G Song Y Zhou F Ding and A Song ldquoA mobile sensornetwork system for monitoring of unfriendly environmentsrdquoSensors vol 8 no 11 pp 7259ndash7274 2008

[2] J Lloret M Garcia D Bri and S Sendra ldquoA wireless sensornetwork deployment for rural and forest fire detection andverificationrdquo Sensors vol 9 no 11 pp 8722ndash8747 2009

[3] M Dunbabin and L Marques ldquoRobots for environmentalmonitoring significant advancements and applicationsrdquo IEEERobotics and Automation Magazine vol 19 no 1 pp 24ndash392012

[4] P Kumar S-G Lee and H-J Lee ldquoE-SAP efficient-strongauthentication protocol for healthcare applications using wire-less medical sensor networksrdquo Sensors vol 12 no 2 pp 1625ndash1647 2012

[5] Y-M Hong H-C Lin and Y-C Kan ldquoUsing wireless sensornetwork on real-time remote monitoring of the load cell forlandsliderdquo Sensor Letters vol 9 no 5 pp 1911ndash1915 2011

[6] S Khodadoustan F Jalali and A Ejlali ldquoReliabilityenergytrade-off in Bluetooth error control schemesrdquo MicroelectronicsReliability vol 51 no 8 pp 1398ndash1412 2011

[7] J Yick B Mukherjee and D Ghosal ldquoWireless sensor networksurveyrdquoComputerNetworks vol 52 no 12 pp 2292ndash2330 2008

[8] Z Guo B Wang P Xie W Zeng and J-H Cui ldquoEfficient errorrecovery with network coding in underwater sensor networksrdquoAd Hoc Networks vol 7 no 4 pp 791ndash802 2009

[9] I F Akyildiz and M C Vuran Wireless Sensor Networks JohnWiley amp Sons Chichester UK 2010

[10] E Cayırcı and C Rong Security in Wireless Ad Hoc and SensorNetworks John Wiley amp Sons Chichester UK 2009

[11] J H Kleinschmidt W C Borelli and M E Pellenz ldquoAnenergy efficiency model for adaptive and custom error controlschemes in Bluetooth sensor networksrdquo International Journal ofElectronics and Communications (AEU) vol 63 no 3 pp 188ndash199 2009

[12] A S Molahosseini K Navi C Dadkhah O Kavehei and STimarchi ldquoEfficient reverse converter designs for the new 4-moduli sets 2

119899minus 1 2

119899 2119899+ 1 2

2119899+1minus 1 and 2

119899minus 1 2

119899+

1 22119899 22119899+1 based onnewCRTsrdquo IEEETransactions onCircuits

and Systems I vol 57 no 4 pp 823ndash835 2010[13] B Cao C-H Chang and T Srikanthan ldquoA residue-to-binary

converter for a new five-moduli setrdquo IEEE Transactions onCircuits and Systems I vol 54 no 5 pp 1041ndash1049 2007

[14] A S Molahosseini C Dadkhah and K Navi ldquoA new five-moduli set for efficient hardware implementation of the reverse

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Mechanical Engineering

Advances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Antennas andPropagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

International Journal of Distributed Sensor Networks 7

Table 3 Area and delay comparison

119873 Main modulus Redundant Modulus Maximum error correction Error detection capabilityError bits in one modulo Error bits in two modulus

2 32 31 3 127 511 5 bits 100 99373 128 127 7 1023 8191 7 bits 100 1004 512 511 15 8191 131071 9 bits 100 100

placed either in the first the second or the third modulo (b)maximum error bit count does not exceed (2119899 + 1) (2119899 + 1)and (119899) respectively Hence the maximum achievable errorcorrection capability is equal to (2119899 + 1) error bits occurringin the first or the second modulo On the other hand theminimum correction capability that can be achieved usingthe proposed modulus set is equal to one error bit within anymodulo of the received packet

In the proposed error control method first sensed dataare divided by the proposed moduli set and then the residuesare computed Next the nodes transmit the residues insteadof sensed data After receiving residues sink computes theoriginal data using 3mainmoduli and their received residuesWhen the residue of the computed number has been dividedby redundant moduli and the received residues for thoseredundantmoduli are not equal an error is detected and errorcorrection procedure is called for it Sink can reconstructthe original data using 3 residues out of the 5 residues andMRC reverse converterThere are only 10 possible conditionsfor selecting 3 residues out of 5 residues (1198625

3= ( 53) =

(5(2 lowast 3)) = 10) Sink computes the original data forall of these possible conditions Given the fact that duringdata transfer some residuesmay have contained errors not allsink computed numbers are accurate and equalThus amongthese 10 numbers those out of dynamic range are removedAfter a voting process those numbers that have received thegreatest votes are selected as correct numbers

In order to gauge the error detection capability of theproposed set in a situation where errors occur in morethan one modulo and where therefore no correction ispossible we simulated the behavior of the error controlalgorithm using C++ programming language The experi-ment runs 3010158400001015840000 different error bit states by setting119899 = 2 3 4 Substituting these values for 119899 in the setwe obtain 32 31 3 127 511 128 127 7 1023 8191 and512 511 15 8191 131071 respectively The test results aredisplayed in Table 3 Note that themaximum error correctionis equal to (2119899 + 1) bits as was mentioned before and thethree error states considered are bits which are located in oneof the main modulus (correction is possible and detection is100) bits which are located in two moduli and finally thecase where bits are resided in three moduli

With reference to Table 3 there are several individualconditions for error detection among the 5 received residuesonly 1 residue contains error 2 residues contain error 3residues contain error Since 2 redundant moduli have beenconsidered for this moduli set error correction of a receivedresidue is possible It makes no difference whether just oneor all bits of the modulo are damaged this can be correctedBased on the damaged bits of the residues we will have

different conditions (eg it is possible that the first andsecond bits the first and third bits or any other combinationof bits are damaged) simulation in C++ language considersall these conditions All possible conditions are simulatedfor 119899 = 2 (ie moduli set 32 31 3 127 511) for 119899 = 3

(ie moduli set 128 127 7 1023 8191) and for 119899 = 4 (iemoduli set 512 511 15 8191 131071 and each time a partof data was damaged intentionally to investigate detectionand correction capability of the method Table 3 displayserror detection percentage for different values of 119899 It alsogives the most number of bits of a modulus that are correctedfor various 119899 values

We evaluated the proposed scheme throughNS-2 simula-tion tool [35] We considered a randomly deployed networkthat is one hundred nodes that were initially spread over anarea of 100 square meters in a random manner The radiocoverage of each sensor node and sink was assumed to bea circular area of 100m in diameter The antenna modeldeployed was omnidirectional Also the initial energy ofsensor nodes set to 01 Joule

The proposed scheme was analyzed in terms of energyconsumption end-to-end delay and network lifetime usingSTCP [21] DTSN [22] TCP and Reed Solomon Table 4shows the simulation parameters

All simulations were repeated 10 times before calculatingthe average of the results As illustrated in Figure 2 the sim-ulation results confirm that the proposed scheme consumessignificantly less energy than the other schemes investigatedIn Figure 3 end-to-end delay is examined where it can beseen that the proposed scheme generates less network delayFinally in Figure 4 it is easy to see that the proposed schemeoutperforms its counterparts in terms of network lifetime

6 Conclusion

In this paper authors unveiled an innovative energy-efficientalgorithm for real time wireless sensor networks that wasbased on a new 3-moduli set 22119899+1 22119899+1 minus 1 2

119899minus 1 By

exploiting the MRC technique an efficient reverse converterwas also designed which overcame two-key constraintsnamely component space and high speed operation In orderto take full advantage of the error controllability property ofthe proposed solution two-redundant-moduli sets were thenadded to the initial three main sets resulting in a combinedset 22119899+1 22119899+1 minus 1 2

119899minus 1 23119899+1

minus 1 24119899+1

minus 1

The new methodrsquos error correction capability was foundto be (2119899 + 1) bits under the ideal condition and errordetection improvement reached a figure of 9901 under theworst case scenario condition and 100 when (119899 ge 3)

8 International Journal of Distributed Sensor Networks

0

05

1

15

2

25

3

TCP STCP DTSN RS(15 9 7) Proposedmethod

Tota

l ene

rgy

cons

umpt

ion

(J)

Figure 2 Total energy consumption

250260270280290300310320330340

TCP STCP DTSN RS(15 9 7) Proposedmethod

End-

to-e

nd d

elay

(s)

Figure 3 End-to-end delay

Table 4 Simulation parameters

Area of sensor field 100 lowast 100m2

Antenna model OmnidirectionalSimulation time 1000 SRadio range of a sensor node 100mNumber of sensor nodes 100Initial energy 01 JInterface queue type DroptailInterface queue (IFQ) length 50 PacketsEnergy model Battery

By simulating the proposed error control scheme usingan ns-2 network simulation tool and making comparisonsagainst some popular methods outperformance in terms ofreductions of energy consumption and end-to-end delay aswell as extension of network lifetime was clearly evidentThese advantages therefore make the proposed methodmoredesirable for real-time wireless sensor network applicationswhere reliability low energy consumption and high speedoperations are absolute necessities

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

86889092949698

100102104106

TCP STCP DTSN RS(15 9 7) Proposedmethod

Aver

age l

ifetim

e (s)

Figure 4 Average network lifetime

References

[1] G Song Y Zhou F Ding and A Song ldquoA mobile sensornetwork system for monitoring of unfriendly environmentsrdquoSensors vol 8 no 11 pp 7259ndash7274 2008

[2] J Lloret M Garcia D Bri and S Sendra ldquoA wireless sensornetwork deployment for rural and forest fire detection andverificationrdquo Sensors vol 9 no 11 pp 8722ndash8747 2009

[3] M Dunbabin and L Marques ldquoRobots for environmentalmonitoring significant advancements and applicationsrdquo IEEERobotics and Automation Magazine vol 19 no 1 pp 24ndash392012

[4] P Kumar S-G Lee and H-J Lee ldquoE-SAP efficient-strongauthentication protocol for healthcare applications using wire-less medical sensor networksrdquo Sensors vol 12 no 2 pp 1625ndash1647 2012

[5] Y-M Hong H-C Lin and Y-C Kan ldquoUsing wireless sensornetwork on real-time remote monitoring of the load cell forlandsliderdquo Sensor Letters vol 9 no 5 pp 1911ndash1915 2011

[6] S Khodadoustan F Jalali and A Ejlali ldquoReliabilityenergytrade-off in Bluetooth error control schemesrdquo MicroelectronicsReliability vol 51 no 8 pp 1398ndash1412 2011

[7] J Yick B Mukherjee and D Ghosal ldquoWireless sensor networksurveyrdquoComputerNetworks vol 52 no 12 pp 2292ndash2330 2008

[8] Z Guo B Wang P Xie W Zeng and J-H Cui ldquoEfficient errorrecovery with network coding in underwater sensor networksrdquoAd Hoc Networks vol 7 no 4 pp 791ndash802 2009

[9] I F Akyildiz and M C Vuran Wireless Sensor Networks JohnWiley amp Sons Chichester UK 2010

[10] E Cayırcı and C Rong Security in Wireless Ad Hoc and SensorNetworks John Wiley amp Sons Chichester UK 2009

[11] J H Kleinschmidt W C Borelli and M E Pellenz ldquoAnenergy efficiency model for adaptive and custom error controlschemes in Bluetooth sensor networksrdquo International Journal ofElectronics and Communications (AEU) vol 63 no 3 pp 188ndash199 2009

[12] A S Molahosseini K Navi C Dadkhah O Kavehei and STimarchi ldquoEfficient reverse converter designs for the new 4-moduli sets 2

119899minus 1 2

119899 2119899+ 1 2

2119899+1minus 1 and 2

119899minus 1 2

119899+

1 22119899 22119899+1 based onnewCRTsrdquo IEEETransactions onCircuits

and Systems I vol 57 no 4 pp 823ndash835 2010[13] B Cao C-H Chang and T Srikanthan ldquoA residue-to-binary

converter for a new five-moduli setrdquo IEEE Transactions onCircuits and Systems I vol 54 no 5 pp 1041ndash1049 2007

[14] A S Molahosseini C Dadkhah and K Navi ldquoA new five-moduli set for efficient hardware implementation of the reverse

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Mechanical Engineering

Advances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Antennas andPropagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

8 International Journal of Distributed Sensor Networks

0

05

1

15

2

25

3

TCP STCP DTSN RS(15 9 7) Proposedmethod

Tota

l ene

rgy

cons

umpt

ion

(J)

Figure 2 Total energy consumption

250260270280290300310320330340

TCP STCP DTSN RS(15 9 7) Proposedmethod

End-

to-e

nd d

elay

(s)

Figure 3 End-to-end delay

Table 4 Simulation parameters

Area of sensor field 100 lowast 100m2

Antenna model OmnidirectionalSimulation time 1000 SRadio range of a sensor node 100mNumber of sensor nodes 100Initial energy 01 JInterface queue type DroptailInterface queue (IFQ) length 50 PacketsEnergy model Battery

By simulating the proposed error control scheme usingan ns-2 network simulation tool and making comparisonsagainst some popular methods outperformance in terms ofreductions of energy consumption and end-to-end delay aswell as extension of network lifetime was clearly evidentThese advantages therefore make the proposed methodmoredesirable for real-time wireless sensor network applicationswhere reliability low energy consumption and high speedoperations are absolute necessities

Conflict of Interests

The authors declare that there is no conflict of interestsregarding the publication of this paper

86889092949698

100102104106

TCP STCP DTSN RS(15 9 7) Proposedmethod

Aver

age l

ifetim

e (s)

Figure 4 Average network lifetime

References

[1] G Song Y Zhou F Ding and A Song ldquoA mobile sensornetwork system for monitoring of unfriendly environmentsrdquoSensors vol 8 no 11 pp 7259ndash7274 2008

[2] J Lloret M Garcia D Bri and S Sendra ldquoA wireless sensornetwork deployment for rural and forest fire detection andverificationrdquo Sensors vol 9 no 11 pp 8722ndash8747 2009

[3] M Dunbabin and L Marques ldquoRobots for environmentalmonitoring significant advancements and applicationsrdquo IEEERobotics and Automation Magazine vol 19 no 1 pp 24ndash392012

[4] P Kumar S-G Lee and H-J Lee ldquoE-SAP efficient-strongauthentication protocol for healthcare applications using wire-less medical sensor networksrdquo Sensors vol 12 no 2 pp 1625ndash1647 2012

[5] Y-M Hong H-C Lin and Y-C Kan ldquoUsing wireless sensornetwork on real-time remote monitoring of the load cell forlandsliderdquo Sensor Letters vol 9 no 5 pp 1911ndash1915 2011

[6] S Khodadoustan F Jalali and A Ejlali ldquoReliabilityenergytrade-off in Bluetooth error control schemesrdquo MicroelectronicsReliability vol 51 no 8 pp 1398ndash1412 2011

[7] J Yick B Mukherjee and D Ghosal ldquoWireless sensor networksurveyrdquoComputerNetworks vol 52 no 12 pp 2292ndash2330 2008

[8] Z Guo B Wang P Xie W Zeng and J-H Cui ldquoEfficient errorrecovery with network coding in underwater sensor networksrdquoAd Hoc Networks vol 7 no 4 pp 791ndash802 2009

[9] I F Akyildiz and M C Vuran Wireless Sensor Networks JohnWiley amp Sons Chichester UK 2010

[10] E Cayırcı and C Rong Security in Wireless Ad Hoc and SensorNetworks John Wiley amp Sons Chichester UK 2009

[11] J H Kleinschmidt W C Borelli and M E Pellenz ldquoAnenergy efficiency model for adaptive and custom error controlschemes in Bluetooth sensor networksrdquo International Journal ofElectronics and Communications (AEU) vol 63 no 3 pp 188ndash199 2009

[12] A S Molahosseini K Navi C Dadkhah O Kavehei and STimarchi ldquoEfficient reverse converter designs for the new 4-moduli sets 2

119899minus 1 2

119899 2119899+ 1 2

2119899+1minus 1 and 2

119899minus 1 2

119899+

1 22119899 22119899+1 based onnewCRTsrdquo IEEETransactions onCircuits

and Systems I vol 57 no 4 pp 823ndash835 2010[13] B Cao C-H Chang and T Srikanthan ldquoA residue-to-binary

converter for a new five-moduli setrdquo IEEE Transactions onCircuits and Systems I vol 54 no 5 pp 1041ndash1049 2007

[14] A S Molahosseini C Dadkhah and K Navi ldquoA new five-moduli set for efficient hardware implementation of the reverse

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Mechanical Engineering

Advances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Antennas andPropagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

International Journal of Distributed Sensor Networks 9

converterrdquo IEICE Electronics Express vol 6 no 14 pp 1006ndash1012 2009

[15] M Esmaeildoust K Navi and M Taheri ldquoHigh speed reverseconverter for new five-moduli set 2119899 22119899+1 minus 1 2

1198992minus 1 2

1198992+

1 2119899+ 1rdquo IEICE Electronics Express vol 7 no 3 pp 118ndash125

2010[16] A S Molahosseini and M K Rafsanjani ldquoAn improved five-

modulus reverse converterrdquo World Applied Sciences vol 11 no2 pp 132ndash135 2010

[17] P V Ananda Mohan and A B Premkumar ldquoRNS-to-binaryconverters for two four-moduli sets 2119899 minus 1 2

119899 2119899+ 1 2

119899+1minus 1

and 2119899minus 1 2

119899 2119899+ 1 2

119899+1+ 1rdquo IEEE Transactions on Circuits

and Systems I vol 54 no 6 pp 1245ndash1254 2007[18] B Cao T Srikanthan and C H Chang ldquoEfficient reverse

converters for four moduli sets 2119899 minus 1 2119899 2119899+ 1 2

119899+1minus 1 and

2119899minus 1 2

119899 2119899+ 1 2

119899minus1minus 1rdquo IEE Proceedings on Computers and

Digital Techniques vol 152 no 5 pp 687ndash696 2005[19] P V AnandaMohan ldquoNew reverse converters for themoduli set

2119899minus3 2119899minus1 2119899+1 2119899+3rdquo International Journal of Electronics

and Communications (AEU) vol 62 no 9 pp 643ndash658 2008[20] P Xie Z Zhou Z Peng J-H Cui and Z Shi ldquoSDRT a reliable

data transport protocol for underwater sensor networksrdquo AdHoc Networks vol 8 no 7 pp 708ndash722 2010

[21] Y G Iyer S Gandham and S Venkatesan ldquoSTCP a generictransport layer protocol for wireless sensor networksrdquo inProceedings of the 14th International Conference on ComputerCommunications and Networks (ICCCN rsquo05) pp 449ndash454 SanDiego Calif USA October 2005

[22] B Marchi A Grilo and M Nunes ldquoDTSN distributed trans-port for sensor networksrdquo in Proceedings of the 12th IEEEInternational Symposium on Computers and Communications(ISCC rsquo07) pp 165ndash172 Aveiro Portugal July 2007

[23] M Hosseinzadeh A S Molahosseini and K Navi ldquoAnimproved reverse converter for the moduli set 2119899 minus 1 2

119899 2119899+

1 2119899+1

minus1rdquo IEICE Electronics Express vol 5 no 17 pp 672ndash6772008

[24] H Garner ldquoThe residue number systemrdquo IEEE TransactionsElectronic Computer vol 8 pp 140ndash147 1959

[25] K Navi A S Molahosseini and M Esmaeildoust ldquoHowto teach residue number system to computer scientists andengineersrdquo IEEE Transactions on Education vol 54 no 1 pp156ndash163 2011

[26] R Chokshi K S Berezowski A Shrivastava and S J PiestrakldquoExploiting residue number system for power-efficient digitalsignal processing in embedded processorsrdquo in Proceedings ofthe International Conference on Compilers Architecture andSynthesis for Embedded Systems (CASES rsquo09) pp 19ndash28 October2009

[27] R Conway and J Nelson ldquoImproved RNS FIR filter architec-turesrdquo IEEE Transactions on Circuits and Systems II vol 51 no1 pp 26ndash28 2004

[28] M Wnuk ldquoRemarks on hardware implementation of imageprocessing algorithmsrdquo International Journal of Applied Math-ematics and Computer Science vol 18 no 1 pp 105ndash110 2008

[29] J-C Bajard and L Imbert ldquoA full RNS implementation of RSArdquoIEEE Transactions on Computers vol 53 no 6 pp 769ndash7742004

[30] J Ramırez A Garcıa U Meyer-Baese and A Lloris ldquoFast RNSFPL-based communications receiver design and implementa-tionrdquo in Proceeding of the 12th International Conference FieldProgrammable Logic pp 472ndash481 2002

[31] F J Taylor ldquoResidue arithmetic a tutorial with examplesrdquo IEEEComputer vol 17 no 5 pp 50ndash62 1984

[32] F Barsi and P Maestrini ldquoError correcting properties of redun-dant residue number systemsrdquo IEEETransactions onComputersvol 22 no 3 pp 307ndash315 1973

[33] E Kinoshita and K-J Lee ldquoA residue arithmetic extension forreliable scientific computationrdquo IEEE Transactions on Comput-ers vol 46 no 2 pp 129ndash138 1997

[34] N Z Haron and S Hamdioui ldquoRedundant residue numbersystem code for fault-tolerant hybrid memoriesrdquo ACM Journalon Emerging Technologies in Computing Systems vol 7 no 1article 4 2011

[35] ldquoNetwork simulatormdash(ns-2)rdquo httpwwwisiedunsnamns

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Mechanical Engineering

Advances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Antennas andPropagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Mechanical Engineering

Advances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Distributed Sensor Networks

International Journal of

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Antennas andPropagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of