Copyright © 2009 American Scientific PublishersAll rights reservedPrinted in the United States of America

Journal ofLow Power Electronics

Vol. 5, 1–13, 2009

Energy and Power Consumption Estimation forEmbedded Applications and Operating Systems

Saadia Dhouib1!2!!, Eric Senn1, Jean-Philippe Diguet1, Dominique Blouin1, and Johann Laurent11Lab-STICC, University of South Brittany, Lorient, 56100, France

2CES (Computer and Embedded Systems) Laboratory, ENIS, Sfax, Tunisia

(Received: xx Xxxx Xxxx; Accepted: xx Xxxx Xxxx)

This paper presents a methodology that permits to estimate the power and energy consumptionof embedded applications. Estimation is performed from high-level specifications of the completesystem. Power models are built from physical measurements on the hardware platform. Operatingsystem’s services are modeled: scheduler/timer interrupt, inter-process communications, devicesaccesses models are presented. The operating system’s energy overhead is expressed as the sumof multiple contributions related to services activated during a run. Our methodology is applied to themodeling of a Xillinx Virtex-II Pro XUP platform, and a Linux 2.6 operating system. The comparisonof consumption estimations and measurements for different versions of a multi-threaded MJPEGapplication shows an error ranging from 1% to 11%. Our methodology and power models havebeen integrated in a CAD tool, named CAT (Consumption Analysis Toolbox), deployed in the EclipseIDE and also included in the Open Source AADL Tool Environment, bringing energy estimationcapabilities in the AADL design flow.

Keywords: Power, Energy, Estimation, Model, Operating System, Service, Real-Time,Embedded System, Consumption Analysis Toolbox CAT, AADL.

1. INTRODUCTION

Embedded systems are becoming more and more com-plex. Due to technological improvements, it is now pos-sible to integrate a lot of components in a unique circuit.Nowadays, homogeneous or heterogeneous multiprocessorarchitectures within SoC (System on Chip) or SiP (Sys-tem in a Package) offer increasing computing capacities.Meanwhile, applications are growing in complexity. Thus,embedded systems commonly have to perform differentmultiple tasks, from control oriented (innovative user inter-faces, adaptation to the environment, compliance to newformats, quality of service management) to data intensive(multimedia, audio and video coding/decoding, softwareradio, 3D image processing, communication streaming),and to sustain high throughputs and bandwidths.One side effect of this global evolution is a dras-

tic increase of the circuits’ power consumption. Leakagepower increases exponentially as the process evolves tofiner technologies. Dynamic power is proportional to theoperating frequency. With higher chip densities, thermal

!Author to whom correspondence should be addressed.Email: saadia.dhouib@univ-ubs.fr

dissipation may involve costly cooling devices, and batterylife is definitely shortened.The role of an Operating System (OS) is essential in

such a context. Real Time Operating Systems (RTOS)offer a wide variety of services to ease the exploitation ofembedded platforms: cooperative and pre-emptive multi-tasking, process management, fixed or dynamic priorityscheduling, multi-threading, support for periodic and ape-riodic tasks, semaphores, inter-process communications,shared memory, memory, file, and device management.It offers an abstraction of the hardware that permitsthe reduction of time to design, development, and test-ing of new systems. It also offers power managementservices which may exploit low-level mechanisms (low-operating/low-standby power modes, voltage/frequencyscaling, clock gating! ! !) to reduce the system’s energyconsumption.44

But the Operating System itself has a non negligibleimpact on the energy consumption. The Operating Sys-tem’s energy overhead depends on the complexity of theapplications and the number of services called. In Refs. [1]and [2], it was observed that, depending on the application,the energy consumption of an embedded system could risefrom 6% to 50%. This ratio gets higher if the frequency

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Energy and Power Consumption Estimation for Embedded Applications and Operating Systems Dhouib et al.

and supply voltage of the processor increase. In Ref. [3],it is shown that the OS can consume from 1% to 99%of the processor energy depending on the services called.Power consumption is now a major constraint in manydesigns. Being able to estimate this consumption for thewhole system and for all its components is now compul-sory. Estimating energy consumption due to the OperatingSystems is thus unavoidable. It is the first step towardsthe application of off-line or on-line power optimizationtechniques.It is well-known that high-level optimizations have the

greatest impact on the system’s final performance. How-ever, they are only possible if estimations can be per-formed at the earliest levels in the systems’ design flow.One of our objectives in the European ITEA projectSPICES (Support for Predictable Integration of missionCritical Embedded Systems)4 is to enrich the AADLmodel based design flow to permit precise energy andpower consumption estimations at different levels in therefinement process. AADL (Architecture Analysis andDesign Language) is an input modeling language for thedesign of real-time embedded systems,5 now commonlyused in the avionic and automotive domains. It helps toverify functional and non-functional properties of the sys-tem, from early analysis of the specification to code gen-eration for the hardware platform.6–8

A lot of work has been done on power consumption esti-mation at different abstraction levels in embedded systemsdesign. Many approaches deal with low level models, andare dedicated to the analysis of hardware components, orpart of hardware components. They are not usable for com-plex systems. In this paper, we will focus on approachesintended to assess the power and energy consumptionof a complete system, including its operating system. Infact, the major contribution of this paper, compared toour former publications, is the proposition of a methodol-ogy for estimating the consumption of a complete embed-ded system, and that includes a multi-threaded application,a real-time operating systems with different services, and aheterogeneous hardware platform. Different consumptionmodels associated to the considered operating system ser-vices are presented as well.In the frame of the SPICES project, our consumption

analysis tool and power models are coupled with tim-ing analysis tools working at different abstraction levelsand with various precisions. All those tools can be foundin the OSATE (Open Source AADL Tool Environment)27

and TOPCASED35 tools suite. Energy consumption esti-mations accuracy thus depends on the error introducedby those timing analysis tools. In our paper, we havechosen to present our results considering measured exe-cution time when needed, in order to isolate the errorintroduced by our power models, from the error due tothe timing analysis tools. Hence, the performances of ourapproach should appear more clearly to the reader. Static

or dynamic timing analysis may be performed with toolsrelated to the SPICES project (see Ref. [4]: SoftExplorer,30

BIP,36 TINA,37 PathCrawler,38 ADES,39 MAST40) andAADL (Cheddar41), SystemC simulations at different lev-els, including the operating system (Scope,42 AADS43).

The remainder of this paper is organized as follows.We present related work in Section 2. Section 3 describesour multi-layer estimation methodology. In Section 4,we present power models on which estimation is based.Section 5 presents our consumption analysis toolboxwhich integrates the methodology and related powermodels. In Section 6, we evaluate our methodology byestimating the energy consumption of three multithreadedversions of a MJPEG encoder. We conclude the paper inSection 7.

2. STATE OF THE ART

In Ref. [9], energy estimation of embedded OperatingSystems relies on micro-architectural cycle-accurate sim-ulation. The software energy estimation is performedat four granularity levels: atomic function, routine, ser-vice, and kernel execution path. A full system instructionlevel simulator (based on Skyeye10) provides an instruc-tion and address trace that is an input of the micro-architectural simulator, which includes power models ofmicro-architectural components. The Strong ARM archi-tecture platform running Linux 2.4 is considered. Thisapproach inherits the drawbacks of micro-architecturallevel power analysis, as performed in the tools Wattch11

or SimplePower.12 Firstly, cycle-level simulations mayprove very time consuming for large programs. Secondly,they necessitate a low-level description of the architec-ture which is often difficult to obtain for off-the-shelf pro-cessors. Hardware devices (Ethernet, external memories,Compact Flash/Disks, External controllers ! ! !) are not con-sidered either, even if they can represent the major part ofpower consumption of embedded systems.In Ref. [13], Fournel et al. presented eSimu, a per-

formance and energy consumption simulator for deeplyembedded hardware platforms, again built upon Skyeye.This approach is based on cycle accurate simulations ofcomplete hardware platforms executing the real applica-tion code. Quantitative energy data are gathered at thebattery output and are translated into per instruction andperipheral event energy figures. An ARM9 based embed-ded system is considered. The Operating System overheadis, however, not identified. Energy consumption is reportedat the source code level regardless of any OS or driverimplementation.In Ref. [14] energy estimation is performed at the sys-

tem level. FPGA accelerated simulation technologies areused to speed-up the system simulation. Energy estima-tion currently relies on spreadsheet to compute powerconsumption from the accelerated simulation results, but

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Dhouib et al. Energy and Power Consumption Estimation for Embedded Applications and Operating Systems

analytical models might be used as well. One major draw-back with this approach is the difficulty to validate andcalibrate the simulator against actual implementations onsilicon, which grows with the complexity of processorscore. Tedious porting work is necessary to support newtarget model, since a large number of power measurementsare necessary for every component in the processor core.Byanes et al.15 proposed an execution driven simulation

testbed that measures the execution behavior and powerconsumption of embedded applications and RTOS, by exe-cuting them on an accurate architectural model of a micro-controller with simulated real-time stimuli. The powerconsumption estimation relies on instruction based tech-niques (10–15% error). The so-called Instruction-LevelPower Analysis (ILPA)16 relies on current measurementsfor each instruction and couple of successive instructions.Even if it proved accurate for simple processors, the num-ber of measures needed to obtain a model for a complexarchitecture would become unrealistic.17 In Ref. [15] theinter-instruction overhead is not precisely modelled. Threedifferent RTOS have been compared: "COS-II , Echnida,and NOS.2 However, the overhead of the OS is consideredglobally and not on a per service approach. The differ-ence between the application and OS consumption is notconsidered.In Ref. [18], simpler models of OS power consump-

tion, with few parameters, are proposed. Li et al. consid-ered OS service routines as the fundamental unit of OSexecution and measured that they have similar and pre-dictable power dissipation behaviors across various bench-marks. They found strong correlation between the powerand the Instruction Per Cycle (IPC) metric, and developeda model that exploits this correlation. Instruction Per Cycleis similar to the parallelism rate that we introduced in ourown approach19#20 for modelling the power consumptionof complex processors. It is related to the fact that in mod-ern high performance superscalar processors, a dominantpart of the power is consumed by circuits used to exploitInstruction Level Parallelism.Vahdat et al.21 conducted a general study on aspects of

Operating System design and implementation to improveenergy efficiency. They investigated low power modesof embedded devices and proposed energy efficient tech-niques to use operating system functionalities.Acquaviva et al.1 proposes a methodology to analyse the

OS energy overhead. They measured the energy consump-tion of the eCos Real Time Operating System running ona prototype wearable computer, HP’s SmartBadgeIII. Theyanalysed the energy impact of the RTOS both at the kerneland the I/O driver level, and the influence of different fac-tors like I/O data burstiness and thread switch frequency.They particularly focused on the relationship between theenergy consumption and processor frequency. The authorsactually analyzed, but did not model, the energy consump-tion for the internal services and I/O drivers of the operat-ing system.

Dick et al.3 analyzed the energy consumption of the"C/OS RTOS when running several embedded applica-tions. They targeted a Fujitsi SPARClite processor basedembedded system. This work presents only an analysis ofRTOS policies on embedded system power consumption.The authors did not develop an energy consumption model.In Ref. [22], a methodology is proposed to characterize

embedded OS energy systematically. The energy consump-tion of OS services and primitives is modelled. A firstanalysis provides energy characteristics, which is a set ofessential components of the operating system used to char-acterize its energy consumption. Then, macro-modellinggives quantitative macro-models for the energy character-istics. The OS considered are "COS and Linux. Two low-level energy simulation tools (Sparcsim, EMSIM) wereused for the characterization instead of direct current mea-surement. This approach is thus limited by the accuracy ofthose energy simulators. Only internal OS mechanisms areconsidered, the energy consumption of external I/O driverswas not investigated.To allow for a fast and fruitful exploration of the design

space at high-levels in model driven approaches, powerconsumption estimations have to be completed in a reason-able delay. We have introduced the Functional Level PowerAnalysis (FLPA) methodology which we have applied tothe building of high-level power models for different hard-ware components, from simple RISC processors to com-plex superscalar VLIW DSP,18#19 and for different FPGAcircuits.20 Our methodology allows for a fast and preciseestimation of the power consumption of complex systems:it does not rely on a simulation, involving more or lesslow-level models, but on a static analysis of the specifi-cation, and possibly a profiling of the application. In fact,simulation may be impossible if the actual code of theapplication is not known in the early stages of the design.Our methodology allows to estimate the power consump-tion of heterogeneous architectures, since it may be appliedto the building of power-models for every component in anembedded system. Today we extend this approach by con-sidering heterogeneous architectures and the overhead dueto the operating system services and the use of peripheralsin addition to the own consumption of applications; theaim is to offer a reasonable trade-off between estimationspeed and accuracy.

3. MULTI-LAYER POWER AND ENERGYESTIMATION METHODOLOGY

Our approach consists in separately estimating the differ-ent sources of power consumption. However, the differentcomponents of embedded systems usually share commonpower supplies that prevent complete differentiation. Forinstance, in the Xilinx Virtex II board (XUP), the Com-pact Flash memory, the SDRAM and the FPGA I/O arepowered by the same 2.5 V power supply. Thus, we have

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Energy and Power Consumption Estimation for Embedded Applications and Operating Systems Dhouib et al.

(a)

(b)

Fig. 1. Multi-layer energy estimation.

adopted an incremental approach where we consider thatenergy can be summed over the hyper period of the real-time system, contrary to power, which is usually localizedand non-summable over different physical components.Figure 1 presents how power and energy consumption

are estimated in the case of the 2.5 V power supply of theXUP board.Figure 1(a) represents real power and energy consump-

tion while Figure 1(b) illustrates our approach and howwe distinguish and estimate the different sources of energyconsumption. Of course, the objective is to obtain an esti-mated area as close as possible to the real area.We first consider what we call Pground, the power

consumption of all the components when the system, with-out OS, is not executing any application. This power con-sumption can be quite important especially in the case ofembedded systems implemented on FPGA. Then we addthe energy contribution of each task by considering theoverhead related to peripherals and OS services.Figure 2 shows how the energy consumption of one

task is estimated. It is the sum of multiple contributionsrepresented by different areas, called layers. One layer Licorresponds to the consumption of one part of the systemfor task i. The energy consumption of the whole system isthe addition of the energy consumption of every task. Theaverage power is computed by considering the estimatedenergy and the application specific period.Our approach is based on high-level power modelling

detailed in the next section, it basically consists in applyingestimation, for every task in the system, with the followingorder:(L1) Eground, it corresponds to the task’s basicenergy consumption and depends on the basic power

Fig. 2. Multi-layer energy estimation of individual task.

consumption Pground and the execution time of the task.

Eground = Pground"T $%& (1)

Pground is based on a simple model built from physicalmeasurements of the targeted platform power consump-tion in the corresponding “idle” configuration. The task’sexecution time information is estimated by direct mea-surements or by timing estimation tools.(L2) 'E% , task intrinsic contributions. It corresponds tothe energy consumption overhead of the task, consideredstandalone.

'E% = 'P% !T $%& (2)

The estimation of 'P% relies on high-level power modelsof the targeted processor, and includes Cache and RAMaccesses.(L3) 'Etimer_interrupt, this is the basic OS energy consump-tion incurred by timer ticks tied to the scheduler.

'Etimer_interrupt = 'Ptimer_interrupt "T $%& (3)

'Ptimer_interrupt is the same for all the tasks and for achosen system configuration (processor, bus and ticktimer frequencies). The timer interrupt energy overhead('Etimer_interrupt& is variable since it depends on the execu-tion time T of the task (%&.(L4) 'Escheduler, scheduler overhead. It includes contextswitches and scheduling operations, which are estimatedindividually for each task.

'Escheduler = 'Pscheduler "'Tscheduler (4)

(L5) 'EIPC, energy due to communication and synchro-nization services.

'EIPC = 'PIPC !'TIPC (5)

(L6) 'Edevice_access, energy overhead related to periph-eral device accesses (Flash, Ethernet or other specificcontrollers).

'Edevice = 'Pdevice !'Tdevice (6)

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Dhouib et al. Energy and Power Consumption Estimation for Embedded Applications and Operating Systems

4. POWER MODELS

As previously stated, our power models are based onthe Functional Level Power Analysis approach. FLPAimplies the decomposition of a complex system into func-tional blocks that are independent with respect to powerconsumption.23 Parameters are identified that characterizethe way the functional blocks will be excited by the inputspecification. A set of measurements is performed, wherethe system consumption is measured for different valuesof the input parameters. Consumption charts are plottedand mathematical equations are computed by regression.This method is interesting because it links low-level mea-sures and observations of the physical implementation,with high-level parameters from earlier steps in the designflow.The model output is compared with measured values

over a large set of realistic applications. This allows fordefining the maximal and average errors introduced by themodel. In the following section, we first present powermodels of standalone tasks running on embedded proces-sors. We then introduce operating system services mod-els such as timer interrupt, IPC, device accesses, whichare linked to embedded devices such as the memory anddevice controllers.

4.1. Power Models of Standalone Tasks

Standalone tasks consume energy when running on pro-cessors and when accessing the memory in case of cachemisses. Power models of embedded processors and mem-ories have been presented in previous works.33#34 Differentpower models have been developed so far, for differentarchitectures, from the simple RISC (ARM7, ARM9) tomuch more complex architectures (the super scalar VLIWDSP TI-C62, C64, and C67), and also for low-power pro-cessors (the TI-C55 and the Xscale). Important phenomenaare taken into account, like cache misses, pipeline stalls,and internal/external memory accesses. The average error,observed between estimations and physical consumptionmeasurements, for a set of various algorithms (FIR filter,LMS filter, Discrete Wavelet Transform (DWT) with dif-ferent image sizes, Fast Fourier Transform (FFT) 64 to1024 points, Enhanced Full Rate (EFR) Vocoder for GSM,MPEG1 decoder, MJPEG chain ! ! !) is lower than 5% at theassembly level, and lower than 10% from the C-code. Inthe case of the PowerPC 405,24 the model comes with anaccuracy which is better than 5% (the average maximumerror found between the physical measurements and theresults of a law). The average error is 2%. Input parametersare: the processor frequency and the frequency of the busit is connected to, the configuration of the memory hierar-chy associated to the processor’s core (i.e., which cachesare used (data and/or instruction) and where the primarymemory is (internal/external to the FPGA)), and the cachemiss rate of the task.

4.2. Power Models of Embedded OS Services

We have developed power and energy models of timerinterrupt, IPC, Ethernet and Compact Flash, for theLinux 2.6 operating system ported to the Xilinx Virtex IIpro development board (Section 6.1). Current variationson the 2.5 V power supply connected to the FPGA I/O,SDRAM and Flash disk; and on to the 3.3 V power sup-ply connected to the Ethernet physical controller, are mea-sured. The Agilent DC Power Analyser25 is used to sourceand measure DC voltage and current into the XUP board.The Power Analyzer is a mainframe that has four slots toaccept one to four DC Power Modules. Each DC PowerModule has a fully integrated voltmeter and ammeter tomeasure the actual voltage and current being sourced outof the DC output into the XUP board. The digitizer ineach module runs at 50 kHz and captures 4096 samplesper trace; the upper limit on samples per trace depends onthe memory configuration of the power analyzer.

4.2.1. Power Model of OS Timer Interrupts

Every timer tick, the scheduler_tick() function is called toevaluate the runnable processes. To estimate the energyoverhead incurred by timer interrupts, we have executedseveral computing intensive programs with and withoutOS. We have observed the same power overhead for allprograms. We show the results for two programs, thefirst one is a discrete cosine transform (DCT) applied to8!8 pixels blocks stored in RAM. The second is a quan-tizer that rounds off the DCT coefficients according to aquantization matrix. Each function is repeatedly executedon the same frame, so that the cache miss effect is attenu-ated. We have executed the programs with different proces-sor and OS tick timer frequencies. With Linux 2.6, we cantune the tick timer frequency to 100, 250, 300 or 1000 Hz.We measured the power consumption of each program run-ning with and without OS, and for each system configura-tion. Energy was computed using timing information takenby direct measurements.Figure 3 shows the energy overhead of the timer inter-

rupt. Energy overhead is computed as follows:

'Etimer_interrupt = E$%withOS&#E$%w/oOS& (7)

Where %withOS corresponds to the program execution withOS and %w/oOS corresponds to the program execution with-out OS.The power consumption overhead is modelled as

follows:

'Ptimer_interrupt =E$%withOS&#E$%w/oOS&

T $%withOS&#T $%w/oOS&(8)

Where T is the measured execution time of the corre-sponding program. We observed that power and energyoverhead variations are the same for every program, and

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Energy and Power Consumption Estimation for Embedded Applications and Operating Systems Dhouib et al.

Fig. 3. Timer energy overhead according to CPU and OS timer frequencies.

depend on the tick timer and CPU frequencies. The poweroverhead model is written as follows:

!

""#

'P1

!!

'Pn

$

%%&=

!

""#

(1

!!(n

)1

!!)n

$

%%& !

'X1

((9)

Where Pi corresponds to power consumption related to theCPU frequency i value; X is the timer tick frequency (Hz);(i is a coefficient associated to the tick timer frequency.

4.2.2. Power Model of IPC

Inter-process communications allow threads in one processto share information with threads in other processes, andeven processes that exist on different hardware platforms.In IPC, the RTOS explicitly copies information from asending process’s address space into a distinct receivingprocess’s address space. Examples of IPC mechanisms arepipes and message passing through mailboxes or sockets(remote interprocess communication).To model IPC power consumption, we have executed

programs that repeatedly use an IPC mechanism, with dif-ferent values for parameters such as the amount of datasent and received, the OS tick timer frequency and the pro-cessor frequency. For example, for measuring the energycost of message queue read or receive, we have repeatedlyexecuted programs containing one software process andtwo threads. The first thread basically sends messages ofvariable length, using the system function mq_send(), to amessage queue. The second thread retrieves the messagesusing the system function mq_receive(). Communicationsare performed within the same process to avoid processcontext switching. We have also executed test programswith a high real time priority to avoid preemptive contextswitch. Our measurements show that only the processorfrequency and the message size influence the IPC con-sumption. Thus, the power model of IPC mechanisms is:

PIPC = aFcpu+b (10)

The detailed power model of message queues, sharedmemory and pipes is detailed in Table I.The energy model, given the processor frequency, is a

function of the message size:

EIPCi = ciXpi +di (11)

Table I. Power model of IPC.

Hw component Power model Avg. error (%)

SDRAM memory Pmqueue (mW&= 1!18Fcpu +2341!9 0.5(2.5 V)

Ppipe (mW&= 1!21Fcpu +2337 0.6Pshared_memory (mW&= 1!14Fcpu +2360 0.6

Where EIPCi is the energy consumption per byte trans-mitted for frequency i, ci, pi and di are coefficients ofthe model. The energy model of the Mqueue mechanismis depicted in Table II. We present energy laws, as wellas the average model error rates for the Mq_send andMq_receive routines. The error rate is computed followingthe equation:

n)

i=1

1n

**Ei#Ei

**

Ei

(12)

Where Ei is the estimated energy and Ei is the measuredvalue.In the case of remote communications, we have pre-

sented the Ethernet model in Ref. [26]. The model has thesame parameters as the local communication model, withan additional parameter, which is the protocol type (TCPor UDP). Our models come with an accuracy that is betterthan 9% (the average maximum error found between thephysical measurements and the estimations). The averageerror is 8%.

4.2.3. Power Model of Compact Flash Accesses

We selected a standard storage device, the compactflash, as a representative example implemented in most

Table II. Mqueue energy model.

CPU E$"J/Byte&= Avg. errorfrequency b"Messagepsize +d (%)

SDRAM memory (2.5 V)Mq_send

100 Mhz 350"X#0!99+0!02 4.8200 Mhz 393"X#1+0!03 2.3300 Mhz 511"X#0!99+0!04 2.8

Mq_receive100 Mhz 363"X#1+0!07 2.2200 Mhz 405"X#0!99+0!09 3300 Mhz 556!47"X#0!99+0!16 1.6

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Dhouib et al. Energy and Power Consumption Estimation for Embedded Applications and Operating Systems

embedded systems. As a first step, we identified the keyparameters that can influence the power and energy con-sumption of compact flash accesses. Then we conductedphysical power measures on the XUP board. Measure-ments were realized with different testbenches containingRTOS routines accessing the compact flash.We have modelled two different Linux system calls. The

first model concerns buffered I/O which are the defaultLinux I/O operations. When the I/O is buffered the com-pact flash does direct memory access from/to the kernelcache, and not from/to the user space source/destinationbuffer allocated by the user application. The second modelconcerns self caching I/O. In this case, the application willkeep its own I/O cache in user space (often in shared mem-ory), so it does not need any additional lower level systemcache. This is done using the option O-Direct when read-ing or writing data.Power and energy models have the same form as that

of Eqs. (10), (11). We have noticed that buffered I/O con-sumes more power, but less energy than self caching I/O.This is due to the fact that when using buffered I/O, moreresources are solicited (RAM, CPU caches) that increasethe power consumption. On the other hand, buffered I/Ois more efficient because it allows programs to reduce dra-matically the number of I/O operations during the runtimeof the system. Consequently, it consumes less energy.

5. CONSUMPTION ANALYSIS TOOLBOX

Our energy estimation methodology and power modelshave been integrated in a Computer Aided Design (CAD)Consumption Analysis Toolbox (CAT). The toolbox com-bines a set of power estimation models with a systemarchitecture model to provide system-level power con-sumption analysis. CAT has been used on our case study tocompute the estimated power consumption. CAT runs onthe Windows and Linux platforms and is deployed on theEclipse Integrated Development Environment (IDE). Thecentral part of CAT is a Domain Specific Language (DSL)that was defined to describe system architectures from apower analysis perspective. It also serves as a communica-tion layer between the CAT application tiers to exchangethe modelled system data. CAT can also be used in con-junction with the Open Source AADL Tool Environment(OSATE),27 and the Toolkit in Open source for CriticalAeronautic Systems Design (TOPCASED).35 In this ver-sion of the toolbox, the AADL instance model editor canbe used instead of the CAT model object editor. CAT maybe downloaded with related documentation on Ref. [45].Figure 4 presents the component based AADL design

flow. The AADL component assembly model contains allthe components and connection instances of the appli-cation, and references the implementation models of thecomponents instances from the AADL models library. TheAADL target platform model describes the hardware of

AADL componentassembly model

AADL targetplatform models:- hw components

- services- connectors

AADL deploymentplan model

AADL PSM modelcomposition

AADL models library:- components

- interfaces

SystemCmodel

SystemCC++ code

Code generation

Model transformation

FPGA DSP GPP

HLS/LS/P&R; Compil./Link.

Fig. 4. AADL component based design.

the physical target platform. This platform is composed ofat least one processor, one memory, and one bus entity tohome processes and threads execution. The AADL deploy-ment plan model describes the AADL-PSM (Platform Spe-cific Model) composition process. It defines all the bindingproperties that are necessary to deploy the processes andservices models of the component-based application on thetarget platform. All those models are combined to obtainthe AADL-PSM model of the complete component-basedsystem. The final implementation of the system is obtainedafterward through model transformations and code gener-ation. Deployment of the application on the hardware plat-form consists in binding processes to memories, threadsto processors, and connections to busses. The Operatingsystem process and threads are also bound to the mem-ory and processor. The resulting Platform Specific Modelis then analysed and parameters influencing power andenergy consumption are automatically extracted by CAT.The power and energy consumption is computed after-ward. More details on the AADL design flow and poweranalysis may be found in Refs. [24] and [28].In the next section, we show how the CAT tool performs

power and energy estimation on different multithreadedversions of an MJPEG system.

6. CASE STUDY

This section illustrates the application of our methodol-ogy on a Motion JPEG (MJPEG) encoder. Starting froman AADL high level description of the MJPEG system,the CAT tool extracts OS-related parameters and estimatesenergy consumption for the whole system. Three differentMJPEG scenarios, with different communication mecha-nisms, are considered. Estimations are finally compared tothe measured consumption to validate our methodology.

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Energy and Power Consumption Estimation for Embedded Applications and Operating Systems Dhouib et al.

Table III. MJPEG scenarios.

Scenario Tasks Communication mechanism

1 1 process, 12 threads, Threads synchronizationPeriodic image with signalsacquisition

2 2 processes, 12 threads, Process Communication throughPeriodic image mqueue, Threads synchronizationacquisition with signals

3 2 processes, 12 threads, Process Communication throughPeriodic image sockets (Ethernet), Threadsacquisition synchronization with signals

6.1. Experimental Framework

The platform is a XUP Virtex-II pro development board,featuring a 256 MB SDRAM memory, a 512 MB CompactFlash, and an Ethernet interface. The Virtex-II pro includestwo PowerPC 405 hard cores, with memory managementunits, data and instruction caches. Many I/O controllersare also integrated in the FPGA, such as audio, Ethernet,UART, compact flash and SDRAM. This device has beenselected as a usual low-cost solution for a configurableSoC including hard-coded IPs. The operating system isLinux 2.6 which introduces a new low-latency preemptivescheduler whose execution time is not affected by the num-ber of tasks being scheduled. Along with POSIX threads,it provides POSIX signals, POSIX message queues andPOSIX high-resolution timers as part of the mainstreamkernel.

6.2. MJPEG Application Scenarios

Motion JPEG is an informal name for multimedia formatswhere each video frame or interlaced field of a digitalvideo sequence is separately compressed as a JPEG image.It is often used in mobile appliances such as digital cam-eras. We have specified three different AADL models ofthe MJPEG application. Each model corresponds to a sce-nario where tasks are organized and communicate differ-ently. Table III summarizes the three MJPEG scenarios.

Fig. 5. AADL model of MJPEG scenario 1.

Scenario 1 (Fig. 5) is constituted of one process contain-ing threads synchronized with signals. Scenario 2 containstwo processes communicating through mqueues. Each pro-cess includes a set of threads synchronized with signals(modelled as connections between thread event ports inFig. 6).Data transfers between threads are modelled as AADL

data port connections. Image_Acquisition periodically getsframes from the Compact Flash and transfers them toRGB2YUV. Thread RGB2YUV divides a frame into a setof 8! 8 pixels blocks, and converts RGB blocks to YUVblocks. The remaining compression operations are sep-arately fulfilled on Y, U and V frames. DCT performstransformations on Y frames, and then sends the result-ing data to the MJPEG_part_2 process through a mqueue.Scenario 2 uses 3 mqueues, each one corresponding to Y,U or V frames.To specify IPC services using AADL, we have extended

the language with new packages.29 Mqueues are imple-mented in the RTOS kernel memory space; services ofmqueues are implemented as server subprograms of themqueue thread. Data received from a mqueue is furtherquantized and then compressed with a loss-less algo-rithm, a variant of Huffman encoding. Finally threadRebuild_Image concatenates the obtained (Y, U, V) frameswith the JPEG header into a compressed image.Scenario 3 is organised as scenario 2, but uses a

remote communication mechanism (socket). The appli-cation is distributed on two XUP platforms connectedthrough Ethernet as shown in Figure 7.

6.3. Energy Estimation on the MJPEG System

We applied our estimation methodology, following the dif-ferent steps presented in Section 3, for scenarios 2 and 3.We start with the AADL specification that provides themapping of each thread on the target architecture. TheCAT tool first computes the power consumption of stan-dalone tasks using the PowerPC 405 model presented inRef. [27]. That corresponds to consumption layers L1 and

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Fig. 6. AADL model of MJPEG scenario 2.

L2 in our approach: Pground is included in the estimatedtask consumption given by the model. The estimation isbased on the SoftExplorer tool,30 integrated in CAT, whichcan analyse C programs specified for each thread accord-ing to the processor model. Parameters of the model areextracted from the AADL specification of the system toanalyze. The tool extracts input parameters for the proces-sor’s power model which are data and instruction cachemiss rates and processor and bus frequencies. Cache missrates are obtained using the cache profiler tool Cachegrind,from the Valgrind tool suite.31 From the timing informa-tion of each task, here obtained by direct measurements,the tool estimates the thread energy consumption. Tim-ing information can also be obtained from timing analy-sis tools currently being developed in the SPICES project,such as PathCrawler32 which is specialized to be used forworst-case/best-case execution time prediction.Secondly, the CAT tool adds the energy overhead due

to the timer interrupts and the scheduler. It correspondsto consumption layers L3 and L4 respectively. These esti-mations are computed with input parameters of the RTOSmodel. Relevant information for these estimations, whichare extracted from the AADL specification, are the pro-cessor and the tick timer frequencies.In a third step, the CAT tool adds the energy overhead

due to IPC corresponding to the consumption layer L5.In scenario 2 (resp. 3), the communication mechanism ismessage queues (resp. Ethernet). Following the mqueue(resp. Ethernet) model, the tool extracts, from the AADL

specification, parameters such as message (resp. IP packet)size, amount of data sent or received, processor frequencyand protocol type (in case of Ethernet); and it computesthe energy overhead.Finally, CAT adds the energy overhead of device

accesses related to the consumption layer L6. ThreadsImage_Acquisition and Rebuild_Image have access to theCompact Flash memory (Input parameters of the CompactFlash model are the processor frequency and the amountof data read or written). Table IV shows the details of theestimation for each task in the system. * is the cache missrate of task %i.

The estimation approach we propose has some fittingerror with respect to the measured energy values. We usethe following average error metric:

$+Ei#Ei$Ei

(13)

Where +Ei is the estimated energy and Ei is the mea-sured value. Table V shows the error rate of the estimationapproach for the MJPEG multithreaded application scenar-ios. While more power consumption sources are consid-ered when the complexity increases, the cumulative errorincreases as well. The higher error for the third scenario(part 1 and 2 respectively corresponds to the first and sec-ond platform) comes from the Ethernet communicationsconsumption model, for which the maximum error is 9%.

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Energy and Power Consumption Estimation for Embedded Applications and Operating Systems Dhouib et al.

Fig. 7. AADL model of MJPEG scenario 3.

Table IV. Energy estimation of multi-threaded MJPEG tasks (2.5 V power supply).

P $%i&

$mW&E$%i&

$mJ&

'Etimer

$mJ&'Emqueue

$mJ&'EEthernet

$mJ&'EFlash

$mJ&%i *$%i& (%) Ti $ms&

Acquisition 3.2 2200 10.91 24 0.43 0 0 12.84RGB2YUV 6.1 2201 15.06 33.16 0.6 0 0 0DCT_Y 1.3 2199.42 29.83 65.61 1.19 5.39 29.82 0Quantizer_Y 1.9 2199.62 27.39 60.26 1.09 8.16 29.8 0Huffman_Y 2.5 2199.82 16.72 36.69 0.66 0 0 0Rebuild_Image 3.7 2200.21 5.8 12.77 0.23 0 0 4.23

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Dhouib et al. Energy and Power Consumption Estimation for Embedded Applications and Operating Systems

Table V. Energy estimation on the MJPEG scenarios.

Scenario Measure (mJ) Estimation (mJ) Error (%)

1 578.56 585.2 1.142 600.95 625.85 4.143 MJPEG part 1 651.16 719.88 10.553 MJPEG part 2 653.4 728.47 11.48

7. CONCLUSION

We have presented a methodology that permits a systemlevel estimation of the power and energy consumption ofcomplete embedded applications. Our methodology comeswith a set of power models for the hardware platform onwhich the application is deployed, and the operating sys-tem which operates the platform. The operating system’sconsumption overhead is view as the sum of multiple con-tributions corresponding to every activated service, such asscheduler/timer interrupts, inter-process communications,and peripheral devices access. The analysis is incremen-tal: for each task the power and energy consumption isestimated before the operating system’s overhead.Our methodology has been applied to the model-

ing of the Xillinx XUP Virtex-II Pro platform andLinux 2.6 OS. Estimations were performed on three multi-threaded versions of the MJPEG application, involving dif-ferent communication mechanisms and the correspondingOS services, and one or two XUP boards. Estimationswere compared to physical consumption measurements:the error between our estimations and the measured con-sumption goes from 1% to 11%.Our methodology, and the associated power models, has

been integrated in the tool CAT (Consumption AnalysisToolbox), deployed in the Eclipse IDE. CAT comes with aDomain Specific Language (DSL) to describe the systemarchitectures from a power analysis perspective. CAT wasalso integrated in OSATE, the Open Source AADL ToolEnvironment, and TOPCASED.Future works will include the development of power

models for operating system’s services not consideredyet, especially with a strong impact on the memorystress (memory virtualization, paging and swapping mech-anisms). Dedicated power management mechanisms havealso to be considered. Future works include the use of ourmethodology on several different multi-threaded real-timeapplications. An automatic measurement platform will bebuild, to automatize the measure of power and energy con-sumption on different embedded systems, that will permitthe validation of our approach on a larger set of variousapplications. Those works will be conducted in the FrenchANR project Open-PEOPLE.46 In the frame of this project,we are planning the modelling of other hardware targetplatforms, and especially the inclusion of FPGA powermodels, which we have already developed for standalonecomponents, in our estimation framework for a completeheterogeneous system.

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Saadia DhouibSaadia Dhouib received her Engineering Diploma in Computer Science from the National School of Computer Sciences (Tunis-Tunisia)in 2004. She received M.S. degree from the National School of Engineers (Sfax-Tunisia) in 2006. She is currently working toward thePh.D. degree at the Lab-STICC (Laboratoire des Sciences et Techniques de l’Information, de la Communication et de la Connaissance),University of South Brittany (Lorient-France) and at the CES (Computer and Embedded Systems) laboratory, National School ofengineers (Sfax-Tunisia). Her research interests include power/energy modelling and estimation of OS-based embedded systems.

Eric SennEric Senn received the B.S. degree in Electrical Engineering from the University of Paris VI in 1991. He was student of the ‘EcoleNormale Supérieure de Cachan’ from 1991 to 1992 and he succeed the ‘Agrégation’ of Electrical Engineering in 1992. In 1993,he received the M.S. Degree in Electronics and Computer Sciences from the University of Paris XI. He was Professor of the FrenchMinistry of Defense in the GIP (Geography Image and Perception) Laboratory for the DGA (Déléguation Générale de l’Armement)from 1995 to 1999. He received his Ph.D. degree in Electronics from the University of Paris XI in 1998. He is currently an AssociateProfessor in the University of South Brittany (UBS-France) and member of the Lab-STICC (formerly known as LESTER) since 1999.He received the HDR (Habilitation à Diriger des Recherches) Degree in 2008 from the UBS. His current works include research onhigh-level methods and tools for embedded systems design (encompassing hardware and software architectures, as well as real timeoperating systems), power and energy modeling, analysis and optimization, and Model Driven Engineering (Meta-models definition,and model transformations).

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Jean-Philippe DiguetJean-Philippe Diguet received the Computer-Science Engineer degree in 1992 from ESEO (France), the M.S. degree and the Ph.D.degree from Rennes University (France) in 1993 and 1996 respectively. In 1997, he has been a visitor researcher at IMEC (Leuven,Belgium). He has been an associated Professor at UBS University (Lorient, France) from 1998 until 2002. In 2003, he initiated atechnology transfer and co-funded the dixip company in the domain of wireless embedded systems. Since 2004 he is a CNRS researcherat Lab-STICC (Lorient, Brest, France). His current work focuses on various topics in the domain of embedded system design: high-level synthesis, design space exploration, power/energy modeling, NoC architectures and CAD tools, reconfigurable and self-adaptiveHW/SW architectures and secured architectures.

Dominique BlouinDominique Blouin received a B.Sc. in Physics from the University of Sherbrooke (Sherbrooke, CANADA) in 1989, and a M.Sc. inphysics from the University of British Columbia (Vancouver, CANADA) in 1994. He was a software architect at Cassiopae until 2008after which he joined the Lab-STICC as a research engineer. His research interests are Model Driven Engineering based ComputerAided Design tools for embedded systems in the field of power and energy consumption.

Johann LaurentJohann Laurent received the M.Sc. degree in Electrical Engineering from Ecole Supérieure d’Electricité of Rennes in 1999 and thePh.D. degree in Electrical Engineering from the Université de Bretagne Sud of Lorient, in 2002. In 2005, he joined the Univer-sité de Bretagne Sud and CNRS laboratory Lab-STICC as an associate professor. His research interests include software/hardwareconsumption models and estimation for complex heterogeneous embedded systems.

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