Upload File

enabling embedded intelligence - risc-v...2019/03/15  · ar/vr/sensor fusion low latency peripheral...

  • Home
  • Documents
  • Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application
13
COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED. Enabling Embedded Intelligence Jack Kang, RISC-V Workshop Taiwan 2019

Upload: others

Post on 25-May-2020

8 views

Category:

Documents


0 download

Report

TRANSCRIPT

Page 1: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Enabling Embedded Intelligence

Jack Kang, RISC-V Workshop Taiwan 2019

Page 2: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

SiFive Core IP Embedding Intelligence Everywhere

SSD, SAN, NAS

Base Stations, Small cells, APs

Switches, Smart NICs, Offload cards

Sensor Hubs, Gateways

Autonomous machines

IoT devices

Storage/Networking/5G ML/Edge

AR/VR/Gaming devices

Smart Home

Imaging/Wearables

Consumer

Page 3: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

Intelligent Edge

Intelligent

Cloud

Embedding Intelligence from the Edge to the Cloud

32-bit Embedded Processors

64-bit Embedded Processors

64-bit Application Processors

Page 4: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

SiFive Core IP 2 series:

SiFive’s smallest and most efficient RISC-V processor IP

Configurable Higher

Performance

Low latency

interrupts

Efficient RISC-V MCU Configurable Core and Memory System

Ultra low-latency interrupts

32-bit

Embedded

Processors

Page 5: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

SiFive Core IP 3 and 5 series:

The world's most deployed RISC-V processor IP

Efficient Configurable Mature

32-bit

Embedded

Processors

64-bit

Embedded

Processors

64-bit

Application

Processors

Efficient Performance Coherent, Heterogenous, Multicore

Hard Real-time capabilities

Page 6: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

SiFive Core IP 7 series:

The highest performance commercial RISC-V processor IP

32-bit

Embedded

Processors

64-bit

Embedded

Processors

64-bit

Application

Processors

Common Feature sets Hard Real-time capabilities Unprecedented scalability

~40% increase

in DMIPS/MHz*

~60% increase

in

CoreMarks/MH

z*

10% increase

in Fmax*

*Compared to SiFive 5

series

Page 7: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

Scalable throughput provided by 8+1 cores per cluster

Extensible design via custom instructions

Configurable memory architecture for application

specific tuning

Enhanced determinism for hard real-time constraints

In-cluster coherent heterogenous combination of real-time and application processors

A single pre-integrated and verified deliverable

Mixed-precision arithmetic for efficient compute of ML

workloads

64-bit addressability for real time latency sensitive applications

Cache lock capability for mission-critical computing

Functional safety provided by in-built fault tolerance

mechanisms

Tightly integrated memory for low latency access

SiFive 7 Series Embedded Intelligence Everywhere

Page 8: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

Storage

Coherent in-cluster combination of application processors and real-time

processors

Configurable memory maps and coherent accelerator ports for tightly coupling storage specific accelerators

Deterministic mode for FAST DATA applications with hard

real-time constraints

Tightly integrated memories and Cache lock capability for

critical real time workloads

Optional FPU for applications which don’t need floating point capability

Storage, ML, Cryptography specific custom instructions

64-bit real-time addressability for BIG DATA applications

Page 9: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

5G/Networking

Complex arithmetic capability for accelerating baseband functions

High bandwidth accelerator ports for enabling intelligent offload processing

In-cluster coherence of application and real-time processor enables 5G latency (<1ms) requirements

Hard real-time capabilities for scheduling baseband protocol layers

Configurable memory maps for optimizing QoS

High throughput processing for next gen 5G stacks

Tightly Integrated Memories and Cache lock capability for critical real

time workloads

Page 10: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

AR/VR/Sensor Fusion

Low Latency peripheral access and coherent accelerator port

Coherent in-cluster combination of application processors with real time

processors

Combine with SiFive 2, 3 or 5 series for designs with tight

power constraints

Workload specific customizations (AR/VR/MR/CV)

Simple caching hierarchy for ease of application optimization

Mixed precision arithmetic for accelerating machine

learning compute

Page 11: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

Rapid adoption of SiFive Core IP from the Edge to the Core

Recently announced products

Wearable

AI Enterprise Edge

CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.

Rapid adoption of SiFive Core IP from the Edge to the Core

Recently announced products

Wearable AI Enterprise Edge

Page 12: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

Embedding intelligence for

a world of a Trillion

Connected Devices

Efficient

Performance

Scalability

Compelling

Feature Set

SiFive Core IP: Embedding Intelligence Everywhere

Page 13: Enabling Embedded Intelligence - RISC-V...2019/03/15  · AR/VR/Sensor Fusion Low Latency peripheral access and coherent accelerator port Coherent in-cluster combination of application

Silicon verified.

Market proven.

The most advanced configurable

core IP and silicon solutions from

the inventors of RISC-V.

Microcontrollers Embedded Linux Multicore

Networking Storage Computing AI

Industrial IoT Consumer Automotive

www.sifive.com


CISC, RISC and Post RISC

The future of operating systems on RISC-VThe future of operating systems on RISC-V ... Introduction to RISC-V RISC-V status Selected RISC-V topics RISC-V and open hardware: the future

Uniprocessors - Computer Science, FSUengelen/courses/HPC/Architect… ·  · 2017-01-19n Uniprocessors ¨ Processor ... CISC, RISC, VLIW, and Vector ... Instruction Latency Case

Tue0830 Workshop Intro & RISC-V Foundation Overview … · § RISC-V Foundation Overview ... and open RISC-V instruction set architecture together ... Tue0830 Workshop Intro & RISC-V

risc suveran

MPC7410 RISC Microprocessor Hardware Specifications Sheets/NXP PDFs/MPC7410.pdf · System Design Information ... † The MPC7410 floating-point unit has been improved to make latency

RISC vs CISC - The Post-RISC Era - Jon "Hannibal" Stokes

RISC - WBUTHELP.COM

RISC Machines

RISC - CISC

RISC Pipeline

Introduction to RISC Assembly Language - Lagout to RISC... · Introduction to RISC Assembly Language Programming ... clean RISC (Reduced Instruction Set Computer) machine, which makes

Risc Vertical

CISC, RISC, and Post-RISC Computers

RISC Architecture

RISC-V: Berkeley Hardware for Your Berkeley Software ... · RISC-V ISA • Fifth RISC ISA from Berkeley, so RISC-V • Modular ISA: Simple base instruction set plus extensions •

Coherent Passive Optical Networks for 5G Transport · Building low-latency and high-capacity optical networks is very important issue, especially when new high-speed cellular technologies

Comparison of RISC Archtectures - UNLPelectro.fisica.unlp.edu.ar/arq/downloads/Papers/RISC/IEEE_Micro_1989... · A Comparison of RISC Archtectures umerous new RISC architectures have

TSK3000A 32-bit RISC Processor - Altium tsk3000a 32 bit risc...TSK3000A 32-bit RISC Processor CR0121 (v1.3) May 09, 2005 3 RISC Processor Background RISC, or Reduced Instruction Set

Chun Chiu. Overview What is RISC? Characteristics of RISC What is CISC? Why using RISC? RISC Vs. CISC RISC Pipelines Advantage of RISC / disadvantage

CCIX: a new coherent multichip interconnect...High performance, low latency • CCIX defines 25GT/s (3x performance*) • Examining 56GT/s (7x performance*) and beyond • Enabling

Beyond Risc

The Silent Invasion. Acorn RISC Machine or Advanced RISC Machine?

RISC By Don Nichols. Contents Introduction History Problems with CISC RISC Philosophy Early RISC Modern RISC

Super Risc

Risc Final3

RISC AND CISC UNDERSTANDING THE RISC AND CISC ARCHITECTURES

EVALUATOR RISC

Risc Cisc

RISC - raperkins.netraperkins.net/ENVE_651/hold RISC/RISC4_Manual.pdf · RISC Manual Version 4.0 ii • RISC allows for pathway, compound and receptor additivity • The fate and

Beyond RISC–The Post-RISC Architecture

S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW … · S3C44B0X RISC MICROPROCESSOR PRODUCT OVERVIEW 1-1 1 ... • 16/32-Bit RISC architecture and powerful ... OVERVIEW RISC Machines,

GRVI Phalanx: A Massively Parallel RISC-V® FPGA ......•Massively parallel, specialized, connected, versatile •High throughput, low latency, energy efficient But two hard problems

N N RISC RISC N

Tom Paone RISC to RISC Transition Procedures ... - … transition procedures... · Tom Paone RISC to RISC Transition Procedures. 2 o Use the WRKHDWRSC *STG and WRKDEVD commands to