enabling an interconnected digital world cadence eda...
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Enabling An Interconnected Digital WorldCadence EDA and IP Update
Jonathan SmithDirector, Strategic AlliancesJune 1, 2017
2 © 2017 Cadence Design Systems, Inc. All rights reserved.
IoT Market Definition and Growth EstimatesLarge and widely varying
Known: “IoT” will include a large mixed-signal component, with complex packaging
3 © 2017 Cadence Design Systems, Inc. All rights reserved.
Cadence Implementation LeadershipTechnology innovation: fast, smart, and optimized
Quantus™
Tempus™
Voltus™
Genus™
Modus™
Innovus™
Massively parallel for speed and capacity
Best PPA and intelligent flows
Rapid convergence and ECO
Fully integrated mixed signal
Implementation FabricCommon Engines, UI, and Flows
Pegasus™
PLACE and ROUTEFRONT END ELECTRICAL SIGNOFF
LogicalConformal®
ElectricalTiming, Power
PPA EnginesOptimization
PhysicalQuantus and DRC
• Best-in-class core tools
• Common foundation
engines
• Differentiated productivity
DESIGN RULE CHECK
4 © 2017 Cadence Design Systems, Inc. All rights reserved.
CHARACTERIZATIONLiberate™
Variety
Cadence Custom IC and PCB Design LeadershipEnabling smart product design from start to finish
PACKAGEAllegro®
Virtuoso
CHIPVirtuoso®
Spectre®
ANALYSISSigrity™ Market leadership for
over 25 years
In excess of 70 different
ecosystem partners
Differentiated and
comprehensive
support for IoT,
automotive, and
aero/defense designs
System Design Enablement via an Extensive Ecosystem
BOARDAllegro®
PSpice®
OrCAD®
Mixed signal
Analog/RF
Photonics support
Rigid-flex board enablement
Advanced node (16nm to 5nm)
Advanced packaging
5 © 2017 Cadence Design Systems, Inc. All rights reserved.
Cadence Verification SuiteTechnology innovation leadership: fast, smart, and optimized
VIPVERIFICATION IP
Perspec™
SW-DRIVEN TEST
vManager™
METRICS
Indago™
DEBUGUniform multi-engine verificationVerification Fabric
Palladium® Z1EMULATION
Xcelium™
SIMULATION
JasperGold®
FORMAL and STATIC
Protium™ S1FPGA PROTOTYPE
Total throughput
Metric-driven signoff
Application optimized
Cloud-centric architecture
• Fast: Best-in-class engines
• Smart: Flow-driven engine
integrations
• Optimized:
Comprehensive solutions
6 © 2017 Cadence Design Systems, Inc. All rights reserved.
2015
Digital and Signoff Tools
22FDX enabled
2016
V0.5 22FDX tapeoutsupported
EAD in 22FDX at CDNLive
2017
Phase III of 22FDX reference flow
Digital reference flow for 28FDS presented at CDNLive
Voltus 28FDS certification presented at CDNLive
Successful Foundry Node Requires an EcosystemStrong collaboration history – tool enablement and design flows
7 © 2017 Cadence Design Systems, Inc. All rights reserved.
Samsung-Cadence Collaboration on 28FDSOI
Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology
Reference flow enables system and semiconductor companies to accelerate delivery of IoT and mixed-signal designs on Samsung’s process
SAN JOSE, Calif., May 24, 2017—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its custom/analog tools and full-
flow digital and signoff tools have achieved certification for the process design kit (PDK) and foundation library for the Samsung
Electronics’ 28nm fully depleted silicon-on-insulator (FDS), also known as FD-SOI , process technology. The Cadence® 28nm FDS
reference flow has been certified by Samsung using a quad-core design with the ARM® Cortex®-A53 processor covering forward body
bias (FBB) with a bias controller, a power-gating scheme, UPF2.1 compliance, multi-bit FF optimization, SCAN/PMBIST/ATPG and
SI/EM-aware design.
8 © 2017 Cadence Design Systems, Inc. All rights reserved.
SOI Advanced-Node EDA Enablement – 28FDS
Samsung 28FDS Cadence Digital Reference Flow presented at CDNLive Silicon Valley 2017: “Fast Ramp to Reap 28FDSOI Benefits ”
Design Capabilities 28FDS
Logic Simulation (Incisive)
Dig
ital
Imple
menta
tion a
nd S
ignoff
(RTL t
o G
DS
)
Synthesis (Genus)
Power Analysis (Joules)
Test (Modus)
Place and Route (Innovus)
Timing Analysis (Tempus)
Extraction (Quantus)
EM/IR Analysis (Voltus)
Physical Verification (PVS)
Litho Physical Analysis (DFM/LPA)
Litho Electrical Analysis (DFM/LEA)
Chemical Mechanical Polishing (DFM/CMP)
Custo
m a
nd A
nalo
g
Desig
n
Schematic Editing (Virtuoso VSE)
Analog Design Environment (Virtuoso ADE)
Layout System (Virtuoso VLS)
Circuit Simulation (Spectre APS/XLS)
Electrically Aware Design (EAD)
EM/IR Analysis (Voltus-Fi)
Certified
Enabled
9 © 2017 Cadence Design Systems, Inc. All rights reserved.
SOI Advanced-Node EDA Enablement – 22FDX
Design Capabilities 22FDX
Logic Simulation (Incisive)
Dig
ital
Imple
menta
tion a
nd S
ignoff
(RTL t
o G
DS
)
Synthesis (Genus)
Power Analysis (Joules)
Test (Modus)
Place and Route (Innovus)
Timing Analysis (Tempus)
Extraction (Quantus)
EM/IR Analysis (Voltus)
Physical Verification (PVS)
Litho Physical Analysis (DFM/LPA)
Litho Electrical Analysis (DFM/LEA)
Chemical Mechanical Polishing (DFM/CMP)
Custo
m a
nd A
nalo
g
Desig
n
Schematic Editing (Virtuoso VSE)
Analog Design Environment (Virtuoso ADE)
Layout System (Virtuoso VLS)
Circuit Simulation (Spectre APS/XLS)
Electrically Aware Design (EAD)
EM/IR Analysis (Voltus-Fi)
This slide contains forward-looking statements about Cadence business or products . Actual results may differ materially from the information presented here.
Certified
Enabled
12FDX: Cadence and GLOBALFOUNDRIES have
started collaborating to support 12FDX node
10 © 2017 Cadence Design Systems, Inc. All rights reserved.
Enabling FD-SOI Process
Genus™ Design
ExplorationReleased in December 2016
Innovus™ Body-Bias
Interpolation To be Released by end of May
2017
Tempus™ Body-Bias
Interpolation To be Released by end of May
2017
Voltus™ Body-Bias
Interpolation To be Released by November
2017
This slide contains forward-looking statements about Cadence business or products . Actual results may differ materially from the information presented here.
11 © 2017 Cadence Design Systems, Inc. All rights reserved.
RTL SDC DFT
Files
Technology
FilesStd Cell
Libraries
*IEEE 1801Power Intent
project_setup.tcl
post_syn and post_pnr
LEC/LP Check
Power Integrity
EMIR Signoff
Modus
ATPG
Logic Synthesis
DFT Insertion
Timing and SI
Signoff
Parasitic RC Extraction
Write Abstract LEF
Extract Timing Model
Block-Level Flow Top-Level Flow
Block Timing Model
Block LEF
Digital Implementation and
In-Design Signoff
*Assemble
Design
Be
st-in
-Cla
ss
PP
A O
ptim
iza
tion
Tempus™ Timing Signoff Solution
Quantus™ QRC Extraction Solution
*Conformal® Low Power CheckerConformal Equivalence Checker
Genus™ Synthesis Solution
Innovus™ Implementation SystemPhysical Verification System
Litho Physical Analyzer
Modus™ Test Solution
Voltus™ IC Power Integrity Solution
12 © 2017 Cadence Design Systems, Inc. All rights reserved.
Cadence Tensilica Processor IP For automotive applications
Front-collision warning
Automatic high beam
Traffic sign detection /
recognition
Lane-departure warning
Digital Radio receiver: HD Radio, DAB, DAB+, DRM, T-DMB
Multi-channel audio decode and advanced post-processing
Multi-microphone voice command, and noise reduction
Embedded signal processing
ADAS vision processing
Digital radio and voice command
Acoustic noise cancellation
Advanced Driver Assistance Systems
Built-in LTE Modem andWi-Fi Access Point
Peer-to-peer smart car networking for intelligent
vehicle highway control
GPS
Telematics connectivity / Radar
Emergency Services
Battery management
Regenerative power management
Engine control
Cabin environmental control
Tensilica® HiFi DSPs Tensilica Fusion DSPs
Tensilica Vision DSPs Tensilica ConnX DSPs
• Shipping in volume;
• >12 HiFi licensees in automotive
Multiple wins in next-
gen ADAS systems
Radar/Lidar
• Shipping in 1st V2V
802.11p from NXP;• Wins in future Radar
ADAS systems
Fusion DSPs introduced
2015, 2016, and 2017
ISO 26262 Ready / ISO 9001 CertifiedMultiple rounds of experience delivering DIAs to automotive licensees
13 © 2017 Cadence Design Systems, Inc. All rights reserved.
Cadence Custom and Digital tools Ready for FD-SOI
• Multi-year collaboration with foundry FD-SOI leaders
• PDK enablement, tool readiness, design flows in place
• Enables designers to take optimal advantage of FD-SOI features such as body-biasing
14 © 2017 Cadence Design Systems, Inc. All rights reserved.
Thank You
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of
Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
16 © 2017 Cadence Design Systems, Inc. All rights reserved.
Backup
17 © 2017 Cadence Design Systems, Inc. All rights reserved.
The CDNS-GF 22FDSOI Digital Reference Flow is a RTL2GDS2 solution including Synthesis (Genus), Place and Route (Innovus), Parasitic Extraction (Quantus), Static Timing Analysis (Tempus), Power Analysis (Voltus), Formal Verification (Conformal), Test Solution (Modus), Physical Verification (PVS) and DFM (MVS) tools. The flow covers block-level flow and hierarchical multi-bias domain flow.
The hierarchical reference flow (P5) uses a bias generator and a processor monitor to generate bias voltage for three bias domains. The CPU, timer block and top-level logic are physically placed in three different domains separated by boundary cells. Global physical cell placement and bias power network routing are performed during floor planning.
The block-level reference flow (P2/P4) uses OR1200 RTL with Invecas Standard Cells for official digital reference flow release, with industry-standard CPU RTL is also used for PPA benchmark in P2. The reference flows include both all-in-one make file for RTL-to-GDSII and standalone make file for each step.
GF 22FDSOI Digital Reference Flow Overview
18 © 2017 Cadence Design Systems, Inc. All rights reserved.
P2 first released on Aug 14, 2015
− Basic digital reference flow including RC, Innovus, Quantus, Tempus
− Block level with only FBB cells, external back bias voltage
− Bias routing to WellTAP cell from external power pins, one BIAS voltage pair (NW, PW), with
different BIAS voltages
P4 first released on Nov 6, 2015
− 1801 low-power flow with 3 power domains
− Genus, Conformal, Incisive, and ET are also added to P2
− Implementation of Mixed Vt due to various bias conditions
− Bias routing to WellTAP cell from external power pins, multiple BIAS voltage pairs, with pre-defined voltage level per domain
P5 first released on April 30, 2016
− Bottom-up hierarchical low power flow with body bias IP to generate body bias voltage
− Bias routing to WellTAP cells, multiple BIAS voltage pairs, with different BIAS voltages for
different domains
Key Features at Phased Releases
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of
Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.