en39sl800 8 megabit (512k x 16-bit) flash memory with ...€¦ · this data sheet may be revised by...

This Data Sheet may be revised by subsequent versions Elite Semiconductor Memory Technology Inc. or modifications due to changes in technical specifications.

1

EN39SL800

Rev. K, Issue Date: 2016/07/22

FEATURES

• Single power supply operation - Full voltage range: 1.65-1.95 volt for read and

write operations. - Ideal for battery-powered applications.

• High performance - Access times as fast as 70 ns

• Low power consumption (typical values at 5 MHz)

- 5 mA typical active read current - 15 mA typical program/erase current - 0.2 μA typical standby current

• Uniform Sector Architecture: - 256 sectors of 2-Kword - 16 blocks of 32-Kword - Any sector or block can be erased individually

• Block protection: - Hardware locking of blocks to prevent

program or erase operations within individual blocks

• Chip Unprotect Mode

• High performance program/erase speed - Word program time: 8µs typical - Sector erase time: 90ms typical - Block erase time: 180ms typical - Chip erase time: 2s typical

• JEDEC Standard Embedded Erase and Program Algorithms

• JEDEC standard DATA# polling and toggle bits feature

• Single Sector, Block and Chip Erase

• Erase Suspend / Resume modes: Read or program another Sector/Block during Erase Suspend Mode

• Support JEDEC Common Flash Interface (CFI).

• Low Vcc write inhibit < 1.2V

• Minimum 100K endurance cycle

• Package Options - 48-ball 6mm x 8mm TFBGA - 48-ball 4mm x 6mm WFBGA

• Industrial temperature Range GENERAL DESCRIPTION

The EN39SL800 is an 8-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 524,288 words. Any word can be programmed typically in 8µs.The EN39SL800 features 1.8V voltage read and write operation, with access time as fast as 70ns to eliminate the need for WAIT statements in high-performance microprocessor systems.

The EN39SL800 has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#) controls, which eliminate bus contention issues. This device is designed to allow either single Sector/Block or full chip erase operation, where each block can be individually protected against program/erase operations or chip unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector or block.

EN39SL800 8 Megabit (512K x 16-bit) Flash Memory With 4Kbytes Uniform Sector, CMOS 1.8 Volt-only


2

EN39SL800


CONNECTION DIAGRAMS

TFBGA Top View, Balls Facing Down


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EN39SL800


A6

A2

B6

A4

C6

A6

D6

A17

E6

NC

F6

NC

G6

WE#

H6

NC

J6

A9

K6

A11

A5

A1

B5

A3

C5

A7

D5

NC

H5

NC

J5

A10

K5

A13

L5

A14

A4

A0

B4

A5

C4

A18

J4

A8

K4

A12

L4

A15

A3

CE#

B3

DQ8

C3

DQ10

J3

DQ4

K3

DQ11

L3

A16

A2

VSS

B2

OE#

C2

DQ9

D2

NC

H2

NC

J2

DQ5

K2

DQ6

L2

DQ7

B1

DQ0

C1

DQ1

D1

DQ2

E1

DQ3

F1

VCC

G1

DQ12

H1

DQ13

J1

DQ14

K1

DQ15

L1

VSS

WFBGA Top View, Balls Facing Down


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EN39SL800


Table 1. PIN DESCRIPTION Figure 1. LOGIC DIAGRAM

Pin Name Function

A0-A18 Addresses

DQ0-DQ15 16 Data Inputs/Outputs

CE# Chip Enable

OE# Output Enable

WE# Write Enable

Vcc Supply Voltage (1.65-1.95V)

Vss Ground

NC Not Connected to anything

EN39SL800

DQ0 – DQ15A0 - A18

WE#

CE#

OE#


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EN39SL800


Table 2. Uniform Sector / Block Architecture (Block 8 ~ 15)

Block Sector Address Range

Sector Size (Kwords) A18 A17 A16 A15 A14 A13 A12 A11

(X16)

15

255 07F800h-07FFFFh 2 1 1 1 1 1 1 1 1254 07F000h-07F7FFh 2 1 1 1 1 1 1 1 0253 07E800h-07EFFFh 2 1 1 1 1 1 1 0 1252 07E000h-07E7FFh 2 1 1 1 1 1 1 0 0251 07D800h-07DFFFh 2 1 1 1 1 1 0 1 1250 07D000h-07D7FFh 2 1 1 1 1 1 0 1 0249 07C800h-07CFFFh 2 1 1 1 1 1 0 0 1248 07C000h-07C7FFh 2 1 1 1 1 1 0 0 0247 07B800h-07BFFFh 2 1 1 1 1 0 1 1 1246 07B000h-07B7FFh 2 1 1 1 1 0 1 1 0245 07A800h-07AFFFh 2 1 1 1 1 0 1 0 1244 07A000h-07A7FFh 2 1 1 1 1 0 1 0 0243 079800h-079FFFh 2 1 1 1 1 0 0 1 1242 079000h-0797FFh 2 1 1 1 1 0 0 1 0241 078800h-078FFFh 2 1 1 1 1 0 0 0 1240 078000h-0787FFh 2 1 1 1 1 0 0 0 0

14

239 077800h-077FFFh 2 1 1 1 0 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

224 070000h-0707FFh 2 1 1 1 0 0 0 0 0

13

223 06F800h-06FFFFh 2 1 1 0 1 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

208 068000h-0687FFh 2 1 1 0 1 0 0 0 0

12

207 067800h-067FFFh 2 1 1 0 0 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

192 060000h-0607FFh 2 1 1 0 0 0 0 0 0

11

191 05F800h-05FFFFh 2 1 0 1 1 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

176 058000h-0587FFh 2 1 0 1 1 0 0 0 0

10

175 057800h-057FFFh 2 1 0 1 0 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

160 050000h-0507FFh 2 1 0 1 0 0 0 0 0

9

159 04F800h-04FFFFh 2 1 0 0 1 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

144 048000h-0487FFh 2 1 0 0 1 0 0 0 0

8

143 047800h-047FFFh 2 1 0 0 0 1 1 1 1142 047000h-0477FFh 2 1 0 0 0 1 1 1 0141 046800h-046FFFh 2 1 0 0 0 1 1 0 1

…. …. …. ….

….

….

….

…. …. …. ….

130 041000h-0417FFh 2 1 0 0 0 0 0 1 0129 040800h-040FFFh 2 1 0 0 0 0 0 0 1128 040000h-0407FFh 2 1 0 0 0 0 0 0 0


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EN39SL800


Table 2. Uniform Sector / Block Architecture (Block 0 ~ 7)

Blaok Sector Address Range Sector Size

(Kwords) A18 A17 A16 A15 A14 A13 A12 A11(X16)

7

127 03F800h-03FFFFh 2 0 1 1 1 1 1 1 1 126 03F000h-03F7FFh 2 0 1 1 1 1 1 1 0 125 03E800h-03EFFFh 2 0 1 1 1 1 1 0 1

…. …. …. ….

….

….

….

…. …. …. ….

114 039000h-0397FFh 2 0 1 1 1 0 0 1 0 113 038800h-038FFFh 2 0 1 1 1 0 0 0 1 112 038000h-0387FFh 2 0 1 1 1 0 0 0 0

6

111 037800h-037FFFh 2 0 1 1 0 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

96 030000h-0307FFh 2 0 1 1 0 0 0 0 0

5

95 02F800h-02FFFFh 2 0 1 0 1 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

80 028000h-0287FFh 2 0 1 0 1 0 0 0 0

4

79 027800h-027FFFh 2 0 1 0 0 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

64 020000h-0207FFh 2 0 1 0 0 0 0 0 0

3

63 01F800h-01FFFFh 2 0 0 1 1 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

48 018000h-0187FFh 2 0 0 1 1 0 0 0 0

2

47 017800h-017FFFh 2 0 0 1 0 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

32 010000h-0107FFh 2 0 0 1 0 0 0 0 0

1

31 00F800h-00FFFFh 2 0 0 0 1 1 1 1 1

…. …. …. ….

….

….

….

…. …. …. ….

16 008000h-0087FFh 2 0 0 0 1 0 0 0 0

0

15 007800h-007FFFh 2 0 0 0 0 1 1 1 1 14 007000h-0077FFh 2 0 0 0 0 1 1 1 0 13 006800h-006FFFh 2 0 0 0 0 1 1 0 1 12 006000h-0067FFh 2 0 0 0 0 1 1 0 0 11 005800h-005FFFh 2 0 0 0 0 1 0 1 1 10 005000h-0057FFh 2 0 0 0 0 1 0 1 0 9 004800h-004FFFh 2 0 0 0 0 1 0 0 1 8 004000h-0047FFh 2 0 0 0 0 1 0 0 0 7 003800h-003FFFh 2 0 0 0 0 0 1 1 1 6 003000h-0037FFh 2 0 0 0 0 0 1 1 0 5 002800h-002FFFh 2 0 0 0 0 0 1 0 1 4 002000h-0027FFh 2 0 0 0 0 0 1 0 0 3 001800h-001FFFh 2 0 0 0 0 0 0 1 1 2 001000h-0017FFh 2 0 0 0 0 0 0 1 0 1 000800h-000FFFh 2 0 0 0 0 0 0 0 1 0 000000h-0007FFh 2 0 0 0 0 0 0 0 0


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EN39SL800


PRODUCT SELECTOR GUIDE

Product Number EN39SL800

Speed Option Full Voltage Range: Vcc=1.65 – 1.95 V -70

Max Access Time, ns (tacc)

70

Max CE# Access, ns (tce) 70

Max OE# Access, ns (toe) 30

BLOCK DIAGRAM

WE#

CE# OE#

State Control

Command Register

Erase Voltage GeneratorInput/Output Buffers

Program Voltage Generator

Chip EnableOutput Enable

Logic

Data Latch

Y-Decoder

X-Decoder

Y-Gating

Cell MatrixTimerVcc Detector

A0-A18

Vcc Vss

DQ0-DQ15

Address Latch

Block Protect Switches

STB

STB


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EN39SL800


Table 3. OPERATING MODES

8M FLASH USER MODE TABLE

Operation CE# OE# WE# A0-A18 DQ0-DQ15 Read L L H AIN DOUT Write L H L AIN DIN CMOS Standby Vcc ± 0.2V X X X High-Z Output Disable L H H X High-Z

Block Protect L H L Block Address, A6 = L, A1 = H, A0 = L

DIN

Chip Unprotect L H L Block Address, A6 = L, A1 = H, A0 = L

DIN

Notes: L=logic low= VIL, H=Logic High= VIH, VID =10.0 ± 1.0V, X=Don’t Care (either L or H, but not floating!), DIN=Data In, DOUT=Data Out, AIN=Address In Table 4. DEVICE IDENTIFICTION (Autoselect Codes)

8M FLASH MANUFACTURER/DEVICE ID TABLE

Note: 1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code

7Fh. 2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.

Description CE# OE# WE# A18 to

A15

A14 to

A10A92 A8 A7 A6

A5 to A2

A1 A0 DQ8

to DQ15

DQ7 to DQ0

Manufacturer ID: Eon L L H X X VID

H1

X L X L L X 1Ch

L 7Fh

Device ID L L H X X VID X X L X L H 27h 3Fh

Block Protection Verification L L H BA X VID X X L X H L

X 01h (Protected)

X 00h (Unprotected)


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EN39SL800


USER MODE DEFINITIONS Standby Mode The EN39SL800 has a CMOS-compatible standby mode, which reduces the current to < 0.2µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.2. When in standby modes, the outputs are in a high-impedance state independent of the OE# input. Read Mode The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors/blocks, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more additional information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” additional details. Output Disable Mode When the OE# pin is at a logic high level (VIH), the output from the EN39SL800 is disabled. The output pins are placed in a high impedance state. Auto Select Identification Mode The autoselect mode provides manufacturer and device identification, and block protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID ( 9.0 V to 11.0 V) on address pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying block protection, the block address must appear on the appropriate highest order address bits. Refer to the corresponding block Address Tables. The Command Definitions table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode. Write Mode Write operations, including programming data and erasing sectors/blocks of memory, require the host system to write a command or command sequence to the device. Write cycles are initiated by placing the word address on the device’s address inputs while the data to be written is input on DQ [15:0] in Word Mode. The host system must drive the CE# and WE# pins Low and the OE# pin High for a valid write operation to take place. All addresses are latched on the falling edge of WE# and CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The system is not required to provide further controls or timings. The device automatically provides internally generated program / erase pulses and verifies the programmed /erased cells’ margin. The host system can detect


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EN39SL800


completion of a program or erase operation by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. The ‘Command Definitions’ section of this document provides details on the specific device commands implemented in the EN39SL800. Block Protection and Chip Unprotection The EN39SL800 includes the hardware block protection feature, which disables both program and erase operations in any block. The block protect feature is enabled using programming equipment at the user’s site. Block is unprotected when the devices are shipped. Block Protection To activate the block protection mode, the programming equipment must force VID on address pin A9 and control pin OE#, (VID=10V ± 1.0V), CE# = WE# = VIL. The block addresses (A18-A15) should be set to the block to be protected while (A6, A1, A0) = (VIL, VIH, VIL). Programming of the protection circuitry begins on the falling edge and is terminated with the rising edge of the WE# pulse. Addresses must be held constant during the WE# pulse. Please see Flowchart 7a for Block Protection Algorithms and Figure 11 for the waveform of timings. Verification of the protection circuitry requires the programming equipment to apply VID on address pin A9 while OE# is set at VIL, WE# is at VIH and (A6, A1, A0) = (VIL, VIH, VIL). To check for block protection, scanning of A18 – A15 while (A6, A1, A0) = (VIL, VIH, VIL) and activating CE# will produce 01H at the device’s outputs (DQ0 – DQ7). During this mode, the lower addresses (except for A0, A1, and A6) are don’t care (can be VIL or VIH but not floating). The unspecified addresses are don’t care which means they can be VIL, or VIH, but should not be floating. We also recommend that the data pins also be at VIL or VIH during the time that WE# is at VIL. Chip Unprotection Previously protected blocks can be unprotected using the chip unprotection algorithm as seen in Flowchart 7b and Figure 12 for the waveform of timings. All blocks must be placed in the protection mode using protection algorithm mentioned above before unprotection can be executed. To activate the chip unprotection mode, the programming equipment must force VID on address pin A9 and control pin OE#, (VID=10V ± 1.0V), CE# = WE# = VIL. And set addresses (A6, A1, A0) = (VIH, VIH, VIL). The unprotection circuitry is then invoked by keeping WE# at VIL for a length of tWPP2. To determine if unprotection is complete, each block must be verified. The chip unprotect verify mode is entered by setting OE#=VIL, WE#=VIH, and raising A9 to VID. The unprotection status can then be read from DQ0-DQ7 by setting block address bits A18-A15 to the desired block address, and A6=1, A1=1, A0=0, and CE# to VIL. A 00h on DQ0-DQ7 indicates that unprotection of that particular block is complete; otherwise repeat the process by re-entering the unprotection mode and re-invoking the unprotection circuitry for a period of tWPP2. Repeat the process also if the unprotection status of any other blocks does not indicate 00h on DQ0-DQ7. When DQ0-DQ7 reads 00h for all blocks, chip unprotection is complete. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output is latched and always available to the system. Icc4 in the DC Characteristics table represents the automatic sleep mode current specification.


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EN39SL800


COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-7. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode. Table 5. CFI Query Identification String (1)

Adresses (Word Mode) Data Description

10h 11h 12h

0051h 0052h 0059h

Query Unique ASCII string “QRY”

13h 14h

0002h 0000h Primary OEM Command Set

15h 16h

0040h 0000h Address for Primary Extended Table

17h 18h

0000h 0000h Alternate OEM Command set (00h = none exists)

19h 1Ah

0000h 0000h Address for Alternate OEM Extended Table (00h = none exists)

1. Refer to CFI publication 100 for more details.


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EN39SL800


Table 6. System Interface String

Addresses (Word Mode) Data Description

1Bh 0016h Vcc Min (write /erase) DQ7-DQ4: volts, DQ3 –DQ0: 100 millivolts

1Ch 0020h Vcc Max (write /erase) DQ7-DQ4: volts, DQ3 –DQ0: 100 millivolts

1Dh 0000h Vpp Min. voltage (00h = no Vpp pin present) 1Eh 0000h Vpp Max. voltage (00h = no Vpp pin present) 1Fh 0004h Typical timeout per single word program 2N μs

20h 0000h Typical timeout for Min, size buffer write 2N μs (00h = not supported)

21h 000Ah Typical timeout per individual sector/block erase 2N ms 22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 0005h Max. timeout for word write 2N times typical 24h 0000h Max. timeout for buffer write 2N times typical 25h 0004h Max. timeout per individual sector/block erase 2N times typical

26h 0000h Max timeout for full chip erase 2N times typical (00h = not supported)

Table 7. Device Geometry Definition Addresses

(Word mode) Data Description 27h 0014h Device Size = 2N byte (14h = 20; 220 = 1MByte) 2Ah 2Bh

0000h 0000h

Max. number of byte in multi-byte write = 2N (00h = not supported)

2Ch 0002h Number of Erase Sector/Block Regions within device 2Dh 2Eh 2Fh 30h

00FFh 0000h 0010h 0000h

Erase Sector Region 1 Information (y+1 = Number of sectors; z x 256B = sector size) y = 255 + 1 = 256 sectors (00FFh = 255) z = 16 x 256 Bytes = 4 KByte/sector (0010h = 16)

31h 32h 33h 34h

000Fh 0000h 0000h 0001h

Erase Block Region 2 Information (y+1 = Number of blocks; z x 256B = block size) y = 15 + 1 = 16 blocks (000Fh = 15) z = 256 x 256 Bytes = 64 KByte/block (0100h = 256)


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EN39SL800


Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise. Low VCC Write Inhibit When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO. Write Pulse “Glitch” protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read. Power-up Write Inhibit During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = VIL, WE# = VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.


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EN39SL800


COMMAND DEFINITIONS The operations of EN39SL800 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Block Protection, Program, Sector/Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode. Table 8. EN39SL800 Command Definitions

Command Sequence C

ycle

s

Bus Cycles

1st Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

6th Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr DataRead 1 RA RD

Reset 1 xxx F0

Aut

osel

ect Manufacturer ID 4 555 AA 2AA 55 555 90

000 7F

100 1C

Device ID 4 555 AA 2AA 55 555 90 X01 273F

Block Protect Verify 4 555 AA 2AA 55 555 90 (BA)X02

XX00

XX01

Program 4 555 AA 2AA 55 555 A0 PA PD

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Block Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 50

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Erase Suspend 1 xxx B0

Erase Resume 1 xxx 30

CFI Query 1 55 98 Address and Data values indicated in hex RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PA BA = Block Address: address of the Block to be erased or verified. Address bits A18-A15 uniquely select any Block SA = Sector Address: address of the Sector to be erased or verified. Address bits A18-A11 uniquely select any Sector

Reading Array Data The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors/blocks, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset.


15

EN39SL800


Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a block is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires VID on address bit A9 and is intended for PROM programmers. Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence. The system must write the reset command to exit the autoselect mode and return to reading array data. Programming Command Programming the EN39SL800 is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first. Programming status may be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode. Chip Erase Command Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence.


16

EN39SL800


Any commands written to the chip during the Embedded Chip Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip, Sector/Block Erase Operation Timings for timing waveforms. Sector/Block Erase Command Sequence Sector/Block erase is a six bus cycle operation. The sector/block erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector/block to be erased, and the sector/block erase command. The Command Definitions table shows the address and data requirements for the sector/block erase command sequence. Once the sector/block erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector/Block Erase Operations Timing diagram for timing waveforms. Erase Suspend / Resume Command The Erase Suspend command allows the system to interrupt a sector/block erase operation and then read data from, or program data to, any sector/block not selected for erasure. This command is valid only during the sector/block erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector/block erase operation, the device requires a maximum of 20 µs to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector/block not selected for erasure. (The device “erase suspends” all sector/blocks selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors/blocks produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector/block is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors/blocks. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The Autoselect command is not supported during Erase Suspend Mode. The system must write the Erase Resume command (address bits are don’t-care) to exit the erase suspend mode and continue the sector/block erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.


17

EN39SL800


WRITE OPERATION STATUS DQ7: DATA# Polling The EN39SL800 provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# Polling feature is active during the embedded Programming, Sector/Block Erase, Chip Erase, and Erase Suspend. (See Table 6) When the embedded Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the embedded Programming, an attempt to read the device will produce the true data written to DQ7. For the embedded Programming, DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE# or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of the WE# or CE# pulse for chip erase or sector/block erase. DATA# Polling must be performed at any address within a sector/block that is being programmed or erased and not a protected sector/block. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected block. Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing diagram is shown in Figure 8. DQ6: Toggle Bit I The EN39SL800 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector/block erase or chip erase. In embedded Programming, if the block being written to is protected, DQ6 will toggles for about 2 μs, then stop toggling without the data in the block having changed. In Sector/Block Erase or Chip Erase, if all selected blocks are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read mode without changing data in all protected blocks. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9.


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EN39SL800


DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a “1” on DQ5. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector/Block Erase Timer After writing a sector/block erase command sequence, the output on DQ3 can be used to determine whether or not an erase operation has begun. (The sector/block erase timer does not apply to the chip erase command.) When sector/block erase starts, DQ3 switches from “0” to “1.” This device does not support multiple sector/block erase command sequences so it is not very meaningful since it immediately shows as a “1” after the first 30h command. Future devices may support this feature. DQ2: Erase Toggle Bit II The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector/block is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector/block is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors/blocks that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector/block is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors/blocks are selected for erasure. Thus, both status bits are required for sector/block and mode information. Refer to the following table to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully


19

EN39SL800


completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Flowchart 6). Write Operation Status

Operation DQ7 (note2) DQ6 DQ5

(note1) DQ3 DQ2 (note2)

Standard Mode

Embedded Program Algorithm DQ7# Toggle 0 N/A No

toggle Embedded Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend

Mode

Reading within Erase Suspended Sector/Block 1 No

Toggle 0 N/A Toggle

Reading within Non-Erase Suspended Sector/Block Data Data Data Data Data

Erase-Suspend Program DQ7# Toggle 0 N/A N/A 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See

“DQ5:Exceeded Timing Limits” for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.


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EN39SL800


Table 9. Status Register Bits

DQ Name Logic Level Definition

7

DATA# POLLING

‘1’ Erase Complete or erase Sector/Block in Erase suspend

‘0’ Erase On-Going

DQ7 Program Complete or

data of non-erase Sector/Block during Erase Suspend

DQ7# Program On-Going

6

TOGGLE BIT

‘-1-0-1-0-1-0-1-’ Erase or Program On-going

DQ6 Read during Erase Suspend

‘-1-1-1-1-1-1-1-‘ Erase Complete

5 TIME OUT BIT ‘1’ Program or Erase Error ‘0’ Program or Erase On-going

3 ERASE TIME OUT BIT

‘1’ Erase operation start ‘0’ Erase timeout period on-going

2 TOGGLE BIT

‘-1-0-1-0-1-0-1-’

Chip Erase, Sector/Block Erase or Erase suspend on currently addressed Sector/Block. (When DQ5=1, Erase

Error due to currently addressed Sector/Block. Program during Erase Suspend on-going at current address

DQ2 Erase Suspend read on non Erase Suspend Sector/Block

Notes: DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5 Time Out Bit: set to “1” if failure in programming or erase DQ3 Sector/Block Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES). DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector/Block


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EN39SL800


EMBEDDED ALGORITHMS Flowchart 1. Embedded Program

START

Write Program Command Sequence

(shown below)

Data# Poll Device

Last

Address?

Programming Done

Increment Address

No

Yes

Verify Data?

Flowchart 2. Embedded Program Command Sequence See the Command Definitions section for more information on WORD mode.

2AAH / 55H

555H / AAH

555H / A0H

PROGRAM ADDRESS / PROGRAM DATA


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EN39SL800


Flowchart 3. Embedded Erase Flowchart 4. Embedded Erase Command Sequence See the Command Definitions section for more information on WORD mode.

START

Write Erase Command Sequence

Data Poll from System or Toggle Bit

successfully completed

Erase Done

Data =FFh?

Yes

No


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EN39SL800


Flowchart 5. DATA# Polling Algorithm Notes: (1) This second read is necessary in case the first read was done at the exact instant when the status data was in transition. Flowchart 6. Toggle Bit Algorithm

Notes: (2) This second set of reads is necessary in case

the first set of reads was done at the exact instant when the status data was in transition.

No

Yes

DQ6 = Toggle?

DQ5 = 1?

DQ6 = Toggle?

No

No

Yes

Yes

Read Data twice

Start

Read Data twice (2)

Fail Pass

No

No

DQ7 = Data?

DQ5 = 1?

DQ7 = Data?

Yes

Yes

No

Yes

Read Data

Start

Read Data (1)

Fail Pass


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EN39SL800


Flowchart 7a. In-System Block Protect Flowchart

Yes

Yes

Yes

No

No

No

Read from Block Address A18-A15 while A6=VIL, A1=VIH, A0=VIL

A9= VID, CE#=OE#= VIL,

WE#= VIH

Time Out 100 μs

Activate WE#

OE#= VID, A9= VID, CE#= VIL, Vcc=3.3V A6=0, A1=1, A0=0

PLSCNT=1

Setup Block Address (A18-A15)

START

Data = 01h ? Protect another

Block? PLSCNT=25 ?

Device failed

Increment PLSCNT

Remove VID from A9 Write Reset Command

Block Group Protection Complete Block Protect Algorithm


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EN39SL800


Flowchart 7b. In-System Chip Unprotect Flowchart

Yes

Yes

Yes

No

No No

Set A6=1, A1=1, A0=0, CE# = VIL

Set OE#= VIL, WE#= VIH , A9=VID

Activate WE# Pulse

Set OE#=VID, A9=VID

Setup Chip Unprotect Mode , A6=1, A1=1, A0=0

PLSCNT=1, Set Block Address to SA0

Protect All Blocks

START

Data = 00h ? PLSCNT=1000? Last Block Address?

Remove VID from A9

Increment Block Group Address

Device Failed

Read Data from Device

Increment PLSCNT Time Out 10 ms

Chip Unprotection Completed

Chip Unprotect Algorithm


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EN39SL800


Table 10. DC Characteristics (Ta = - 40°C to 85°C; VCC = 1.65-1.95V)

Notes 1. Maximum IBCCB specifications are tested with Vcc = Vcc max.

Symbol Parameter Test Conditions Min Typ Max Unit

ILI Input Leakage Current 0V≤ VIN ≤ Vcc ±3 µA

ILO Output Leakage Current 0V≤ VOUT ≤ Vcc ±3 µA

ICC1 Active Read Current CE# = VIL, OE# = VIH,F=5MHz

5 10 mA

ICC2 Supply Current (Standby) CE# = Vcc, Vcc = Vcc max 0.2 5.0 µA

ICC3 Supply Current (Program or Erase)Program or Erase in

progress 15 25 mA

ICC4 Automatic Sleep Mode VIH = Vcc ± 0.2 V VIL = Vss ± 0.2 V

0.2 5.0 µA

VIL Input Low Voltage -0.5 0.3 x VCC V

VIH Input High Voltage 0.7 x Vcc Vcc +

0.3 V

VOL Output Low Voltage IOL = 100 μA 0.1 V

VOH Output High Voltage IOH = -100 μA, Vcc - 0.1 V

VID A9 Voltage (Electronic Signature) 9.0 10.0 11.0 V

IID A9 Current (Electronic Signature) A9 = VID 50 µA

VLKO Supply voltage (Erase and

Program lock-out) 1.2 1.5 V


27

EN39SL800


Test Conditions

Test Specifications

Test Conditions -70 Unit Output Load Capacitance, CL 30 pF

Input Rise and Fall times 5 ns Input Pulse Levels 0.0-2.0 V

Input timing measurement reference levels 1/2 Vcc V

Output timing measurement reference levels 1/2 Vcc V


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EN39SL800


AC CHARACTERISTICS Table 11. AC CHARACTERISTICS (Ta = - 40°C to 85°C; VCC = 1.65-1.95 V)

Read-only Operations Characteristics Parameter Symbols Description Test Setup Speed Options UnitJEDEC Standard -70

tAVAV tRC Read Cycle Time Min 70 ns

tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL

Max 70 ns

tELQV tCE Chip Enable To Output Delay OE# = VIL Max 70 ns

tGLQV tOE Output Enable to Output Delay Max 30 ns

tEHQZ tDF Chip Enable to Output High Z Max 20 ns

tGHQZ tDF Output Enable to Output High Z Max 20 ns

tAXQX tOH

Output Hold Time from Addresses, CE# or OE#, whichever occurs first

Min 0 ns

tOEH

Output Enable Hold Time

Read Min 0 ns Toggle and Data# Polling Min 10 ns

Notes: 1. High Z is Not 100% tested. 2. For – 70 Vcc =1.65 – 1.95V Output Load : 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to Vcc Timing Measurement Reference Level, Input and Output: 1/2 Vcc

Figure 2. AC Waveforms for READ Operations

Addresses

CE#

OE#

WE#

Outputs

tBACC

tBRCB

Addresses Stable

t BOE B

HIGH Z Output Valid

t BCE B tBOH

tBDF

t BOEH B

HIGH Z


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EN39SL800


Table 12. AC CHARACTERISTICS (Ta = - 40°C to 85°C; VCC = 1.65-1.95V) Write (Erase/Program) Operations

Parameter Symbols Description Speed Options

JEDEC Standard -70 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 45 ns

tDVWH tDS Data Setup Time Min 30 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recovery Time before Write (OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 35 ns

tWHDL tWPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 8 µs

tWHWH2 tWHWH2 Erase Operation (Note 2)

Sector Typ 0.09 s

Block Typ 0.18 s

Chip Typ 2 s

tVCS Vcc Setup Time (Note 1) Min 50 µs

tVT Voltage Transition Time Min 500 ns

tWPP1 Block Pulse Width Min 100 μs

tWPP2 Chip Unprotection Pulse Width Min 10 ms

tST Voltage setup time Min 4 μs Notes: 1. Not 100% tested. 2. See Erase and Programming Performance for more information.


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EN39SL800


Table 13. AC CHARACTERISTICS (Ta = - 40°C to 85°C; VCC = 1.65-1.95V) Write (Erase/Program) Operations Alternate CE# Controlled Writes

Parameter Symbols Description Speed Options

JEDEC Standard -70 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 ns

tDVEH tDS Data Setup Time Min 30 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time before Write (OE# High to CE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 35 ns

tEHEL tCPH CE# Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 8 µs

tWHWH2 tWHWH2 Erase Operation

(Note 2)

Sector Typ 0.09 s

Block Typ 0.18 s

Chip Typ. 2 s

Notes: 1. Not 100% tested. 2. See Erase and Programming Performance for more information.


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EN39SL800


Table 14. ERASE AND PROGRAMMING PERFORMANCE

Parameter Limits Comments Typ Max Unit

Sector Erase Time 0.09 0.4 sec Excludes 00H programming prior

to erasure Block Erase Time 0.18 2 sec

Chip Erase Time 2 20 sec

Word Programming Time 8 200 µs Excludes system level overhead

Chip Programming Time 4 5.5 sec

Erase/Program Endurance 100K cycles Minimum 100K cycles

Table 15. DATA RETENTION

Parameter Description Test Conditions Min Unit

Data Retention Time 150°C 10 Years

125°C 20 Years


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EN39SL800


AC CHARACTERISTICS Figure 3. AC Waveforms for Chip Erase Operations Timings Notes: 1. VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command

sequence.

VCC

Addresses

CE#

OE#

WE#

Data

tCH

tGHWL

tCS tWPH

tWP

tWHWH2

tDH tDS

0x55 0x10 Status DOUT

tVCS

Erase Command Sequence (last 2 cycles) Read Status Data (last two cycles)

tWCtAS tAH

0x2AA 0x555 VA VA


33

EN39SL800


AC CHARACTERISTICS Figure 4. AC Waveforms for Block Erase Operations Timings Notes: 1. BA=Block Address (for block erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command

sequence.

VCC

Addresses

CE#

OE#

WE#

Data

tCH

tGHWL

tCS tWPH

tWP

tWHWH2

tDH tDS


tVCS


tWCtAS tAH

0x2AA BA VA VA


34

EN39SL800


Figure 5. AC Waveforms for Sector Erase Operations Timings Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command

sequence.

VCC

Addresses

CE#

OE#

WE#

Data

tCH

tGHWL

tCS tWPH

tWP

tWHWH2

tDH tDS


tVCS


tWC tAS tAH

0x2AA SA VA VA


35

EN39SL800


Figure 6. Program Operation Timings Notes: 1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address. 2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command

sequence.

tVCS

DOUT Status PDOxA0

tDS tDH

tWHWH1

tAHtAS tWC

0x555 PA PA PA

Program Command Sequence (last 2 cycles) Program Command Sequence (last 2 cycles)

tGHWL

Data

VCC

WE#

Addresses

CE#

OE# tCH

tWPH tCS

tWP


36

EN39SL800


Figure 7. AC Waveforms for /DATA Polling During Embedded Algorithm Operations Notes: 1. VA=Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle. Figure 8. AC Waveforms for Toggle Bit During Embedded Algorithm Operations

tCE

tOE

tCH

Valid Data Valid Status Valid Status Valid Status

(first read) (second read) (stops toggling)

Addresses

CE#

OE#

WE#

DQ6, DQ2

tRC

tACC

VA VA VA VA

tOEH tDF

tOH

tOEH tDF

tOE

tCE

tCH tACC

tRC

VA VA VA

tOH

Valid Data True Complement Comple-ment

Status Data Status Data True Valid Data

CE#

Addresses

OE#

WE#

DQ[7]

DQ[6:0]


37

EN39SL800


Figure 9. Alternate CE# Controlled Write Operation Timings Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status Dout = array data read at VA Figure 10. DQ2 vs. DQ6

WE#

DQ6

DQ2

Enter Embedded

Erase Erase

Suspend

Enter Erase Suspend Program

Erase Resume

Erase Enter Suspend

Read

Enter Suspend Program

Erase Erase Complete

Erase Suspend Read

DOUT StatusPD for Program 0x30 for Sector Erase 0x50 for Block Erase 0x10 for Chip Erase

0xA0 for Program

tDS tDH

tWH tGHEL

tCP tCPH tWS tWHWH1 / tWHWH2

Addresses

WE#

OE#

CE#

Data

tAH tAS tWC VA

PA for Program SA for Sector Erase BA for Block Erase 0x555 for Chip Erase

0x555 for Program 0x2AA for Erase


38

EN39SL800


Figure 11. Block Protect Timing Diagram Notes: Use standard microprocessor timings for this device for read and write cycles. For Block Protect, use A6=0, A1=1, A0=0.

SAx = Block Address for initial block SAy = Block Address for next block

12V

A18-A12

A0

A1

A6

A9

12V

OE#

WE#

CE#

DATA

SAx SAy

tVT

tOE

01htST

tWPP

tST

tVT

tVT


39

EN39SL800


Figure 12. Chip Unprotect Timing Diagram Notes: Use standard microprocessor timings for this device for read and write cycles. For Chip Unprotect, use A6=1, A1=1, A0=0.

Data

CE#

WE#

OE#

A9

A6

A1

A0

A17, A18, A19

tVT

tVT

VIL

VID

VIH

VIL

VIH

VIL

SAx SAy VIH VIL

VID

VIL

00 h

tOE tST

VIL

VIH

VIH

VIL

tST

tWPP2

VIH

VIL


40

EN39SL800


Figure 13. 48L TFBGA 6mm x 8mm package outline

MIN. NOR MAXA - - - - - - 1.30A1 0.23 0.29 - - -A2 0.84 0.91 - - -D 7.90 8.00 8.10E 5.90 6.00 6.10

D1 - - - 5.60 - - -E1 - - - 4.00 - - -e - - - 0.80 - - -b 0.35 0.40 0.45

DIMENSION IN MMSYMBOL

Note : 1. Coplanarity: 0.1 mm


41

EN39SL800


Figure 14. 48L WFBGA 4mm x 6mm package outline

Note : Controlling dimensions are in millimeters (mm).


42

EN39SL800


ABSOLUTE MAXIMUM RATINGS

Parameter Value Unit Storage Temperature -65 to +150 ℃

Plastic Packages -65 to +125 ℃

Ambient Temperature With Power Applied -55 to +125 ℃

Output Short Circuit Current1 200 mA

Voltage with Respect to Ground

A9, OE# 2 -0.5 to +11.0 V

All other pins 3 -0.5 to Vcc+0.5 V

Vcc -0.5 to Vcc+0.5 V

Notes: 1. No more than one output shorted may be shorted to ground at a time. Duration of the short circuit should not be greater than one

second. 2. Minimum DC input voltage on A9 and OE# pins is –0.5V. During voltage transitions, A9 and OE# pins may undershoot Vss to –1.0V

for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9 and OE# is 9.0V which may overshoot to 11.0V for periods up to 20ns.

3. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.

4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.

RECOMMENDED OPERATING RANGES1

Parameter Value Unit

Ambient Operating Temperature Industrial Devices -40 to 85 ℃

Operating Supply Voltage Vcc

Full Voltage Range: 1.65 to 1.95 V

1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.

Vcc

+2.0V

Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform

0

0


43

EN39SL800


Purpose

Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon’s product family.

Eon products’ New Top Marking

cFeon Top Marking Example:

For More Information

Please contact your local sales office for additional information about Eon memory solutions.

cFeon Part Number: XXXX-XXX Lot Number: XXXXX Date Code: XXXXX


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EN39SL800


ORDERING INFORMATION EN39SL800 - 70 B I P PACKAGING CONTENT P = RoHS compliant

TEMPERATURE RANGE I = Industrial (-40°C to +85°C) PACKAGE

B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA) 0.8mm pitch, 6mm x 8mm package N = 48-Ball Very-Very-Thin-Profile Fine Pitch Ball Grid Array (WFBGA) 0.5mm pitch, 4mm x 6mm package SPEED

70 = 70ns

BASE PART NUMBER EN = Eon Silicon Solution Inc. 39SL = 1.8V Serial 4KByte Uniform-Sector FLASH 800 = 8 Megabit (512K x 16)


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EN39SL800


Revisions List Revision No Description Date A Initial Release 2009/02/20

B 1. Modify Table 5 addresses 13h = 0002h, 14h = 0000h and 15h = 0040h on

page 12. 2. Update Table 12, 13 on page 31 and 32.

2009/03/03

C 1. Correct typo 15 5 mA typical active read current in page 1. 2. Correct typo tBUSY Min Max in Page 31. 2009/03/24

D To modify Table 10, Icc1 active read current (max.) from 6mA to 10mA on page 26 2009/05/13

E

1. Modify TFBGA ball diagram (BYTE#, RESET# and RY/BY# pins are changed to NC status)

2. Removal of WLGA 5mm x 6mm package definition 3. addition of TSOP (type 1) package information

2009/06/08

F 1. Removal of all of 90ns descriptions 2. modify the max sector erase time to 0.4s 3. adding byte / word programming maximum time

2009/06/15

G

1. Remove the BYTE#, RESET# and RY/BY# functions and TSOP (type 1) package information.

2. Modify the description of Block Protection and Chip Unprotection on page 10, 24, 25, 38 and 39.

2009/08/18

H Update Table 4.DEVICE IDENTIFICTION (Autoselect Codes) on page 8. 2011/02/14 I Add Support JEDEC Common Flash Interface (CFI) information on page 1. 2012/03/19 J Correct the typo for the connection diagrams of WFBGA on page 3. 2013/10/24 K Develop 2016/07/22

en39sl800 8 megabit (512k x 16-bit) flash memory with ...€¦ · this data sheet may be revised by...

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