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Subject Program

Subject Identification

Organic Unity

Course : [IS] Informática para a Saúde Degree :

Subject/Module : Arquitecturas e Tecnologias dos Computadores Kind : required

Scientific Field : Communication and Information Technologies ECTS : 7

Year : 1º Semester : 2º School Year : 2010/2011

Prerequisites : None

Hours Of Workload

Theory Classes (TC) 45:00

Practical Laboratory (PL) 45:00

Tutorial (T) 5:00

Hours of Autonomous Work 94:00

Horas Totais 189:00

Lecturing Language Portuguese

Lecturers

Main Lecturer : Rui Vasco Guerra Baptista Monteiro

Lecturers

Rui Vasco Guerra Baptista Monteiro

Framework

This introductory subject aims to provide students with broad knowledge regarding PC hardware, focusing on understandingthe operation of a personal computer. In addition, it is intended to provide basic skills in the area of data networks, forstudents acquire knowledge and techniques that will help him to achieve competence in others Course Units.

Objectives/Skills

General

C1 - knowledge of computer systems components and understand how it work.

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C2 - Follow the trends of the technology used in computers and their costs.

C3 - Acquire skills in technical specification of computer hardware components according to the budget and the purpose forwhich it is intended.

C4 - Concepts about the OSI and TCP/IP reference models, network devices, wiring, Local Area Networks, network designand IP addressing.

Specific

C1.1 - Basic and medium knowledge regarding computer technology and computer organizations and designs.

C1.2 - Implement assembling operations, setup operations, maintenance operations, expansion operations and mostfrequent upgrades of desktop personal computers.

C1.3 - Develop abilities for: installing operating systems in dual boot (Windows and Linux), performing hard disks partitionsimages, performing basic administration and management of operating systems and understanding the use of operatingsystems from the user and system administration point of view.

C2.1 - Ability to use, in an efficient manner, technical information in order to describe the capabilities of computer hardwarecomponents.

C2.2 - Ability to measure and compare computer performance with the use of benchmark tools.

C3.1 - Evaluation and comparison of technical specifications of computer hardware components

C4.1 - Get solid knowledge of the TCP/IP protocol stack, the communication process and the protocols involved.

C4.2 – Acquire basic skills regarding IPv4 addressing.

C4.3 - Use of active network devices - routers, switches and hubs.

C4.4 – Ability to apply theoretical and practical knowledge in the management of a network infrastructure.

Transversal

C5 - Initiation into the practice of bibliographic research and oral communication.

C6 - Ability to work as a team.

C7 - Ability to study and learn independently.

C8 - Ability to integrate knowledge in several areas.

C9 - Ability to understand English texts.

C10 - Ability to analyze the content of computer hardware datasheets within the context of the autonomous preparation ofLaboratory Projects.

C11 - Ability to produce technical reports within the context of the autonomous preparation of Laboratory Projects.

Contents

Synopsis


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Chapter I - Personal Computer (PC) Architecture

Chapter II - Computer Buses

Chapter III - Processors

Chapter IV - Motherboards

Chapter V - Memory

Chapter VI - Data Storage Devices

Chapter VII - Video System

Chapter VIII - RAID Technology

Chapter IX - Benchmark Tools

Chapter X - Specification of Computer Hardware

Chapter XI - Basic concepts about networks

Chapter XII - IP Addressing

Complete

Chapter I - Personal Computer (PC) Architecture

1. Introduction

2. From ENIAC to PC

3. Personal Computer

4. Von Neumann Model

4.1. Central Processing Unit

4.2. Memory Unit

4.3. Input/ Output Devices

4.4. Bus

4.4.1. Definition of Data Transfer Rate

4.4.2. Definition of Bandwidth

5. Functional Division of a Modern PC

6. Physical Components of a Modern PC

6.1. Processor

6.2. Main Memory

6.3. Expansion Boards

6.4. Motherboard

6.5. Chipset

6.6. Clock Signal Generator

7. Processor Microarchitecture

7.1. Definition of Processor Microarchitecture

7.2. Definition of Processor Architecture


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7.3. Processor Microarchitecture vs. Processor Architecture

7.4. Types of Processors

- For servers

- For desktops

- For mobile

7.5. Processor Market Profiles

- Performance

- Mainstream

- Value

7.6. Chronological Evolution of Intel Processor Microarchitectures

7.7. Chronological Evolution of AMD Processor Microarchitectures

8. Personal Computer Architecture

8.1. Key Features of the PC Architecture Evolution

8.2. PC Architecture Evolution for Intel Processor Microarchitectures

8.3. PC Architecture Evolution for AMD Processor Microarchitectures

9. PC Architecture Evolution - PC Systems with Intel Processors

9.1. P5 Microarchitecture

9.2. P6 Microarchitecture

9.3. Netburst Microarchitecture

9.4. Core Microarchitecture

9.5. Nehalem Microarchitecture

9.6. Sandy Bridge Microarchitecture

9.7. PC Architectural Diagrams Summary for Intel Processors

10. PC Architecture Evolution - PC Systems with AMD Processors

10.1. K7 Microarchitecture



10.4. PC Architectural Diagrams Summary for AMD Processors

10.5. Fusion APU Bobcat Microarchitecture

10.6. Fusion APU K10/Stars Microarchitecture

10.7. Bulldozer Microarchitecture

11. Chronological Summary of Architecture PC Features Trends

12. PC Architecture Roadmap

Chapter II - Computer Buses

1. Introduction


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2. Key Features Buses

2.1. Lane types

2.2. Bus width

2.3. Data cycles per clock

2.4. Bus speed or frequency

2.5. Data Transfer Rate

2.6. Bandwidth

2.7. Bus mastering

2.8. Synchronism

3. Personal Computer Bus Types

3.1. Criteria for bus classification

3.2. Buses Range

- System Bus

- Expansion Bus

- Input/ Output Bus

4. System Bus

4.1. CPU-Caches Bus

4.2. CPU-Chipset Bus

4.2.1. FSB Parallel Bus

4.2.2. QPI Serial Bus

4.2.3. DMI Serial Bus

4.2.4. HyperTransport Serial Bus

4.2.5. UMI Serial Bus

4.3. Main Memory Bus

5. Expansion Bus

5.1. PC Bus

5.2. 16 bit ISA

5.3. MCA

5.4. EISA

5.5. VESA local bus

5.6. PCI

5.7. PCI-X

5.8. AGP

5.9. Chipset Northbridge-Southbridge Bus

5.10. PCI Express

6. Input/ Output Bus

6.1. PATA


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6.2. SATA

6.3. SCSI

6.4. USB

6.5. IEEE 1394 or FireWire

6.6. Thunderbolt

Chapter III. Processors

1. Introduction

2. Basic processor operation concepts

2.1. Processor Architecture

2.2. Processor Microarchitecture

2.3. Processor Microarchitecture vs. Processor Architecture

2.4. Processor and Von Neumann Model

2.5. Basic structure of the Processor

2.6. Computer Program

2.7. Programming Languages

2.8. Source Code vs. Machine Code

2.9. Compiled Programs vs. Interpreted Programs

2.10. Processor Basic Operation

3. Instruction Execution Mechanisms

3.1. Instruction Set Models

3.2.1. Complex Instruction Set Computer (CISC)

3.2.2. Reduced Instruction Set Computer (RISC)

3.2.3. Post-RISC

3.2. Programming Model

3.2.1. ALU

3.2.2. Registers

3.2.3. Input/ Output Unit

3.2.4. Control Unit

3.3. Types of Instructions

3.3.1. Data Transfer Instructions

3.3.2. Data Manipulation Instructions

3.3.3. Control Program Instructions

3.4. The Lifecycle of an Instruction

3.5. Instruction Stages

3.5.1. Fetch Stage


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3.5.2. Decode Stage

3.5.3. Execute Stage

3.5.4. Write Stage

3.6. Register File

3.7. Execution Units

3.7.1. Arithmetic and Logical Unit (ALU)

3.7.2. Floating Point Unit (FLU)

3.7.3. Load-Store Unit (LSU)

3.7.4. Branch Execution Unit (BEU)

3.8. Processor’s basic instruction flow

3.9. Pipelined Execution

3.10. Superscalar Execution

3.11. Pipelined Execution Structural Hazards and Superscalar Execution Structural Hazards

3.11.1. Structural Hazards

3.11.2. Control Hazards

3.11.3. Data Hazards

3.12.Register Renaming

4. Processor Manufacturing Process

5. Processor Evolution Major Features

6. x86 Processors Taxonomy

6.1. Purpose

6.2. Registers

6.3. Generations

6.4. Microarchitectures

7. 4 and 8 bit Intel Processors

7.1. 4 bit Processor - 4004 Processor

7.2. 8 bit Processors

- 8008 and 8080 Processors

8. 16 bit Intel Processors

8.1. 8086 Microarchitecture

- 8086 and 8088 Processors

8.2. 186 Microarchitecture - 80186

8.3. 286 Microarchitecture - 80286

9. 32 bit Intel Processors – i386 Microarchitecture

9.1. Microarchitecture Key Features

9.2. Main Microarchitecture Processors


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- 80386DX and 80386SX Processors

10. 32 bit Intel Processors - i486 Microarchitecture



- 80486DX, 80486SX, 80486DX2 and 80486DX4 Processors

11. 32 bit Intel Processors- P5 Microarchitecture


11.2. Microarchitecture Block Diagram


- Pentium P5, Pentium P54C and Pentium MMX Processors

12. 32 bit Intel Processors – P6 Microarchitecture




- Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, Pentium III Xeon, Celeron Covington, CeleronMendocino, Celeron Coppermine and Celeron Tualatin Processors

13. 32 bit Intel Processors - NetBurst Microarchitecture




- Pentium 4 Willamette, Pentium 4 Northwood, Xeon, Celeron Willamette and Celeron Northwood Processors

14. 32 bit AMD Processors – K5 Microarchitecture



14.3. K5 Processor





- K6, K6-2 and K6-III Processors





- Athlon K7, Athlon K75, Athlon Thunderbird, Athlon XP Palomino, Athlon XP Thoroughbred, Athlon XP Barton,Duron Spitfire, Duron Morgan and Sempron Processors

17. 64 bit Intel Processors (IA-64) – Merced and McKinley Microarchitectures



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- Itanium and Itanium 2 Processors

18. 32/64 bit Intel Processors Intel (IA-32/x86-64) – NetBurst Microarchitecture



- Pentium 4 (Prescott, Prescott-2M and Cedar Mill), Pentium 4 Extreme Edition (Gallatin and Prescott-2M),Pentium D (Smithfield and Presler) , Pentium Extreme Edition (Smithfield and Presler) and Celeron D (Prescott-256 and CedarMill-512) Processors

19. 32 bit Intel Processors (IA-32) – Mobile Microarchitecture




- Pentium M (Banias and Dothan), Core Solo (Yonah), Core Duo (Yonah) and Celeron M (Banias-512, Dothan-1M,Dothan-512 and Yonah) Processors

20. 64 bit Intel Processors (x86-64) - Core Microarchitecture




- Core 2 Duo (Allendale, Conroe, Wolfdale, Merom and Penryn), Core 2 Solo (Penryn), Core 2 Quad (Kentsfield,Yorkfield and Penryn), Core 2 Extreme (Conroe XE, Kentsfield XE, Yorkfield XE, Merom and Penryn), Pentium Dual-Core(Conroe, Wolfdale, Merom and Penryn), Celeron Dual-Core (Allendale, Wolfdale-3M, Merom and Penryn) and Celeron M(Merom and Penryn) Processors

20.4. Summary of Mobile and Core Microarchitectures

21. Intel Microarchitectures Evolution and the Tick-Tock Model

21.1. Adopted Strategy for Development of new Microarchitectures

21.2. Tick-Tock Model

21.3. Tick-Tock Model Future Evolution

22. 64 bit Intel Processors (x86-64) – Nehalem Microarchitecture




- Desktop Core i7 (Bloomfield, Lynnfield and Gulftown), Desktop Core i5 (Lynnfield and Clarkdale), Desktop Corei3 (Clarkdale) and Desktop Pentium Series G6xxx (Clarkdale) Processors

- Mobile Core i7 (Clarksfield and Arrandale), Mobile Core i5 and Mobile Core i3 (Arrandale) Processors

23. Sandy Bridge Microarchitecture




- Desktop and Mobile Core i7-2xxx, Desktop and Mobile Core i5-2xxx and Desktop and Mobile Core i3-2xxx

24. Intel Processors Market Strategy


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24.1. Desktop Intel Processors

24.2. Mobile Intel Processors

25. Intel Processors Roadmap

26. 64 bit AMD Processors (x86-64) - K8 (Hammer) Microarchitecture



26.3. Single-core Processors

- Opteron (Sledgehammer), Athlon 64 (Clawhammer, Newcastle, Venice, Winchester, San Diego, Manchester,Toledo, Orleans and Lima), Athlon 64 FX (Sledgehammer, Clawhammer and San Diego) and Sempron 64 (Paris, Palermo,Manila and Sparta)

26.4. Dual-core Processors

- Athlon 64 X2 (Manchester, Toledo, Windsor and Brisbane), Athlon 64 FX (Toledo and Windsor) and Sempron X2(Brisbane)

27. 64 bit AMD Processors (x86-64) - K10 (Barcelona) Microarchitecture



27.3. AMD Processors Renaming

27.4. 65nm Processors

- Phenom X4 - Agena, Phenom X3 - Toliman and Athlon X2 - Kuma

27.5. 45nm Processors

- Phenom II X4 - Deneb, Phenom II X3 - Heka, Phenom II X2 - Callisto, Phenom II X6 – Thuban, Phenom II X4 –Zosma, Athlon II X2 – Regor, Athlon II X4 - Propus, Athlon II X3 - Rana and Sempron Series 100 - Sargas

28. AMD Fusion APU

28.1. Fusion Project Key Features

28.2. Main AMD Fusion APU

- G-Series (Ontario and Zacate), Z-Series (Desna), C-Series (Ontario), E-Series (Zacate) and A-Series (Llano)

28.3. AMD Fusion APU Microarchitectures

28.3.1. Bobcat Microarchitecture

- Ontario APU (C-Series AMD) and Zacate APU (E-Series AMD)

28.3.2. K10/Stars Microarchitecture Improvement

- Llano APU (A-Series AMD)

29. AMD Processors Market Strategy

29.1. AMD Platform until 2010

29.1.1. Servers Processors

29.1.2. Desktops Processors

29.1.3. Mobile Processors

29.2. Desktop AMD Processors for 2011

29.2.1. Brazos Platform


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- C-Series APU (Ontario) and E-Series APU (Zacate)

29.2.2. Lynx Platform

- A-Series APU (Llano)

29.2.3. Scorpius Platform

- FX-Series CPU (Zambezi)

29.3. Mobile AMD Processors for 2011

29.3.1. Brazos Platform

- C-Series APU (Ontario) and E-Series APU (Zacate)

29.3.2. Sabine Platform

- A-Series APU (Llano)

30. 64 bit AMD APU (x86-64) - Bobcat Microarchitecture



30.3. Main Microarchitecture APU

- Ontario (C-Series APU) and Zacate (E-Series APU)

31. 64 bit AMD APU (x86-64) - K10/Stars Microarchitecture



31.3. Main Microarchitecture APU

- Llano (A-Series APU)

32. 64 bit AMD Processors (x86-64) - Bulldozer Microarchitecture




- Zambezi AMD CPU - FX-8xxx Series, Zambezi AMD CPU - FX-6xxx Series and Zambezi AMD CPU - FX-4xxxSeries

33. AMD Processors Roadmap

Chapter IV. Motherboards

1. Introduction

2. Motherboards Role

2.1. Chipset

2.2. BIOS

2.3. UEFI

3. Motherboard Generic Framework

3.1. Processor Connector

- Processor Connector Evolution


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3.2. Memory Modules Connectors

- Memory Modules Connectors Evolution

3.3. Slots

- Slots Evolution

3.4. Power Connectors

3.5. Floppy Drive Connectors

3.6. PATA Devices Connectors

3.7. SATA Devices Connectors

3.8. Rear Panel Connectors

3.9. Chipset

3.10. Jumpers and DIP Switches

3.11. Others components

3.12. BIOS

4. Case

4.1. Case Function

4.2. Case Form Factors

4.2.1. Desktop

4.2.2. Slim Desktop

4.2.3. Tower

4.3. Main Case Standards

4.3.1. AT Format

4.3.2. Baby AT (BAT) Format

4.3.3. ATX Format

4.3.4. MicroATX Format

4.3.5. LPX Format

5. Power Supply Unit

5.1. Power Supply Role

5.2. Main Power Supply Form Factors

5.2.1. AT Power Supply

5.2.2. ATX Power Supply

5.2.3. ATX12V Power Supply

5.2.4. EPS12V Power Supply

5.3. Power Supply Connectors

5.3.1. AT Connectors - P8 and P9

5.3.2. 20 pin ATX Power Connector

5.3.3. 24 pin ATX Power Connector

5.3.4. 20 + 4pin ATX Power Connector


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5.3.5. 4 pin ATX12V Power Connector

5.3.6. 8 pin EPS12V Power Connector

5.3.7. 2 x 4 pin ATX12V Power Connector

5.3.8. 6 pin Auxiliary Power Connector

5.3.9. Floppy Drive Power Connector

5.3.10. IDE/PATA Devices Power Connector

5.3.11. SATA Devices Power Connector

5.3.12. 6 pin PCI Express Connector

5.3.13. 8 pin PCI Express Connector

5.3.14. 6 +2 pin PCI Express Connector

5.4. Evolution of Power Supplies

6. Main Motherboards Form Factors

6.1. AT Form Factor

6.2. Baby AT (BAT) Form Factor

6.3. ATX Form Factor

6.4. MicroATX Form Factor

7. Evolution of Motherboards which support both Intel and AMD Processors

7.1. 80386 Processor supported

7.2. Socket 3 supported



8. Evolution of Motherboards which support Intel Processors

8.1. Slot 1 supported








9. Evolution of Motherboards which support AMD Processors

9.1. Slot A supported

9.2. Socket A supported





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9.6. Socket AM2 supported

9.7. Socket AM2+ supported

9.8. Socket AM3 supported

9.9. Socket FT1 supported

9.10. Socket FM1 supported

9.11. Socket AM3+ supported

Chapter V. Memory

1. Introduction

2. Memory Hierarchy

3. Memory Function

3.1. Cache Memory

3.2. Main Memory

3.3. Secondary Memory

3.4. Virtual Memory

4. Memory Features

5. Error Correcting and Detection

5.1. Parity

5.2. Error Correcting Code (ECC)

6. Information Storage

7. Types of Memory

7.1. ROM Memories

- PROM Memories

- EPROM Memories

- EEPROM Memories

- Flash ROM

7.2. RAM Memories

- Static RAM (SRAM) Memory

- Dynamic RAM (DRAM) Memory

8. SRAM Memory

8.1. SRAM Memory Structure

8.2. SRAM Memory Technologies

8.3. Example of SRAM Memory Chip

8.4. SRAM Memory Read Operation/ Write Operation

9. DRAM Memory

9.1. DRAM Memory Structure

9.2. DRAM Memory Physical Appearance


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- Example of DRAM Memory Chip

9.3. Conceptual Model of DRAM Memory Chip

9.4. DRAM Memory Access

- Read operation

9.5. DRAM Memory Refresh

9.6. 1 bit Memory Cell vs. 1 byte Memory Cell

- Concept of Memory Module

9.7. Memory Banks

9.8. Types of Memory Modules

- 30 pin SIMM

- 72 pin SIMM

- 168 pin DIMM

- 184 pin DIMM

- 240 pin DIMM

9.9. Chip Packaging used in Memory Modules

- DIP (Dual Inline Package)

- SOJ (Small Outline J-Lead)

- TSOP (Thin Small Outline Package)

- FBGA (Fine Pitch Ball Grid Array)

10. DRAM Memory Technologies

10.1. Memory Evolution Summary

10.2. Asynchronous Memory

10.3. Synchronous Memory

11. Asynchronous DRAM Memory

11.1. Timings

11.2. Types of Asynchronous Memory Technology

11.2.1. Conventional DRAM

11.2.2. FPM (Fast Page Mode) DRAM

11.2.3. EDO (Extended Data Out) DRAM

11.2.4. BEDO (Burst EDO) DRAM

12. Synchronous DRAM Memory

12.1. Synchronous Memory Concept

12.2. Commands used by Synchronous Memory

12.3. Steps in Synchronous Memory Access

12.4. Timings

12.5. Types of Synchronous Memory Module Packaging


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12.6. Enhanced Concept of Memory Bank

12.7. Chip Organization and Modules Organization

12.8. Multiples Memory Banks

12.9. Types of Synchronous Memory Modules

- Unbuferred

- Registered

12.10. Types of Synchronous Memory Chip

- Stacking chips

12.11. Types of Synchronous Memory Technology

- SDR SDRAM Memory

- DDR SDRAM Memory

- DDR2 SDRAM Memory

- DDR3 SDRAM Memory

13. Synchronous Memory Technologies - SDR SDRAM Memory

13.1. Types of SDR SDRAM Memory Modules

13.1.1. PC66 SDRAM

13.1.2. PC100 SDRAM

13.1.3. PC133 SDRAM

13.2. Key Features of SDR SDRAM Module

13.3. Examples of SDR SDRAM Memory Module

13.4. Components of Memory Module

13.5. Speed of Memory Module

14. Synchronous Memory Technologies - DDR SDRAM Memory

14.1. Components of Memory Module

14.2. Key Features of DDR SDRAM Module

14.3. Types of DDR Memory Modules

14.4. Concept of Memory Rank

- Memory Bank vs. Memory Rank

14.5. Examples of DDR Memory Module

14.6. Bandwidths

14.7. DDR SDRAM vs. SDR SDRAM

14.8. Dual Channel vs. Single Channel

14.9. Serial Presence Detect (SPD)

15. Synchronous Memory Technologies - DDR2 SDRAM Memory

15.1. Key Features of DDR2 Module

15.2. Components of DDR2 Memory Module

15.3. DDR2 Memory Modules


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15.4. DDR2 Memory Modules vs. DDR Memory Modules

15.5. DDR2 CAS Latency

15.6. DDR2 S Single Channel Mode vs. DDR Dual Channel Mode

15.7. Types of DDR2 Memory Modules

15.8. Examples of DDR2 Memory Module

16. Synchronous Memory Technologies – DDR3 SDRAM Memory

16.1. Key Features of DDR3 Module

16.2. DDR3 Memory vs. DDR3L Memory

16.3. Components of DDR3 Memory Module

16.4. DDR3 Memory Modules

16.5. DDR3 Improvements

16.6. Types of DDR3 Memory Modules

16.7. Examples of DDR3 Memory Module

16.8. DDR3 Modules vs. DDR2 Modules vs. DDR Modules

16.9. Extreme Memory Profile (XMP)

17. Synchronous Memory Technologies - Mobile SDRAM Memory

17.1. Key Features

17.2. Types of Memory

17.2.1. Mobile SDR

17.2.2. Low Power DDR (LPDDR)

17.2.3. Low Power DDR2 (LPDDR2)

18. Memory Packaging

18.1. Dual Inline Package (DIP)

18.2. 30 pin Single Inline Memory Module (SIMM)

18.3. 72 pin SIMM

18.4. 168 pin Dual Inline Memory Module (DIMM)

18.5. 184 pin DIMM

18.6. 240 pin DIMM

18.7. SO-DIMM

19. Memory Evolution and Future

19.1. Summary of SDRAM Memory Evolution

19.2. Memory Roadmap

19.2.1. DDR4 SDRAM Memory

19.2.2. LPDDR3 Memory vs. WideIO Memory

Chapter VI. Data Storage Devices


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1. Introduction

2. Magnetic Dives

2.1. Hard Disks

2.1.1. Components

2.1.2. Data Codification

2.1.3. Head Actuator Mechanism

2.1.4. CHS Geometry of Hard Disks

- Heads

- Cylinders and Tracks

- Sectors by Track

2.1.5. Types of Hard Disks and Auto Detection

2.1.6. Addressing Modes

- CHS Mode

- Large ou ECHS Mode

- LBA Mode

2.1.7. Methods to Address Sectors

- CHS Mode

- LBA Mode

2.1.8. BIOS Commands vs. ATA Commands

2.1.9. Evolution of Address Modes and ATA Drive Capacity Limitations

- CHS Mode - the 528 MB Barrier

- Bit-shift Geometric CHS Translation (ECHS Mode) - 8.4 GB Barrier

- LBA-assist Geometric CHS Translation - 8.42 GB Barrier

- Pure LBA – From 137 GB to 144 PB Barrier

2.1.10. Key Features of Hard Disks

2.1.11. Evolution of Hard Disks

2.2. Floppy Drive and Zip Drives

3. Optical Drives

3.1. CD

3.1.1. CD Construction and Technology

3.1.2. CD Formats

- CD-DA (CD Digital Audio), CD-ROM, CD-R and CD-RW

3.1.3. Write and Read Speed

3.1.4. CD Capacity

3.2. DVD

3.2.1. DVD Construction and Technology

3.2.2. DVD vs. CD


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3.2.3. DVD Capacity and DVD Record Time

3.2.4. Profiles of DVD Physical Formats

3.2.5. DVD Formats

- DVD-ROM, DVD-Video, DVD-Audio, DVD-R, DVD+R, DVD-RW, DVD+RW and DVD-RAM

3.2.6. Read and Write Speed

3.3. HD DVD

3.3.1. HD DVD History

3.3.2. Key Features of HD DVD

3.4. Blu-Ray Disc (BD)

3.4.1. BD History

3.4.2. Key Features of BD

3.4.3. Blu-Ray vs. DVD

3.4.4. BD - How it works

3.4.5. BD Layers

3.4.6. BD Layers vs. DVD Layers vs. CD Layers

3.4.7. BD Write/Read Speed vs. DVD Write/Read Speed vs. CD Write/Read Speed

3.4.8. BD Storage Capacity

3.4.9. Blu-Ray Key Features vs. HD DVD Key Features vs.e DVD Key Features

4. Magneto-Optical Drives

5. Flash Memory Devices

5.1. Proprieties of Flash Memory

5.2. Flash Memory Technologies

5.3. Memory Flash Devices vs. Magnetic Devices

5.4. Data Reliability in Flash Memory Devices

5.5. USB Flash Drives

5.5.1. Key Features

5.5.2. Storage Capabilities

5.6. Solid State Disks (SSD)

5.6.1. Construction

5.6.2. Types of Flash Memory Chips

5.6.3. Pages and Blocks

5.6.4. Access Time

5.6.5. Bandwidth

5.6.6. SSD Advantages

5.6.7. SSD Disadvantages

5.6.8. SSD vs. HDD


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5.6.9. SSD Prices

5.6.10. TRIM Command

5.6.11. SSD Optimization

5.6.12. Some Examples of SSD Storage

5.7. Types of Memory Cards

Chapter VII. Video System

1. Introduction

2. Video System Operation

3. Concepts

3.1. Pixel

3.2. Spatial Resolution

3.3. Chromatic Resolution

3.4. Colour Depth

3.5. Video Modes

3.6. Refresh Rate

4. Video Adapters

4.1. Video Adapters Role

4.2. Video Adapters Standards

4.3. Types of Video Adapters

4.4. Main Components of Video Adapter

4.4.1. Video BIOS

4.4.2. Graphic Processor

4.4.3. Video Memory

4.4.4. RAMDAC

4.5. Video Adapter Interfaces

4.5.1. System Interface

- PCI, AGP and PCI Express

4.5.2. Display Interface

- VGA, DVI, HDMI and DisplayPort

4.6. Video Adapters Evolution

5. CRT Monitors

5.1. Operation of CRT Monitors

5.2. Types of CRT Monitors

5.2.1. Monochromatic

5.2.2. Polychromatic

5.3. Dot vs. Pixel


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5.4. Technologies used to Manufacture CRT

5.4.1. Shadow Mask

5.4.2. Aperture Grille

5.5. Display Specifications

5.5.1. Display Size

5.5.2. Resolution Supported

5.5.3. Aspect Ratio

5.5.4. Vertical Refresh Rate

5.5.5. Horizontal Refresh Rate

5.5.6. Bandwidth

5.5.7. Dot Pitch vs. Stripe Pitch

6. LCD Monitors

6.1. LCD Monitors Operation

6.2. Types of LCD Monitors Technology

6.2.1. Passive Matrix

6.2.2. Active Matrix

6.3. Pixel Pitch

6.4. LCD Monitors Interface

6.5. CRT Monitors Advantages and Disadvantages vs. LCD Monitors Advantages and Disadvantages

Chapter VIII. RAID Technology

1. RAID Technology - How it works

2. RAID Technology History

3. RAID Technology Levels

3.1. RAID Level 0 - Striping

3.2. RAID Level 1 - Mirroring

3.3. RAID Level 0+1

3.4. RAID Level 1+0

3.5. RAID Level 3

3.6. RAID Level 5

3.7. JBOD

4. Failure Response

5. Modes of RAID Technology Implementation

5.1. By Software

5.2. By Firmware/Drivers

5.3. By Hardware


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6. Summary of RAID Levels Features

Chapter IX. Benchmark Tools

1. Introduction

2. Issues in Benchmark Tools

3. Concept of Benchmark

4. Utility of Benchmark Tools

5. Types of Benchmarks

5.1. Synthetic Benchmarks

5.1.1. Advantages

5.1.2. Disadvantages

5.2. Real Program

5.2.1. Advantages

5.2.2. Disadvantages

6. Examples of Benchmarks Tools

6.1. Bytemark

6.2. SiSoftware Sandra

6.3. Winstone

6.4. SPEC

7. Main SiSoftware Sandra Benchmarks

7.1. Processor Arithmetic

7.2. Processor Multi-Media

7.3. Multi-Core Efficiency

7.4. Memory Bandwidth

7.5. Cache & Memory

7.6. Memory Latency

Chapter X. Specification of Computer Hardware

1. PC Purchase

2. PC Assembly

3. PC Purchase with Component Specification

4. PC Upgrade

5. Classification of Hardware Components

6. Selection of Hardware Components

6.1. Case

6.2. Motherboard

6.3. Processor


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6.4. Main Memory

6.5. Video System

- Video Adapter and Monitor

6.6. Video Adapter

6.7. Monitor

6.8. Hard Disk

6.9. Optical Drives

7. Specification of Personal Computer Hardware

7.1. Strategy Specification

7.1.1. Identification of Minimal Requirements

7.1.2. Base Specification

7.1.3. Analysis and Evaluation of Proposals

8. Examples of Computer Hardware Ranges

8.1. Performance

8.2. Mainstream

8.3. Value

Chapter XI. Basic concepts about networks

1. Introduction to Data Networks

1.1. Definition of Data Network

1.2. Networks Classification

1.2.1. LAN - Local Area Network

1.2.2. MAN - Metropolitan Area Network

1.2.3. WAN - Wide Area Network

1.3. Network Advantages

1.4. Network Disadvantages

1.5. Network Components

1.6. Communication Modes

1.7. Types of Traffic

1.7.1. Voice

1.7.2. Data

1.8. Circuit Switching versus Packet Switching

1.8.1. Circuit Switching

- Advantages

- Disadvantages

1.8.2. Packet Switching


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- Advantages

- Disadvantages

- Datagram Mode

- Virtual Circuit Mode

1.9. Network Architecture

1.9.1. Layer

1.9.2. Protocol

1.9.3. Interface

2. The OSI Model

2.1. Layers

2.2.1 Physical

2.2.2 Data Link

- Physical Address - MAC address

2.2.3 Network

- Logical Address - IP address

2.2.4 Transport

2.2.5 Session

2.2.6 Presentation

2.2.7 Application

2.2. Host Layers vs. Network Layers

2.3. Layer Functions

2.4. Data Encapsulation

2.5. Peer-to-Peer Communication

2.6. Network Devices by Layers

3. The TCP/IP Model

3.1. Model Function

3.2. Description of the TCP/IP Model

3.2.1 Application Layer

- Principles of Application Layer Protocols

- HTTP and FTP Protocols

- Electronic Mail Protocols

- DNS Protocol

- DHCP Protocol

3.2.2 Transport Layer

- Transport-Layer Services and Principles

- Connectionless Transport - UDP Protocol

- Principles of Reliable Data Transfer


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- Connection-Oriented Transport - TCP Protocol

3.2.3 Network Layer

- Internet Protocol – IP Protocol

- Network Service Models

3.2.4 Data link Layer

- Media Access

- Topologies

3.3. TCP/IP Model versus OSI Model

4. Network Devices

4.1. Hubs

4.2. Bridges

4.3. Switches

4.4. Routers

5. Topologies

5.1. Bus

5.2. Star

5.3. Extended Star

6. Physical Means of Transmission

6.1. Copper

6.1.1. Coaxial Cable

6.1.2. UTP Cable

6.1.3. STP Cable

6.2. Optical Fiber

Chapter XII. IP Addressing

1. Introduction

2. IPv4 address structure

3. Binary-decimal and decimal-binary conversion

4. Address for different purposes

5. Address assignment

6. IPv4 addresses classification

7. Subnet address e subnet masks

8. Address and subnets calculations

9. Practical examples


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Demonstration of the coherence of the contents with the objectives/skills of the subject

The syllabus was designed to contribute to the acquisition of skills and objectives as follows:

Chapter I - Personal Computer (PC) Architecture (C1, C1.1, C2, C4)

Chapter II - Computer Buses (C1, C1.1, C2, C4)

Chapter III - Processors (C1, C1.1, C2, C4)

Chapter IV - Motherboards (C1, C1.1, C2, C4)

Chapter V - Memory (C1, C1.1, C2, C4)

Chapter VI - Data Storage Devices (C1, C1.1, C2, C4)

Chapter VII - Video System (C1, C1.1, C2, C4)

Chapter VIII - RAID Technology (C1, C1.1, C2, C4)

Chapter IX - Benchmark Tools (C1, C1.1, C2, C3.1, C4)

Chapter X - Specification of Computer Hardware (C1, C1.2, C2, C3, C4)

Chapter XI - Concepts about Networks (C1, C1.1, C2, C4)

Chapter XII - IP Addressing (C1, C1.1, C2, C4)

Teaching/Learning Methodology

Contact and Autonomous

The learning methodology is developed through the following components:

Classroom

1. Theoretical Classes

1.1 Presentation and exposition of the syllabus contents related with technology used by computer and network systems

1.2 Examples of technology implementation to real computer and network systems

1.3 Examples and exercise resolution to consolidate concepts related with IP addressing, occasionally using real scenarios ofcomputer networks

2. Practical and Laboratory Classes

2.1 Advice and guidance of students in the bibliographic research work

2.2 Handling and identification of components used by computers

2.3 Use, handling and identification of network cables and active network equipments

2.4 Achievement of 10 assembling laboratory projects (practical assignment), setup, identification, test and evaluation ofcomputer and networking technology, with the drafting of reports

3. Tutorial Orientation

3.1 Tutorials in small groups to aid the learning process and clarify any doubts

3.2 Provide an opportunity for students to exchange ideas with their tutors, about the bibliographic research work

3.3 Advice and guidance within the context of the autonomous preparation of laboratory projects.


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Autonomous Learning

1. Study

1.1 Reading of books, notes, excerpts and assessment tests from the course recommended reading list

1.2 Assessment tests resolution

1.3 Preparation of practical laboratory work

1.4 Resolution of extra exercises about IP addressing

2. E-learning

2.1 Usage of studying elements made available by the teachers

Specific Resources

1. Theoretical classes- regular classroom with a multimedia projector

2. Practical and laboratory - hardware laboratory and network laboratory

3. Tutorial - teacher's office, regular classroom or hardware laboratory

4. Specific Hardware – cases, power supplies, motherboards, processors, memory modules, video adapters, magnetic harddisks, CD-ROM readers, DVD readers, network interface cards, floppy drives, monitors, routers, hubs, switches

5. Web platform for educational contents (Moodle)

Demonstration of the coherence of the teaching/learning methodology with the objectives/skills of the subject

The teaching methods used were defined in order to contribute to the competencies set for the course as follows:

Classroom

1. Theoretical Classes

1.1 Presentation and exposition of the syllabus contents related with technology used by computer and network systems(C1, C1.1, C2, C2.1, C3, C4, C4.1, C4.2)

1.2 Examples of technology implementation to real computer and network systems (C1, C1.1, C2, C2.1, C3, C4, C4.1, C4.2)

1.3 Examples and exercise resolution to consolidate concepts related with IP addressing, occasionally using real scenarios ofcomputer networks (C4, C4.1, C4.2, C4.4)

2. Practical and Laboratory Classes

2.1 Advice and guidance of students in the bibliographic research work (C5, C6, C8, C9)

2.2 Handling and identification of components used by computers (C1.1, C1.2, C2.1)

2.3 Use, handling and identification of network cables and active network equipments (C2.1, C4.1, C4.3, C4.4)

2.4 Achievement of 10 assembling laboratory projects (practical assignment), setup, identification, test and evaluation ofcomputer and networking technology, with the drafting of reports (C1.1, C1.2, C1.3, C2.1, C2.2, C3.1, C4.1, C8, C9)

3. Tutorial Orientation

3.1 Tutorials in small groups to aid the learning process and clarify any doubts (C7, C8, C9)


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3.2 Provide an opportunity for students to exchange ideas with their tutors, about the bibliographic research work (C5, C6,C7, C8, C9)

3.3 Advice and guidance within the context of the autonomous preparation of laboratory projects (C6, C7, C10, C11)

Autonomous Learning

1. Study

1.1 Reading of books, notes, excerpts and assessment tests from the course recommended reading list (C1, C1.1, C2, C2.1,C3, C4, C4.1, C4.2, C7, C8, C9)

1.2 Assessment tests resolution (C1, C1.1, C2, C2.1, C3, C4, C6, C7, C8, C9)

1.3 Preparation of practical laboratory work (C6, C7, C8, C9, C10, C11)

1.4 Resolution of extra exercises about IP addressing (C4.2, C4.4, C6, C7)

2. E-learning

2.1 Usage of studying elements made available by the teachers (C7)

Assessment


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Description

The methods of assessment of knowledge and skills are:

CONTINUOUS EVALUATION:

- An individual written test (WT) with a minimum of 9.5

- A bibliographic research work (BR) and ten laboratory projects (LP) with the drafting of reports, with a global minimum of9.5

Final: 50%*WT+50%*(BR + LP)

FINAL EVALUATION:

- An individual written test (WT) with a minimum of 9.5

- A practice test (PT) with a minimum of 9.5

Final: 50%*WT + 50%*PT

Note: The student obtains approval in the course if he has a final grade equal or greater than 10.

Number of Evaluations

Continuous/Periodic 12

Final 2

Bibliography

Main

“Tecnologia dos Equipamentos Informáticos”, Rui Vasco Monteiro, Filipe Neves, João Pereira, Nuno Rodrigues eRicardo Martinho; 1ª Edição, FCA – Editora de Informática, 2004“Upgrading and Repairing PCs”, 20th Edition, Scott Mueller, Que, 2011“Computer Networks, 5th Edition, Andrew S. Tanenbaum, Prentice Hall International, 2010Slides, Texts and Notes of the Course Unit provided by the Professor

Complementary

“Building the Perfect PC”, 3rd Edition, Robert Thompson, Barbara Thompson, O’Reilly, 2010“Redes de Computadores - Curso Completo, 7ª Edição Revista e Actualizada, José Gouveia, Alberto Magalhães, FCA -Editora de Informática, 2009“Inside the Machine: An Illustrated Introduction to Microprocessors and Computer Architecture”, 1st Edition, JonStokes, No Starch Press, 2007“Computer Architecture: A Quantitative Approach”, 5th Edition, John L. Hennessy, David A. Patterson, Morgan


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Kaufmann, 2011“Computer Organization and Design, Revised Fourth Edition: The Hardware/ Software Interface”, 4rd Edition, David A.Patterson, John L. Hennessy, Elsevier/Morgan Kaufmann, 2011“The Complete PC Upgrade & Maintenance Guide”, 16th Edition, Mark Minasi, Sybex, 2005“The Indispensable PC Hardware Book”, 4th Edition, Hans Peter Messmer, Addison–Wesley, 2001

Approval

Approved by CTC in : 06-01-2012


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