Research ArticleEmulator Based on Switching Functions for a Dual InterleavedBuck-Boost Converter

Marco Antonio Sánchez Vázquez , Ismael Araujo-Vargas , and Kevin Cano-Pulido

National Polytechnic Institute, Higher School of Mechanical and Electrical Engineering Culhuacan, 04430, Mexico

Correspondence should be addressed to Marco Antonio Sanchez Vazquez; ingmarcosanchezv80@gmail.com

Received 15 March 2019; Revised 14 June 2019; Accepted 3 July 2019; Published 4 August 2019

Academic Editor: Zhan Shu

Copyright © 2019 Marco Antonio Sanchez Vazquez et al. This is an open access article distributed under the Creative CommonsAttribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work isproperly cited.

Under the unavailability of some components of a complex system, the Hardware In the Loop (HIL) tool allows the emulation ofother subsystems. When these devices are not available, a customized emulator can be developed based on the Piecewise LinearModel (PWLM) and a numerical method for solving the differential equations system. However, these implementations require theuse of a Field Programmable Gate Array (FPGA) with extensive hardware resources. In this article we propose the use of switchingfunctions for the modeling of power converters of a Hybrid Power System (HPS), allowing the reduction of hardware resourcesof the FPGA, and the number of steps per switching cycle is increased. The results are compared with SABER simulations and aPWLM evaluated with the Euler method.

1. Introduction

Frequently during the development of a complex systemthere are multiple subsystems under study; this represents achallenge for the rapid evolution of large projects. With thehelp of an emulator, multiple components can be developedquickly and efficiently; these tools are called Rapid ControlPrototyping (RCP) or HIL. The HIL simulation is a formof simulation of real time; its initial use was in flightsimulators and in missile guides, and nowadays its use hasbeen extended to power electronics [1].HILs are based on twotechnologies: microprocessors and FPGA. The disadvantageof the microprocessor-based emulators is that sequentiallogic would require clocks of the order of 1012Hz to matchthe FPGA concurrence with clocks of the order of 106Hzthat would perform the same number of operations [2]. Theapplications in power electronics are the development of thetrain power system [3], ships [4], electric vehicles [5, 6],and microgrids [7–9], achieving in the best of cases a stepsize of the order of 10ns, if the numerical representation issufficiently accurate to reduce the error by truncation.

It is observed that the development of a HIL requiresthe mathematical model that describes the behaviour ofthe system; that in the case of power converters refers to

the equations that solve the electrical network. The hard-ware resources of the FPGA depend on the model to beimplemented, the synthesis procedure, and the format of thearithmetic: in Fixed Point (FXP) or Floating Point (FP). In[10] to model an NPC converter, the network equations weredescribed with the Modified and Augmented Node Analysis(MANA), obtaining the state equations. In [11] to model athree-phase inverter, the network equations were describedunder the Associated Discrete Circuit (ADC). In [12] theaverage value method was used to calculate the output valueof a three-phase interleaved converter. In [3, 13–19], equationsare used in the state space to describe the behaviour ofdifferent topologies of power converters. However, in orderto be implemented, an FPGA with wide range of resourcesis required; around 65000 Look Up Tables (LUT) to obtaina step size of the order of 5ns, in some cases multiplexarithmetic operations can reduce the size between 15000 and6000 LUT, with a cost of increasing the step size to 250 ns [18]

In this article, the model based on Switching Functions(SF) for a Dual Interleaved Buck-Boost Converter (DIBBC)with interphase transformer (IPT) was developed, and thehardware implementation was made for an FPGA of limitedresources. Likewise SABER simulations results were com-pared with a PWLM and this proposal. It was observed

HindawiMathematical Problems in EngineeringVolume 2019, Article ID 5930548, 10 pageshttps://doi.org/10.1155/2019/5930548

2 Mathematical Problems in Engineering

Q1

Q2

D1

D2

L1 L2

LCOM

C RS

g2

g1

IPT

vS

vLCOM

vL1vL2

vO

vDIFF

A

B

COM

GND

iS

iQ1

iQ2

iL1 iL2

iLCOM

iC iO

iD

iD1

iD2

Figure 1: Scheme of a Dual Interleaved Buck-Boost Converter (DIBBC).

that the difference between models is minimal; however, inthe hardware implementation the difference is drastic. Inaddition, it was noted that the step size is only restricted tothe core speed of the FPGA.

2. Switching Functions Model for DIBBC

2.1. The DIBBC. Figure 1 shows the diagram of a DIBBCcomposed of a DC voltage source, VS, a switch bridge Q1, Q2,D1, D2, an (IPT) that includes L1 and L2 where L1 = L2, acommon inductor 𝐿COM, an output capacitor C, and a loadR [20].

2.2. Operation Principle. The circuit operates under the stateof transistors Q1 and Q2, presenting two possible permanentstate operation regions: D < 0.5 and D > 0.5; the mainwaveforms are depicted in Figure 2, in (a) - (k) correspondingto D < 0.5 and in (l) - (v) to D > 0.5. In (a) and (l) the signalsof the states of the transistors Q1 and Q2 and VG1 and VG2 areobserved for the fixed frequency (1/T) and a phase shiftedbetween them of T/2 and a balanced duty cycle, D. (b) and(m) show the voltages in the nodes VAG and VBG. In (c) and(n) is the differential voltage VAB = VAG - VBG. VAB producesthe current in the differential inductor 𝑖𝐿DIFF or IPT (d) and(o). (e) and (p) correspond to the voltage in the commoninductor V𝐿COM. The currents in the common inductor 𝑖𝐿COMare shown in (f) and (q), the currents in L1 and L2 are (g) and(h), and the currents in diodes 𝑖𝐷1 and 𝑖𝐷2 are shown in (h)and (s). The currents of Q1 and Q2 are shown in (i) and (v).The currents 𝑖𝐷 in (j) and (u) are the sum of the currents indiodesD1 and D2, and the current in the capacitor in (k) and(v).

Figure 3 shows the nine possible configurations of theDIBBC. The configurations from I to IV, Figures 3(a)–3(d),correspond to Continuous Current Mode (CCM), the other

five configurations are presented in the DCM, and theDiscontinuous Current Mode (DCM) configurations V to IXare shown in Figures 3(e)–3(i); the DCM occurs when i𝐿1 = 0or i𝐿2 = 0; under these conditions i𝐷1 = 0 or i𝐷2 = 0.

2.3. Switching Functions Model for a DIBBC. In each config-uration of the circuit, the voltages of the nodes VAB and VBG,which depend only on V𝑆 and V𝑂, can be established by theproduct of

k𝐻 = 𝑀𝑉k𝑆 (1)

The vectors k𝐻 are the voltages in the VAG and VBG nodes:[VAG VBG]T, and the vector k𝑆 is the supply voltage V𝑆 andthe capacitor voltage V𝑂: [V𝑆 V𝑂]T. 𝑀V is a transformationmatrix for each configuration that is called Voltage SwitchingMatrix. For the currents of transistors Q1 and 𝑄2 there isa current vector i𝑄: [𝑖𝑄1 𝑖𝑄2]T, and for the currents of thediodes, i𝐷 is [i𝐷1 i𝐷2]T. The current vector of the inductorsi𝐿 is [𝑖𝐿1 𝑖𝐿2]T; after i𝐿, i𝑄, and i𝐷 it can be obtained throughthe Current Switching Matrices M𝐼𝑄 and M𝐼𝐷 shown in (2)and (3), respectively. Equation (1) is called voltage switchingfunction (FSWv) and (3) is called current switching function(FSWi):

i𝑄 = 𝑀𝐼𝑄i𝐿 (2)

i𝐷 = 𝑀𝐼𝐷i𝐿 (3)

Table 1 shows the M𝑉 and M𝐼𝐷 matrices for each configu-ration of the circuit; it indicates that the conditions for eachconfiguration are presented and shade the configurations ofthe CCM.M𝑄 is excluded because at the moment it is not ofinterest for this work.

The current in 𝐿COM can be divided into two when apply-ing the superposition principle: the current that produces the

Mathematical Problems in Engineering 3

vg1(t)

vg2(t)

vAG (t)vBG(t)

TT/2

DT (1-D)T (1-D)T

TT/2

DT

Configuration I III II III IIII

VS

VS

VO VO

VS+VO VS+VO

VS+VO

VS

VS+VO

vLDIFF(t)

iLDIFF(t) iLDIFF

(t)

iLDIFF

vLCOM(t) (VS -VO)/2 (VS -VO)/2

VO

ILCOM ILCOMΔiLCOMΔiLCOM

iLCOM(t)

iL1(t)

iL2(t)

iL1=iLDIFF

+iLCOM /2iL2

=-iLDIFF+iLCOM

/2iL1

=iLDIFF+iLCOM /2

iL2=-iLDIFF

+iLCOM/2

ILCOM/2 ILCOM

/2

IPh IPh

ΔiPh ΔiPh

IO IO

iD = iD1 + iD2

iD = iD1 + iD2

iC = iD - iO

iC = iD - iO

iD1(t)

iD2(t)

iQ1(t)

iQ2(t)

iD(t)

iO(t) iO(t)

t

t

t

t

t

t

t

t

t

t

t t

t

t

t

t

t

t

t

t

t

t

IV I IV IVII IConfiguration

D < 0.5 D > 0.5

(a)

(b)

(c)

(d)

(e)

(f )

(g)

(h)

(i)

(j)

(k)

(l)

(m)

(n)

(o)

(p)

(q)

(r)

(s)

(t)

(u)

(v)

IPh IPh

ΔiPh ΔiPh

Δ iLDIFFΔ

vg1(t)

vg2(t)

vAG (t)vBG(t)

vLDIFF(t)

vLCOM(t)

iLCOM(t)

iL1(t)

iL2(t)

iD1(t)

iD2(t)

iQ1(t)

iQ2(t)

iD(t)

Figure 2: Steady-state waveforms of the DIBBC.

4 Mathematical Problems in Engineering

Q1 = ON, Q2 = OFF, iL2 > 0

Q 1Q 2

D 1D 2

L1 L2

LCOM

C RS

IPT

vS

vLCOM

vL1vL2

vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Configuration I

(a)

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Q1 = OFF , Q2 = ON, iL1 > 0

Configuration II

LCOMvLCOM

(b)

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Q1 = OFF, Q2 = OFF, iL1 > 0, iL2

> 0

Configuration III

LCOMvLCOM

(c)

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Q1 = ON, Q2 = ON

Configuration IV

LCOMvLCOM

(d)

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Q1 = ON, Q2 = OFF, iL2 = 0

Configuration V

LCOMvLCOM

(e)

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Q1 = OFF, Q2 = ON, iL1 = 0

Configuration VI

LCOMvLCOM

(f)

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Q1 = OFF, Q2 = OFF, iL2 = 0

Configuration VII

LCOMvLCOM

(g)

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Q1 = OFF, Q2 = OFF, iL1 = 0

Configuration VIII

LCOMvLCOM

(h)

Q1 = OFF, Q2 = OFF, iL1 = 0, iL2 = 0

Q 1Q 2

D 1D 2

L1 L2 C RS

IPT

vSvL1

vL2vO

vDIFFA

B

COM

GND

iS

iQ1

iQ2

iL1iL2

iLCOM

iC iO

iDiD1

iD2

Configuration IX

LCOMvLCOM

(i)

Figure 3: DIBBC configurations.

voltage in node A: V𝐿COMA and the current that producesthe voltage in node B: V𝐿COMB. The voltages in CCM for𝐿COMA, 𝐿COMB, L1, and L2, are given by (4), (5), (6), and (7),respectively, and are obtained from the node analysis betweenA, B, COM, and GND of the circuit of Figure 1, for which L1= L2 must be considered.

V𝐿COMA= 12V𝐴𝐺 (4)

V𝐿COMA= 12V𝐵𝐺 (5)

V𝐿1 =12 (VAG − VBG) (6)

V𝐿2 =12 (VBG − VAG) (7)

In DCM the voltages in 𝐿COMA, 𝐿COMB, L1, and L2 are givenby (8), (9), (10), and (11), respectively:

V𝐿COMA= 𝐿COM𝐿 + 𝐿COM V𝐴𝐺 (8)

V𝐿COMB= 𝐿COM𝐿 + 𝐿COM V𝐵𝐺 (9)

V𝐿1 =𝐿

𝐿 + 𝐿COM (VAG − VBG) (10)

V𝐿2 =𝐿

𝐿 + 𝐿COM (VBG − VAG) (11)

Equations (4) to (11) are the interactions in the voltage in theinductor network between nodes A, B, COM, and GND, andthey are called XFRMv. The network of inductors is formedby an interphase transformer (IPT) with the branches L1 and

Mathematical Problems in Engineering 5

Table 1: Voltage switching function in A and B nodes and current switching function in diodes 1 and 2.

Configuration Q 2 Q 1 vAG vBG MV iQ1 i i i MID

I 0 1 vS -vO1 00 −1

i 0 0 i 0 00 1

II 1 0 -vO vS0 −11 0

0 i iL1 0 1 00 0

III 0 0 -v

-v

O -vO0 −10 −1

0 0 iL1 i 1 00 1

IV 1 1 vS vS1 01 0

i i 0 0 0 00 0

V 0 1 vS 0 1 00 0

i 0 0 0 0 00 0

VI 1 0 0 vS0 01 0

0 i 0 0 0 00 0

VII 0 0 O 0 0 −10 0

0 0 i 0 1 00 0

VIII 0 0 0 -vO0 00 −1

0 0 0 i 0 00 1

IX 0 0 0 0 0 00 0

0 0 0 0 0 00 0

Q2 D1 D2

L1 L2

L2

L2

L1 L2

L1

L2

L1

L2

L2 and a common inductor, 𝐿COM, the current proper to theIPT i𝐿𝑆 is obtained by means of (12) where kL is the vector[VL1 VL2]T and L−1 is the inverse matrix of the inductances ofthe transformer and iLS is the vector [𝑖𝐿𝑆1 𝑖𝐿𝑆2]T.

i𝐿𝑆 = 𝐿−1 ∫ k𝐿𝑑𝑡 (12)

𝑖LCOMA and 𝑖LCOMB are given by (13) and (14), respectively,

𝑖LCOMA= 1LCOM∫ VLCOMA

𝑑𝑡 (13)

𝑖LCOMB= 1LCOM∫ VLCOMB

𝑑𝑡 (14)

The currents i𝐿1 and i𝐿2 are given in (15) and (16), respectively.This set of equations are the interaction of the currents in theinductor network and are called XFRMi:

𝑖𝐿1 = 𝑖𝐿𝑆1 + 𝑖𝐿COMA(15)

𝑖𝐿2 = 𝑖𝐿𝑆2 + 𝑖𝐿COMB(16)

In the DCM, L1 and L2 stop behaving like a transformer andbecome an inductor when leaving one of its branches at highimpedance, so we can do v𝐿1 = v𝐿2 = 0. Observing the setsof (4) and (8), (5) and (9), (6) and (10), and (7) and (10), wehave the common factors VAG, VBG, VAG-VBG, and VBG-VAG,respectively, and we can summarize (4) to (11) in Table 2,where we have the common factor for each inductor voltageand GXFRMV gain factor.

The balance of the current 𝑖D is described by (17) and (18);(17) corresponds to the current coming from diodes D1 andD2 and (18) corresponds to the current injected into the RCoutput network.

𝑖D = 𝑖D1

+ 𝑖D2(17)

𝑖D = 𝑖C + 𝑖R (18)

Table 2: XFRMV factors.

CCMGXFRMV

(Config. I to IV)

DCMGXFRMV

(Config. VI to IX)Common factor

VLCOMA

12

LCOML + LCOM VAG

VLCOMB

12

LCOML + LCOM VBG

VL112 0 VAG − VBG

VL212 0 VBG − VAG

If 𝑖R = VO/R and 𝑖C = C(dVo/dt) are substituted in (18) andthe equation is reordered, then (19) is obtained:

dV𝑜dt= 𝑖D

C− VORC

(19)

If (19) is integrated, (20) is obtained, which would be theexpression for modeling the output voltage VO

VO = 1C ∫ 𝑖Ddt −1RC∫ VOdt (20)

Equations (1) to (20) and Tables 1 and 2 describe the systemmodel; if you see each equation as a function of input outputyou can build a block diagram. This diagram is shown inFigure 4.

2.4. System Discretization. The system of Figure 4 is inthe time domain; the Laplace transform must be appliedto convert it to the domain of the complex variable 𝑠. Inthis diagram, with the exception of the integrators, all arearithmetic operators or gains, so the discretization consistedof replacing the integrators with discrete integrators of theblock diagram. The discrete integrator that was used in this

6 Mathematical Problems in Engineering

CONFIGURATIONSELECTOR

FSWV XFRMV

1LCOM

L-1FSWIXFRMI

1C

1RC

+-

QQiL

vS

1

2

vO vHvL iL

iLS iDvO

MUXMV

MUXMI

MUXGXFRM

CFG

CGFCGFCGF

iD

vLCOM iLCOM

∫

∫∫∑

Figure 4: Block diagram of the DIBBC described by switching functions.

work has a delay physically feasible, and the transfer functionof integration is given in equation (21):

𝐻(𝑠) = 1𝑠 (21)

Equation (21) is discretized by applying the 𝑧-transform,obtaining the transfer function of an integrator shown in (22),where 𝑇𝑆 is the sampling period:

𝑧 [1𝑠 ] =𝑇𝑆1 − 𝑧−1 (22)

Equation (22) corresponds to an integrator without delay; anintegrator with delay according to the delay theorem of the ztransform is shown in

𝐻(𝑧) = 𝑇𝑠𝑧−1

1 − 𝑧−1 (23)

In Figure 5 a block diagramof the discretemodel of the circuitof Figure 1 is shown.

3. Hardware Implementation

For implementation there is a card with a low-end FPGAAltera Cyclone IV E model EP4CE22F17C6N with 22320LUT. The manufacturer provides the tool to develop systemscalled Quartus Prime, which allows the implementation oflogic and arithmetic, in two languages of hardware descrip-tion: VHDL and Verilog.

3.1. Arithmetic. Using the tool for IP development (Intellec-tual Property) of Quartus Prime called LPM Mega Wizard,the additions, subtractions, and multiplications of the modelof Figure 4 were implemented. It was decided to use fixedpoint arithmetic with the format Q (64.32), having 32 bitsfor the integer part and 32 for the fractional part. Theadvantage of using fixed point is that the implementationin hardware does not require sequential operations andallows all operations to be performed concurrently. The

decision to use the fixed point format was made taking intoaccount the dynamic range of the signals and the error ofthe representation of the constants of the system. With thisformat, the truncation error of the representation of theconstants is less than 0.0005%. In Results, an error analysiswill be shown over time.

3.2. Switching Functions. Only in the case that there aretwo possible states such as that of the switches, in hardwareyou can replace that switch represented by a product in theswitching function by a multiplexer, like the functions of(1) to (3). Figure 6 shows how the switching function wasimplemented. It is observed that the products are replacedby multiplexers, which are controlled by the configurationmultiplexers, which allow the input of the coefficients of themX mn switching matrices. A 64-bit multiplier in hardwarefor the CYCLONE IV occupies a space of 4352 LUT, whilea 64-bit multiplexer occupies only 64 LUT, which representsa reduction of 68 times the hardware space.

4. Results

Four simulations were carried out, the first using a simulatorfor physical systems, which in this case was SABER 2.4,the second simulation using PWLM evaluated by the Eulermethod in MatLAB 2015a, the third being the switchingfunctions using a SIMULINK 2015a model and evaluatedby the Euler method, and the fourth being the embeddedmodel of the switching functions with the RTL simulationtool included in Quartus Prime 18.00. Table 3 shows thevalues of the simulation parameters. SABER is a very accuratesimulator so it will be the reference to calculate the error.The state variables of the PWLM are 𝑖𝐿1, 𝑖𝐿2, and V𝑂, so thegraphs for them are displayed. Figures 7, 8, and 9 show theresults of the simulations for the time from 0 ms to 10 ms:(a) corresponds to the four simulations, (b) corresponds tothe error of the PWLM, the SF evaluated in SIMULINK, andSF evaluated by the FPGA all with respect to SABER, (c) isa zoom between 9.50 ms to 9.55 ms, and (d) is a zoom of the

Mathematical Problems in Engineering 7

CONFIGURATION

SELECTOR

FSWV XFRMV

TSLCOM

TSL-1

FSWIXFRMI

TSC

TS

RC

+-

Q1Q2iL

vS

vO vHvL

vLCOM

iLiLS

iLCOM

iD

MUXMV

MUXMI

MUXGXFRM

CFG

CGFCGFCGF

iD++

++ z-1

z-1

++ z-1 vO

FS

FS

FS

FS

∑

Figure 5: Discrete model of a DIBBC.

i1

zero

i2o1

o2

m1_11m2_11

mn_11

m1_12m2_12

mn_12

m1_21m2_21

mn_21

m1_22m2_22

mn_22

CFG

Switc

hing

Mat

rix C

oeffi

cien

ts

Inpu

t Vec

tor

Out

put V

ecto

r

ProductMultiplexers

MatrixMultiplexers

Figure 6: Hardware implementation for a switching function.

error for the interval of (c).When the system is in steady stateit is observed that the errors between the SFs overlap withoutdiverging. The error for 𝑖𝐿1 at t = 9.526 ms for the PWLM isunder 1.09%, for both SFs it is 1.22%, the error for 𝑖𝐿2 at t =9.526ms for PWLM is 0.83%, and for SFs it is 0.63%; the errorfor V𝑂 at t = 9.526 ms for PWLM is 0.45% and for SFs it is

Table 3: Simulation parameters.

Parameter Value𝑉𝑠 350 V𝐹𝑠𝑤 75 kHz𝐹𝑠𝑡 150 MHz𝐷 45%𝑅 4Ω𝐿 38 𝜇H𝐿com 7 𝜇H𝐶 95 𝜇F

0.44%. It should be noted that the circuit enters the DCM intwo regions: when the circuit is turned on at t = 0s and duringthe transient in the interval t = 159𝜇s to t = 413𝜇s. The systemreaches the steady state at t = 3.5 ms.

In terms of hardware implementation, a PWLM for theDIBBC would occupy a space of 79552 LUT in a CycloneIV. In the case of the switching function model it deals with9738 LUT (43.63% of the resources of the available card),depending on the Quartus Prime synthesis reports. Otherembodiments were made for the PWLM by multiplexing themultipliers: one was multiplexing one row of equation andanother was multiplexing rows of matrix. The results areshown in Table 4.

5. Discussion

In order to implement a HIL based on a PWLM whosestep size is less than 10 ns in an FPGA, extensive hardwareresources are required. It is observed that when using amodelbased on switching functions and fixed point arithmetic witha high resolution, the space in hardware for its implemen-tation is drastically reduced, allowing the use of a FPGAwith few resources and with accuracy similar to that of otherimplementations and the step size is restricted to the corespeed of the FPGA. This implementation is intended to beused for the development of a hybrid power system, since it

8 Mathematical Problems in Engineering

SABERPWLMSW SLSW FPGA

1 2 98 100 54 6 73Time [ms]

0100200300400500600

Curr

ent [

A]

(a)

1 2 3 4 5 6 7 8 9 100Time [ms]

PWLMSW SLSW FPGA

10−10

10−5

100

105

erro

r [%

]

(b)

9.510 9.530 9.5409.5209.505 9.5159.500 9.525 9.545 9.5509.535Time [ms]

405060708090

Curr

ent [

A]

SABERPWLMSW SLSW FPGA

(c)

9.505 9.510 9.515 9.520 9.525 9.530 9.535 9.540 9.545 9.5509.500Time [ms]

PWLMSW SLSW FPGA

10−3

10−2

10−1

100

101

erro

r [%

]

(d)

Figure 7: Analysis of the error of 𝑖𝐿1 between SABER and PWLM, SF Simulink and SF FPGA.

1 2 3 4 5 6 7 8 9 100Time [ms]

SABERPWLMSW SLSW FPGA

0100200300400500600

Curr

ent [

A]

(a)

1 2 3 4 5 6 7 8 9 100Time [ms]

PWLMSW SLSW FPGA

10−10

10−5

100

105

erro

r [%

]

(b)

405060708090

Curr

ent [

A]

9.505 9.510 9.515 9.520 9.525 9.530 9.535 9.540 9.545 9.5509.500Time [ms]

SABERPWLMSW SLSW FPGA

(c)

9.505 9.510 9.515 9.520 9.525 9.530 9.535 9.540 9.545 9.5509.500Time [ms]

PWLMSW SLSW FPGA

10−3

10−2

10−1

100

101

erro

r [%

]

(d)

Figure 8: Analysis of the error of 𝑖𝐿2 between SABER and PWLM, SF Simulink and SF FPGA.

Mathematical Problems in Engineering 9

0100200300400500600

Volta

ge [V

]

1 2 3 4 5 6 7 8 9 100Time [ms]

SABERPWLMSW SLSW FPGA

(a)

1 2 3 4 5 6 7 8 9 100Time [ms]

PWLMSW SLSW FPGA

10−4

10−2

100

102

erro

r [%

]

(b)

284

285

286

287

288

Volta

ge [V

]

9.505 9.510 9.515 9.520 9.525 9.530 9.535 9.540 9.545 9.5509.500Time [ms]

SABERPWLMSW SLSW FPGA

(c)

9.505 9.510 9.515 9.520 9.525 9.530 9.535 9.540 9.545 9.5509.500Time [ms]

PWLMSW SLSW FPGA

10−1

100

erro

r [%

]

(d)

Figure 9: Analysis of the error of V𝑂 between SABER and PWLM, SF Simulink and SF FPGA.

Table 4: Comparison between different implementation strategies.

Implementation Sampling Frequency Number of steps perswitching cycle FSa/FSW Multipliers Resources FPGA

(CYCLONE 4 22K)PWLMmultipliermultiplexed in equationrow

52.5 MHz 700 3 14.67%

PWLMmultiplexermultiplexed in matrix row 105 MHz 1400 9 89.60%

SFM 150 MHz 2000 5 43.63%

is required to embed in a FPGA the models of several powerconverters, sources, and loads. This implementation can beextended for use inmicrogrids.The switching functions allowseeing in the systems how the flow of the power is in anatural way so that the power balance does not require avery complex mathematical description that increases thehardware resources of a HIL.

Data Availability

The simulation data used to support the findings of this studyare available from the corresponding author upon request.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

Acknowledgments

The authors acknowledge to the Instituto PolitecnicoNacional (IPN) Mexico, for its facilities where it has beenpossible to carry out this work, Comision de Operacion yFomento de Actividades Academicas of the IPN (COFAA),for its financial support for the publication of this researcharticle, and the Universidad Autonoma de Chihuahua(UACH) Mexico, for academic support granted for therealization of this research.

References

[1] C. Buccella, C. Cecati, and H. Latafat, “Digital control ofpower converters—a survey,” IEEE Transactions on IndustrialInformatics, vol. 8, no. 3, pp. 437–447, 2012.

[2] F. Ji, H. Fan, and Y. Sun, “Modelling a FPGA-based LLC con-verter for real-time hardware-in-the-loop (HIL) simulation,” in

10 Mathematical Problems in Engineering

Proceedings of the 8th IEEE International Power Electronics andMotion Control Conference (IPEMC-ECCE Asia ’16), pp. 1016–1019, IEEE, China, May 2016.

[3] C. Liu, R. Ma, H. Bai, Z. Li, F. Gechter, and F. Gao, “Hybridmodeling of power electronic system for hardware-in-the-loopapplication,” Electric Power Systems Research, vol. 163, pp. 502–512, 2018.

[4] M. Milton, A. Benigni, and J. Bakos, “System-level, FPGA-based, real-time simulation of ship power systems,” IEEETransactions on Energy Conversion, vol. 32, no. 2, pp. 737–747,2017.

[5] L. Herrera, C. Li, X. Yao, and J. Wang, “FPGA-based detailedreal-time simulation of power converters and electric machinesfor EV HIL applications,” IEEE Transactions on Industry Appli-cations, vol. 51, no. 2, pp. 1702–1712, 2015.

[6] J.-M. Timmermans, J. Van Mierlo, P. Lataire, F. Van Mulders,and Z. McCaffree, “Test platform for hybrid electric powersystems: development of a HIL test platform,” in Proceedings ofthe European Conference on Power Electronics and Applications(EPE ’07), Denmark, September 2007.

[7] Z. Jiang, R. A. Dougal, R. Leonard, H. Figueroa, and A. Monti,“Hardware-in-the-loop testing of digital power controllers,” inProceedings of the 21st Annual IEEE Applied Power ElectronicsConference and Exposition (APEC ’06), pp. 901–906, IEEE, USA,March 2006.

[8] H. Li, M. Steurer, K. Shi, S. Woodruff, and D. Zhang, “Devel-opment of a unified design, test, and research platform forwind energy systems based on hardware-in-the-loop real-timesimulation,” IEEE Transactions on Industrial Electronics, vol. 53,no. 4, pp. 1144–1151, 2006.

[9] P. Vlado, A. Evgenije, G. Stevan, V. Marko, and R. Milan,“Precise PV active power - converter control rapid prototypingframework,” in Proceedings of the 19th International Symposiumon Power Electronics (Ee ’17), pp. 1–6, Serbia, October 2017.

[10] F. Montano, T. Ould-Bachir, and J. P. David, “An evaluationof a high-level synthesis approach to the FPGA-based sub-microsecond real-time simulation of power converters,” IEEETransactions on Industrial Electronics, vol. 65, no. 1, pp. 636–644,2018.

[11] M. Dagbagi, A. Hemdani, L. Idkhajine, M. W. Naouar, E.Monmasson, and I. Slama-Belkhodja, “ADC-based embeddedreal-time simulator of a power converter implemented in alow-cost FPGA: application to a fault-tolerant control of agrid-connected voltage-source rectifier,” IEEE Transactions onIndustrial Electronics, vol. 63, no. 2, pp. 1179–1190, 2016.

[12] R. Kang, S. Kim, I. Yang, K. Jeong, C. Kang, and G. Kim, “Theuse of FPGA in HIL simulation of three phase interleaved DC-DC converter,” in Proceedings of the IEEE Vehicle Power andPropulsion Conference (VPPC ’12), pp. 772–776, IEEE, Republicof Korea, October 2012.

[13] H. Kidokoro andM. Nakahara, “FPGA-based hardware-in-the-loop simulator of high switching frequency power converters,”in Proceedings of the IEEE International TelecommunicationsEnergy Conference (INTELEC ’15), IEEE, Japan, October 2015.

[14] C. Dufour, H. Blanchette, and J. Belanger, “Very-high speedcontrol of an FPGA-based finite-element-analysis permanentmagnet synchronous virtualmotor drive system,” inProceedingsof the 34th Annual Conference of IEEE Industrial Electronics, pp.2411–2416, IEEE, Orlando, Fla, USA, November 2008.

[15] P. Le-Huy, S. Guerette, L. A. Dessaint, and H. Le-Huy, “Real-time simulation of power electronics in power systems usingan FPGA,” in Proceedings of the 2006 Canadian Conference

on Electrical and Computer Engineering, pp. 873–877, IEEE,Ottawa, Canada, May 2006.

[16] C. Liu, R.Ma,H. Bai, F. Gechter, and F.Gao, “Anew approach forFPGA-based real-time simulation of power electronic systemwith no simulation latency in subsystem partitioning,” Interna-tional Journal of Electrical Power & Energy Systems, vol. 99, pp.650–658, 2018.

[17] S. Ben Said, K. Ben Saad, and M. Benrejeb, “HIL simulationapproach for a multicellular converter controlled by slidingmode,” International Journal of Hydrogen Energy, vol. 42, no. 17,pp. 12790–12796, 2017.

[18] T. Ould Bachir, C. Dufour, J. Belanger, J. Mahseredjian, andJ. David, “A fully automated reconfigurable calculation enginededicated to the real-time simulation of high switching fre-quency power electronic circuits,”Mathematics and Computersin Simulation, vol. 91, pp. 167–177, 2013.

[19] R. Razzaghi, M. Mitjans, F. Rachidi, and M. Paolone, “Anautomated FPGA real-time simulator for power electronics andpower systems electromagnetic transient applications,” ElectricPower Systems Research, vol. 141, pp. 147–156, 2016.

[20] F. Gomez-Olguin, I. Araujo-Vargas, T. Granados-Luna, P.Velazquez-Elizondo, K. Cano-Pulido, and A. Villarruel-Parra,“Design and assessment of a 30 kW/75 kHz DC-DC, two-phasedual interleaved buck-Boost converter,” in Proceedings of the2nd IEEE Texas Power and Energy Conference (TPEC ’18), pp.1–6, IEEE, USA, February 2018.

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