embedding of planar graphs(u) massachusetts inst … · swork suapported by an nsbrc scholarship...

13
HD-A132 538 PLANAR EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST i/I OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE D DOLEV ET AL. FEB 83 Hr /LCS/TM-3 N00014-80 C 86 2 UNCLASSIFIED /121 N

Upload: others

Post on 12-Oct-2020

0 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

HD-A132 538 PLANAR EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST i/IOF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCED DOLEV ET AL. FEB 83 Hr /LCS/TM-3 N00014-80 C 86 2

UNCLASSIFIED /121 N

Page 2: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

1.0 328 I

IU II Ih E

MICROCOPY RESOLUTION TEST CHARTNATIONAL BUREAU OF STANOARCS-1963-A

W JL

Page 3: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

LABORATO~y MASSACHUSETTS LABORATORY FOR INSTITUTE OCOMPUTER SCIENCE TECHNOLOGY

MIT/LCS/TM-237

PLANAR EMBEDDING OF

PLANAR GRAPHS

S S- I I

Ditibto Unlimited-

I IM

I.I

Co tr c I0 0 4 80 C 0 2 s SE 6S

It I

II -

LAM-AP1@U Ui public releasel I|, utz~uioQ Unlimited " '

A..D. Dotev, F." T. Leighton, and H. Trickey C

February 1983 DTI

8 B

545 TECHNOJOGY SQUARE. CAMBRIDGE, MASSACHUSETITS 02139

, i o . . q , . ,. ° *. % * - - - -. . . .- = .. . .. . * *. . . . *-. . . . . o .

Page 4: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

Planar Embedding of Planar Graphs

Danny Dolevt Frank Thomson Leightont Howard Trickey'IBM Research Mathematics Dept. Computer Science Dept.San Jose Laboratory MIT Stanford University

Key words: graph embedding, planar grapbs, outerplanar graphs, crossover-free, iLP-complete

(stract /V

Planar embedbng with minimal area of graphs on an integer grid is an interesting problem incvtheory. Vai p gave an algorithm to construct a planar embedding for trees in linear area; he also provedthat there are planar graphs that require quadratic area.

We fill in a spectrum between Valiant's results by showing that an N-node planar graph has a planarembedding with area 'O(NF), where F is a bound on the path length from any node to the exterior face. Inparticular, an outerplanar graph can be embedded without crossovers in linear area.. This bound is tight, upto constant factors: for any N and F, there exist graphs requiring 11(NF) area for planar embedding.

Also, finding a minimal embedding area is shown to be NP-co plete for forests, and hence for moregeneral types of graphs.t

PNN Ai Accession For

~4 0 ~dSw Distribution/AvilbliyCoe

t Part of the work was done while the author was at Stanford University and supported by a Chaim Wcismann postdoctoralfellowship and DARPA contract MDAOO3-C-0102. Current address: Institute of Mathematics and Computer Science, HebrewUniversity, (ilvat Ram 91904, Jerusalem, Israel.

t Work supported by DARP'A contracLNlAQ09j4-0N22r Air Force contract 0811.32-0321, and a Bantrell Fellowship.sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7.

Page 5: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

1. Introduction

VLSI design motivates the following class of problems: given a graph, map its vertices onto a plane and

its edges onto paths in that plane between the corresponding mapped vertices. Normally there are some

restrictions that the mappings must obey, such as a minimum distance between mapped vertices. The maps

give a layout, and the problem is to find a layout with a small cost. The mapping restrictions and the cost

function together specify a particular member of the class of layout problems.

Embedding of graphs has been extensively studied during the last few years [L80, V, FP, BK, CS, R,

RS, L81, L82J. In this paper we consider the layout problem when the layouts are rectilinear embedding.

without crouovers and the cost is the area of a box bounding the layout. To avoid complications, we assume

that graphs are restricted to have vertices of degree 4 or less.

In [V], Valiant looked at the layout problem for rectilinear embeddings (both with and without cross-

overs), using the bounding box area cost. He proved that a tree of vertices with maximum degree 4 can be

laid out without crossovers in an area that is linear in the number of edges (or vertices). He also showed how

Ato get a such an embedding for any planar graph using quadratic area, and proved that there are planar

graphs requiring quadratic area.

Deflitloen A planar graph has width F if there is a planar embedding of the graph such that every node

of the graph is linked to the external face of the embedding by a path of at most F vertices.

We shall show that any N-node planar graph of width F can be laid out in O(NF). area. Special cases

of th include linear area embedding. for trees and outerplanar graphs, and quadratic area embedding. for

graphs of width O(N). Furthermore, the area bound is tight up a to constant factor. This fills in a spectrum

between Valiant's results. The graph in Fig. 1.1 has N nodes and width F, and each component requires

fl(F2) for a planar embedding (see M), so the entire graph requires fl(NF) area.

N/4F subgrWlis

V nodes 4F nods

Figure 1.1 Graph needing fl(NF) area

We shall also show that finding an optimal embedding rot a forest is )JP-complete.

-I-

' ~ _.%.-%

Page 6: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

1, 2

Figure 2.1 (a) good separation (b) bad separation

2. A Plmaw Giapk Separ&.

The layout method is basically that used by Valiant M and' fideers [L" to get embeddings with,

ueinavers allowed: the grpampqle iato two, by remoagafo% wM subpw6 io recursivety Ibid' out, and,

44 them he ubProblemlayo*&mt~ rkndv -1el ~be p~wr edv

The key to methods lik these we separator theorems, wWAs guarantee that one can always split

up a grapk as needed without; having to remove too mne edima Lit and Taijan ILTI oivestigated

planar graphr sepatong aa& shwed that saw phaw rayh. of 19" eadies am be spit into' maximateIr

eqomuae parts by removing O(v/) edge&. Hfwever smsm es'ti sepral awe uemiftoh fbr a

dhld.aadcoer layout saragyf. The edges removed. by thuir w*div~ew'th. g'qk elihe a- akoWi

ix Fg IIIa) or Fig. 2.1(b), an& only the former can he-u=izr- oulatnthed. The following theorem

-o*4 ebueriesww thw *PmP separatioslom

Theorem1. A planar gvpk'ui N > 2 o~e fdp.amI4adviddF cow bt-aepevukd into

to .ubgrophahp rewuoP4VgOMP9 dge, #!sch "he cec-_-W.-1-1 P ii' 60-lati j .tOhr'ecfes. Civwfte planartdwinjg of Oa- graph the sepmeeton- can be med. atshown 4wFp Z1(e) vether theft. .1.(b) (aetshliary

th gOita kaing actoraf hosmidth F or teao).

PV Nti ieceseary, add dummy edges to the graph u*Wtths*emdewiag has~ipcyI*%thvroutr

face, and there are only triangles as interior faces. ITWd can always be done, keeptag1the graph planar and

without increassng the -width. Call tb grapr Gl.

lfhe Ab&*% .- avelaOt bewthe uumbwuesuddin tb..aboges patewtbe elett

th. outer face. IMta-.pruimg pail in G be a sIzqA*M:bNIWa vertex on the outer face tar another one,

Page 7: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

I I @

P 1

A a o e

r o

oi) 00)

- , - C .e h C s

c:k D b:k f D

a a

Figure 2.1 Cases for Separator Theorem

k-lI'sk, k-I, ... , 2, 1. We wil find a separating path with k <Fa uch that no more than twothirds of G's

vertices are on either side of it (where 'side" refers to one of the two regions that the path divides the plane

into if line are drawn from the path ends to infinity). Then G can be separated as required in the theorem

statement by removing at most 4 x 2k edges from the vertices in the separating path. The vertices on the

path itself can be divided between the two sides so that neither side ends up with more than two thirds of G.

Start out with any outer-face edge s the separating path. Assume, in general, that we have a situation

with A vertices on one side of the path, B vertices on the other, and N - A - B vertices on the path itself.

IfA:_IN andB _< N then wearedone, soamsume that B > IN.

The cases that arise are shown in Fig. 2.2 (where vertex distances are shown after colons). Figures 2.2(i)

and 2.2(i) are degenerate cases that are handled by using the right b-c path instead of the left one. The

process continues with the new path.

In Fig. 2.2(iii), vertex f is not the same as b or d. By the definition of distance of a vertex, there is an

exit path, 9- ...- h, with vertices o f distances , j - 1, ..., I or i, j + 1, ... , m - 1, m, m - 1, ... , 1 where

i + 2 and m 5 F. This exit path may coincide wholely or in part with d-...-e or b- ...-. a, but it never

need cram over them because It can merge with the rest of whichever path it touches. Also, the path should

not go back through f; this can always he avoided in a triangulated graph.

Most of the B vertices that were on the right side of the original separating path are now divided into

pieces of sises C and D. Assuming D > C, the new separating path is a-.. b-c-J-g ..... -h. Clearly, this

-3-

y-- , ; , . . ; - . , - ., - . - ,. - . - . _ . . - -

Page 8: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

7%-

- ..... m - ~ -. m - -r

I J

ig 3. arintw u mia

ne at n fth eqiedfre.N 5- Nthnw are- dme otews reea th rcs.Tevrief~~~ ~ ~ ~ an r ato h irie ht eeo n sd fteteodsprtn ah ow uthv

handled ma k ae( tCtenw I -pho - .- 4P.-- - - - - # isomhme~rdko

-ln -medn Akrtm -f -

embddegLTh dlknei ige aryin sarytgoop.bda

newpamtheor of the eqird om. sion n A Nten we sudsaet eezawhe rectin prossy Theecn

the zen rofvet cs bme wnig sdeo thae pthe a rsoc.. that eano go attforeder t e thath

Theaitatornit 1 .2(),whee te ath~ t. verlema* w m Fig.m 1 whieres the middletin

eties weon hrdepoinah herm

a Plaar hbeddig Alrith

The~~~~~~~~~~~~~~~~~~~~L laoN mLhdue iMad[M o wbdig~ vn ee hctwrsfrpaa

Page 9: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

-~o 7% ..

To turn such a drawing into a grid embedding, insert a new grid line for every dotted straight line

segment. For the diagonal lines making the connections, at most two new horizontal and two new vertical

grid lines may be needed. (The existing edges may have to be shifted so they make their final approach from

a different direction.) Let K be the number of "kinks", i.e., horizontal and vertical grid lines that need to be

added to connect any exterior face vertex of a given embedding to somewhere completely outside. It is easy

to see that K increases only by 0(t) at each marrying step, because the added edges needn't wrap around

the layout more than once. Thus, if i is the maximum of the number of marrying stages involved in laying

out G, and G2, then they can be married by added o(iF) horizontal and vertical grid lines to embed the

O(F) separating edges.

Theorem 2. Any planar graph G with N vertices of degree at most 4, and width at most F, has a planar

embedding in a grid of area A(N) = O(FN).

Proof: Other than the separation and marrying methods, the layout algorithm is the same as the one in

M. It has to be able to produce an embedding in an H x W grid, as long as J:5 HIW _ 3, and HW is

sufficiently large. Suppose by induction that A(N) is sufficient area for an N-vertex graph. Also, suppose

that K(N) is a bound on the number of kinks.

G is separated into G and G2 by removing O(F) edges, with 1GI1 = zIGI, j !< z < 1. Then an

(H - cFK(N)) x (W - cFK(N)) grid is divided in two by a cut parallel to the shorter side in the ratio

z (1 - x). By a theorem in M, the aspect ratios of the two pieces will be in the range , f r, and ,

can be laid out in these pieces, then the embedding can be completed as described above, inserting at most

cFK(N) horizontal and vertical grid lines, for some constant c. So the theorem is true if (assuming H _< W)

1_ 2(H - cFK(N)XzW - zcFK(N)) 1 A(zN), Vx, I < ! 2

Using HW _ A(N) and (H + W)l/A M _ 4l 1V3, this will be true if

x((N - ,,Ir-(NcFK(N)) j- A(xN), V,, < Z < S

3 -3

After log/ 3 N/F separation steps the graph pieces P.;e no larger than F, so if we stop the recursion at

that point we have K(N) = 0(logN/F). It is easily veriied by substitution that

A(N) = csNF - jON44 4g

satisfies the recurrence, for some a and 0 independent of N and F. In the base case, with N = F, an O(N t)

embedding (see [VM) can be used. One has to be careful to get an embedding that preserves the topology of

a given planar drawing, but it is easy to see how to do this. I

-5-

Page 10: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

Figuare 4.1 Frame Tree fots Z1=5

4. )4P-Completenm of Optbiuaa frt 1DOWbWa

Chme. a for"s and so teger A, the fosat layodd pft&#Mh II 16 ftd Whi~her or not MWe is a planar

rectisear embedding withls lei than or eauul to A ha this wat~ e *111 show that the torest layout

pebti M, P-cnsmpkte. ThbV&4 be dfe by t~mI~f the WfUlttft pObtesn to it.

h a S'Prtiasm Pftbhdm eb amtoft~gt 21 ... ,m "A~ MA %a

wd /4 < at< 3/tb NF : 130. TlmlbeW b OMOftatipew t tks d nt tn dl oist

mob we ft& Mee do* in B.TIe PMMMn iskt ism I* beoom* KPm 4A.00ftdder the tMe ift ig. 4.1(4) lbal it the &Men Wee. Th~ft oft *tet at ftetyr OW~ "*nt ew~pt t~st

an bb 9 h"b of she I (?W$,A Ai -ft mdd wOl be WOOiK4 OW,~ A *1t &k*h Wetl lfitdles.)

LL 8 Maew mbg 4MfsO Us from# "e WO a fuuvWIN 6u oft 0(4n +3) X (98 + 3) or lee. avidkdoft 0,5 PWO geWPdb OW OM .oasc* At lbW ANe. # A 06MU rt~ft

or MOK*uIb. of"a dow whMr to* fofUe a"p 610A iS#Wsso Wi ehtUVfd as in Pit. 4.1?b) "ust

Prod: The IMk (40 + 1) x (25 + 3) - "w ,eVtis so t effbedding Is requbed to ws eE fr Id poit

hravueow w else loa*eft 6%. This ames tha ab .dg of thetWe an e 9eW~kWt a a ith bt t imtA,

hR that wrould take up a grid point In the middle tha is Mwed ko Onbeddiff a graph votta.

Amy layout wing a*~ i-mat edpm mont hate anl of she degree-4 VWftee ofa vertical Apine btie on top

.at 'Oelhfti b N, hbrw him OWui OWN to f be two deite-4 vefte at optote

OWNW4e *-4~qM AMis b ISGMpnb (M -Of Oas G&W woeft VWo~l hafe to be ibuftd between

Page 11: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

Therefore, the only possible changes to the given diagram, other than point renaming, are ones at the

degree-2 vertices, such an in Fig. 4.1(b). I

Notice that if the frame tree is embedded using an allowed folding near the top of a spine, this cuts a

hole into two pieces of sizes 2 and B - 2. There cannot be more than one fold into a hole. From now on,

use to term *hole* to mean either a B-point vertical slot or one of these 2 + (B - 2)-point aggregates.

Theorem 4. The forest layout problem s NP-complete.

Proof: Given an instance of the 3-partition problem, construct the frame tree and add 3m other pieces,

unconnected to that tree: for each zi there is a piece consisting of zi vertices joined into a line by zi - I

edges. If m is odd, use the frame graph for the next higher even number and fill in one of the vertical holes.

Now we claim that the 3-partition problem instance has a solution iff there is an embedding of this

forest with a bounding box area of (4n+ 3) x (2B+ 3). For, by the lemma, if there is such an embedding then

it must be as shown in Fig. 4.1(a) with the extra pieces filling up the holes. Since all the grid points are to

be used, this gives a solution to the 3-partition problem, because the size restrictions on the x's imply that

there must be exactly three pieces in each hole. Conversely, given a solution to the 3-partition problem, asuitable embedding can be found by filling the holes in the frame tree with the pieces corresponding to the

partitioned sets.

This is not a polynomial reduction, since the frame tree has a number of vertices of the order of the

numbers involved in the 3-partition problem, rather than the number of bits required to represent thoe

numbers. This does not matter, however, since the 3-partition problem is strongly UP-complete. The layout

problem is in HP because one can simply guess a mapping of all the vertices to grid points and then verit

that the edges can all be put along the connecting lines. Therefore, the forest layout problem is NP-complete.

l

References

[BK] R. P. Brent and H.T. Kung, "On the area embedding of binary tree layouts," Australian Nat. Univ.

Rep. TR-CS-79-07, 1979.

[CS] M. Cutler and Y. Shiloach, "Permutation layout,* Networks 8, pp. 253-278, 1978.

jFP] M. J. Fischer and M. S. Paterson, "Optimal tree layout," Proc. 12th ACM Symp. Theory Comput,

1980.

jGJ M. R. Carey and D. S. Johnson, omputers and Intractabitity. San Francisco: Freeman, 1979.

-" -7-

Page 12: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

[LIF. T1. Le~oa. -Now bow bound technktue he VLI,* Prc. fad MANE Symp. fouadations Corn-

put. EeL, 1931, pp. 1-12.

(Lai F. T. Leghton, "A bayot strategy for VLSI which is probabl good,* Proc. 14th ACM Symp. Theory

Cosuput., Ion, pp. W97.

[IaC. 3. Lob...., "AmaScient graph Imposts (hr WWS). Pim. 1 BBB SYMnP. Feuadationm Coms-

put. ScL, M16.

[L21 R. J. Uipon ad 3L L. Tarje, 4A spamatewsrom br pbowar @Ipha A Goofat n Thoretical

OUmnPat Ed., Uniweuuty at Waterloo, 13M, pp. 1-10.

(RJ A. L Roenberg -on nbedding graphs in grids,' IBM Watsn Research Center Tech. Rep. RC 7553

(# 2666) IMO

PMS W. L. Rune, and L. Sopd.,, &abouin bou* plom abeidfo of Ures CMV Ckaf. on VLSI

Symsexm and Cmdnpi&b&2, O Mier36.

M L G. Vaboisa, %hoksmdiu mudrmin VLI eboulie,' AM Trm. COmut., V91.0-30, pp. 135-

441

Page 13: EMBEDDING OF PLANAR GRAPHS(U) MASSACHUSETTS INST … · sWork suapported by an NSBRC scholarship and NSF grant MCSS-12U?7. 1. Introduction VLSI design motivates the following class

i--v

IIIg

V.A,

AII

'A' *Artw

.09.*