eltr 145 (digital 2), section 1 recommended schedule · eia raising the standard; electronics...

ELTR 145 (Digital 2), section 1

Recommended schedule

Day 1Topics: Latch circuitsQuestions: 1 through 10Lab Exercise: S-R latch from individual gates (question 51)

Day 2Topics: 555 timer circuitQuestions: 11 through 20Lab Exercise: 555 timer in astable mode (question 52)

Day 3Topics: Gated latch circuitsQuestions: 21 through 30Lab Exercise: Troubleshooting practice (decade counter circuit – question 54)

Day 4Topics: Flip-flopsQuestions: 31 through 40Lab Exercise: Troubleshooting practice (decade counter circuit – question 54)

Day 5Topics: Flip-flops (continued)Questions: 41 through 50Lab Exercise: J-K flip-flop IC (question 53)

Day 6Exam 1: includes S-R latch circuit performance assessmentLab Exercise: Troubleshooting practice (decade counter circuit – question 54)

Troubleshooting practice problemsQuestions: 57 through 66

DC/AC/Semiconductor/Opamp review problemsQuestions: 67 through 86

General concept practice and challenge problemsQuestions: 87 through the end of the worksheet

Impending deadlinesTroubleshooting assessment (counter circuit) due at end of ELTR145, Section 3Question 55: Troubleshooting logQuestion 56: Sample troubleshooting assessment grading criteria

1


Skill standards addressed by this course section

EIA Raising the Standard; Electronics Technician Skills for Today and Tomorrow, June 1994

F Technical Skills – Digital CircuitsF.11 Understand principles and operations of types of flip-flop circuits.F.12 Fabricate and demonstrate types of flip-flop circuits.F.13 Troubleshoot and repair flip-flop circuits.F.17 Understand principles and operations of clock and timing circuits.F.18 Fabricate and demonstrate clock and timing circuits.F.19 Troubleshoot and repair clock and timing circuits.

B Basic and Practical Skills – Communicating on the JobB.01 Use effective written and other communication skills. Met by group discussion and completion of labwork.B.03 Employ appropriate skills for gathering and retaining information. Met by research and preparation

prior to group discussion.B.04 Interpret written, graphic, and oral instructions. Met by completion of labwork.B.06 Use language appropriate to the situation. Met by group discussion and in explaining completed labwork.B.07 Participate in meetings in a positive and constructive manner. Met by group discussion.B.08 Use job-related terminology. Met by group discussion and in explaining completed labwork.B.10 Document work projects, procedures, tests, and equipment failures. Met by project construction and/or

troubleshooting assessments.C Basic and Practical Skills – Solving Problems and Critical Thinking

C.01 Identify the problem. Met by research and preparation prior to group discussion.C.03 Identify available solutions and their impact including evaluating credibility of information, and locating

information. Met by research and preparation prior to group discussion.C.07 Organize personal workloads. Met by daily labwork, preparatory research, and project management.C.08 Participate in brainstorming sessions to generate new ideas and solve problems. Met by group discussion.

D Basic and Practical Skills – ReadingD.01 Read and apply various sources of technical information (e.g. manufacturer literature, codes, and

regulations). Met by research and preparation prior to group discussion.E Basic and Practical Skills – Proficiency in Mathematics

E.01 Determine if a solution is reasonable.E.02 Demonstrate ability to use a simple electronic calculator.E.06 Translate written and/or verbal statements into mathematical expressions.E.07 Compare, compute, and solve problems involving binary, octal, decimal, and hexadecimal numbering

systems.E.12 Interpret and use tables, charts, maps, and/or graphs.E.13 Identify patterns, note trends, and/or draw conclusions from tables, charts, maps, and/or graphs.E.15 Simplify and solve algebraic expressions and formulas.E.16 Select and use formulas appropriately.E.21 Use Boolean algebra to break down logic circuits.

2


Common areas of confusion for students

Difficult concept: Determining response of a state-dependent logic system.The very wording of this ”difficult concept” may seem difficult to the reader! What I am saying here is

that latches and flip-flops are difficult to figure out because their outputs not only depend on the logic levelsof the inputs, but also on the previous output states. For this reason, these devices fall into the category of”state machines:” they ”remember” what logic state they were last in.

I have but one tool for you to use in understanding state machine circuits: the lowly timing diagram.Truth tables fail to fully capture the essence of state machines unless they are expanded to include column(s)showing the last output(s) as well as the inputs. Timing diagrams keep a record of a circuit’s last outputstates as you check to see what will happen for each new input condition. Learn how to draw and interprettiming diagrams, and you will have a powerful tool to apply toward the study of latches and flip-flop circuits!

Difficult concept: The time-constant equation.Many students find the time-constant equation difficult because it involves exponents, particularly

exponents of Euler’s constant e. This exponent is often expressed as a negative quantity, making it evenmore difficult to understand. The single most popular mathematical mistake I see students make with thisequation is failing to properly follow algebraic order of operations. Some students try to overcome thisweakness by using calculators which allow parenthetical entries, nesting parentheses in such a way that thecalculator performs the proper order of operations. However, if you don’t understand order of operationsyourself, you will not know where to properly place the parentheses. If you have trouble with algebraic orderof operations, there is no solution but to invest the necessary time and learn it!

Beyond mathematical errors, though, the most common mistake I see students make with the timeconstant equation is mis-application. One version of this equation expresses increasing quantities, whileanother version expresses decreasing quantities. You must already know what the variables are going to doin your time-constant circuit before you know which equation to use! You must also be able to recognize oneversion of this equation from the other: not by memory, lest you should forget; but by noting what the resultof the equation does as time (t) increases. Here again there will be trouble if you are not adept applyingalgebraic order of operations.

3

Questions

Question 1

What do you think this logic buffer gate will do, with the output signal ”feeding back” to the input?

Output

What do you think this buffer will do when each input switch is separately pressed?

Output

VDD

A

B

Why does the second buffer circuit need a resistor in the feedback loop?file 02896

Question 2

When studying latch circuits, you will come across many references to set and reset logic states. Givea simple definition for each of these terms in the context of latch and flip-flop circuits.

file 02897

4

Question 3

The circuit shown here is called an S-R latch:

VDD

Set

Reset

Q

Q

Complete the truth table for this latch circuit:

Set Reset0

01

1 1

Q Q

0 1

0

file 01349

Question 4

Some digital circuits are considered to have active-low inputs, while others have active-high inputs.Explain what each of these terms means, and how we might identify which type of input(s) a digital circuithas.

file 02898

5

Question 5

The circuit shown here is called an S-R latch:

Q

Q

Identify which of the two input lines is the Set, and which is the Reset, and then write a truth tabledescribing the function of this circuit.

file 01351

Question 6

Latch circuits are often drawn as complete units in their own block symbols, rather than as a collectionof individual gates:

S Q

QR

S

R

Q

Q

VDD VDD

This simplifies schematic drawings where latches are used, much as the use of gate symbolism (asopposed to drawing individual transistors and resistors) simplifies the diagrams of more elementary digitalcircuits.

From the block symbols shown in this question, is there any way to determine which of the S-R latchesis built with NOR gates, and which one is built with NAND gates?

file 01352

6

Question 7

The following relay logic circuit is for starting and stopping an electric motor:

L1 L2

CR1

CR1

CR1 Motor

Start Stop

Draw the CMOS logic gate equivalent of this motor start-stop circuit, using these two pushbuttonswitches as inputs:

Start

Stop

VDD

Mtr

Make sure that your schematic is complete, showing how the logic gate will drive the electric motor(through the power transistor shown).

file 01348

7

Question 8

One practical application of S-R latch circuits is switch debouncing. Explain what ”bounce” refers to inmechanical switches, and also explain how this circuit eliminates it:

S Q

QR

VDD

VDD Output

Also, show where an oscilloscope could be connected to display any switch ”bounce,” and explain howthe oscilloscope would have to be configured to capture this transient event.

file 01353

8

Question 9

Complete the timing diagram, showing the state of the Q output over time as the Set and Reset switchesare actuated. Assume that Q begins in the low state on power-up:

VDD

S Q

QR

Set

Reset

VDD

SetActuated

Released

Actuated

Released

Reset

QHigh

Low

Time

file 02899

9

Question 10

A student builds this simple S-R latch for their lab experiment:

VDD

Set

Reset

Q

Q

When the student powers up this circuit, she notices something strange. Sometimes the latch powersup in the set state (Q high and Q low), and other times it powers up in the reset state (Q low and Q high).The power-up state of their circuit seems to be unpredictable.

What state should their circuit power up in? Did the student make an error building the latch circuit?file 01378

10

Question 11

The following expression is frequently used to calculate values of changing variables (voltage and current)in RC and LR timing circuits:

e−t

τ or1

et

τ

If we evaluate this expression for a time of t = 0, we find that it is equal to 1 (100%). If we evaluatethis expression for increasingly larger values of time (t → ∞), we find that it approaches 0 (0%).

Based on this simple analysis, would you say that the expression e−t

τ describes the percentage that avariable has changed from its initial value in a timing circuit, or the percentage that it has left to changebefore it reaches its final value? To frame this question in graphical terms . . .

TimeInitial

Final

t

Voltageor

CurrentPercentage changed

from initial value

Percentage left tochange before reaching

final value

TimeFinal

t

Voltageor

Current

Percentage changedfrom initial value

Percentage left tochange before reaching

final value

Initial

Increasing variable Decreasing variable

Which percentage does the expression e−t

τ represent in each case? Explain your answer.file 02946

Question 12

Calculate the voltage across a 470 µF capacitor after discharging through a 10 kΩ resistor for 9 seconds,if the capacitor’s original voltage (at t = 0) was 24 volts.

Also, express this amount of time (9 seconds) in terms of how many time constants have elapsed.file 00452

Question 13

Calculate the amount of time it takes for a 33 µF capacitor to charge from 0 volts to 20 volts, if poweredby a 24 volt battery through a 10 kΩ resistor.

file 01814

11

Question 14

Determine the amount of time needed after switch closure for the capacitor voltage (VC) to reach thespecified levels:

40 VDC C = 4.7 µF

R = 220 kΩSwitch

+−

VC Time0 volts10 volts20 volts30 volts40 volts

Trace the direction of electron flow in the circuit, and also mark all voltage polarities.file 02942

Question 15

Determine the amount of time needed for the capacitor voltage (VC) to fall to the specified levels afterthe switch is thrown to the ”discharge” position, assuming it had first been charged to full battery voltage:

Switch

12 V

R = 190 kΩ

C = 17 µF

VC Time10 volts8 volts6 volts4 volts2 volts

Trace the direction of electron flow in the circuit, and also mark all voltage polarities.file 02943

12

Question 16

The type ”555” integrated circuit is a highly versatile timer, used in a wide variety of electronic circuitsfor time-delay and oscillator functions. The heart of the 555 timer is a pair of comparators and an S-R latch:

−

+

−

+

S

R

Q

CLR

Reset

+V

Disch

Trig Out

555 timer

+V

Gnd

Thresh

Ctrl

The various inputs and outputs of this circuit are labeled in the above schematic as they often appearin datasheets (”Thresh” for threshold, ”Ctrl” or ”Cont” for control, etc.).

To use the 555 timer as an astable multivibrator, simply connect it to a capacitor, a pair of resistors,and a DC power source as such:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

CtrlA

B

R1

R2

C1

If were were to measure the voltage waveforms at test points A and B with a dual-trace oscilloscope,we would see the following:

13

B

A

Explain what is happening in this astable circuit when the output is ”high,” and also when it is ”low.”file 01418

14

Question 17

The model ”555” integrated circuit is a very popular and useful ”chip” used for timing purposes inelectronic circuits. The basis for this circuit’s timing function is a resistor-capacitor (RC) network:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

R1

R2

C

In this configuration, the ”555” chip acts as an oscillator: switching back and forth between ”high” (fullvoltage) and ”low” (no voltage) output states. The time duration of one of these states is set by the chargingaction of the capacitor, through both resistors (R1 and R2 in series). The other state’s time duration is setby the capacitor discharging through one resistor (R2):

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

R1

R2

C

Capacitor charging through R1 and R2 (series)

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

R1

R2

C

Capacitor discharging through R2 only

Note: all currents shown in the direction of conventional flow

Obviously, the charging time constant must be τcharge = (R1+R2)C, while the discharging time constantis τdischarge = R2C. In each of the states, the capacitor is either charging or discharging 50% of the waybetween its starting and final values (by virtue of how the 555 chip operates), so we know the expression

e−t

τ = 0.5, or 50 percent.†

† For those who must know why, the 555 timer in this configuration is designed to keep the capacitorvoltage cycling between 13 of the supply voltage and

23 of the supply voltage. So, when the capacitor is

15

Develop two equations for predicting the ”charge” time and ”discharge” time of this 555 timer circuit,so that anyone designing such a circuit for specific time delays will know what resistor and capacitor valuesto use.

file 01807

Question 18

This astable 555 circuit has a potentiometer allowing for variable duty cycle:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

With the diode in place, the output waveform’s duty cycle may be adjusted to less than 50% if desired.Explain why the diode is necessary for that capability. Also, identify which way the potentiometer wipermust be moved to decrease the duty cycle.

file 01419

charging from 13VCC to its (final) value of full supply voltage (VCC), having this charge cycle interruptedat 23VCC by the 555 chip constitutes charging to the half-way point, since

23 of half-way between

13 and 1.

When discharging, the capacitor starts at 23VCC and is interrupted at13VCC , which again constitutes 50%

of the way from where it started to where it was (ultimately) headed.

16

Question 19

A popular use of the 555 timer is as a monostable multivibrator. In this mode, the 555 will output apulse of fixed length when commanded by an input pulse:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

Inputpulse

Fixed time

How low does the triggering voltage have to go in order to initiate the output pulse? Also, write anequation specifying the width of this pulse, in seconds, given values of R and C. Hint: the magnitude ofthe supply voltage is irrelevant, so long as it does not vary during the capacitor’s charging cycle. Show yourwork in obtaining the equation, based on equations of RC time constants. Don’t just copy the equation froma book or datasheet!

file 01420

17

Question 20

A sequential timer circuit may be constructed from multiple 555 timer ICs cascaded together. Examinethis circuit and determine how it works:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

Inputpulse

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

Output A Output B

Can you think of any practical applications for a circuit such as this?file 02944

18

Question 21

The circuit shown here is a gated S-R latch. Write the truth table for this latch circuit, and explain thefunction of the ”Enable” (E) input:

Q

QS

R

E

E S R Q Q0

1

0 0

0 0

0

0

1

1

1

1

0

0

1

1

1

1

1

0

1

0

1

0

file 01354

Question 22

Here is an S-R latch circuit, built from NAND gates:

Q

QS

R

Add two more NAND gates to this circuit, converting it into a gated S-R latch, with an Enable (E)input, and write the truth table for the new circuit.

file 01355

19

Question 23

Here, a gated S-R latch is being used to control the electric power to a powerful ultraviolet lamp, usedfor sterilization of instruments in a laboratory environment:

S Q

QR

E

VDDLockout On

Off

L1 L2

SSR

Lamp

120 VAC

Based on your knowledge of how gated S-R latches function, what is the purpose of the ”Lockout”switch? Also, explain how the CMOS latch is able to exert control over the high-power lamp (i.e. explainthe operation of the interposing devices between the latch and the lamp).

Now, suppose the lab personnel want to add a feature to the ultraviolet sterilization chamber: an electricsolenoid door lock, so that personnel can open the door to the chamber only if the following conditions aremet:

• Lamp is off• ”Lockout” switch is sending a ”low” signal to the latch’s Enable input

Modify this circuit so that it energizes the door lock solenoid, allowing access to the chamber, only ifthe above conditions are both true.

file 01356

20

Question 24

A variation on the gated S-R latch circuit is something called the D-latch:

Q

Q

E

E Q Q0 0

0

01

1

1

1

D

D

Complete the truth table for this D latch circuit, and identify which rows in the truth table representthe set, reset, and latch states, respectively.

file 01357

21

Question 25

Complete the timing diagram, showing the state of the Q output over time as the input switches areactuated. Assume that Q begins in the low state on power-up:

VDDVDD

Actuated

Released

Actuated

Released

QHigh

Low

Time

D

D

Q

QD

E

Enable

Enable

file 02901

22

Question 26

Complete the timing diagram, showing the state of the Q output over time as the input switches areactuated. Assume that Q begins in the low state on power-up:

Actuated

Released

Actuated

Released

QHigh

Low

Time

Enable

S Q

QR

E

S

Actuated

Released

R

file 02913

23

Question 27

An analog-to-digital converter is a circuit that inputs a variable (analog) voltage or current, and outputsmultiple bits of binary data corresponding to the magnitude of that measured voltage or current. In thecircuit shown here, an ADC inputs a voltage signal from a potentiometer, and outputs an 8-bit binary”word,” which may then be read by a computer, transmitted digitally over a communications network, orstored on digital media:

VDD

Vin 8-bit digitaloutput

ADC

As the input voltage changes, the binary number output by the ADC will change as well. Suppose,though, that we want to have sample-and-hold capability added to this data acquisition circuit, to allow us to”freeze” the output of the ADC at will. Explain how using eight D latch circuits will give us this capability:

VDD

Vin 8-bit digitaloutput

ADC

Q

QD

E

Q

QD

E

Q

QD

E

Q

QD

E

Q

QD

E

Q

QD

E

Q

QD

E

Q

QD

E

VDDSample

Hold

file 01358

24

Question 28

Gated latch circuits often come packaged in multiple quantities, with common gate inputs, so that morethan one of the latches within the integrated circuit will be enabled and disabled simultaneously. Examinethis logic symbol, representative of the 74AC16373, a 16-bit D-type latch with tri-state outputs:

1EN

C1

2EN

C2

1OE

2OE

1LE

2LE

1D1D1 1Q11

1D2 1Q2

1D3 1Q3

1D4 1Q4

1D5 1Q5

1D6 1Q6

1D7 1Q7

1D8 1Q8

2D2D1 2Q1

2D2 2Q2

2

2D3 2Q3

2D4 2Q4

2D5 2Q5

2D6 2Q6

2D7 2Q7

2D8 2Q8

Note how the sixteen D latches are divided into two groups of eight. Explain the functions of the fourinputs at the very top of the symbol (1EN, C1, 2EN, and C2). Which of these input lines correspond to the”Enable” inputs seen on single D-type latch circuits? Also, describe what the ”wedge” shapes represent onthe 1EN and 2EN input lines.

Suppose you wished to have all sixteen latch circuits enabled as one, rather than as two groups of eight.Show what you would have to do to this circuit in order to achieve this goal.

file 01359

25

Question 29

In many types of digital systems, a set of square-wave signals are phase-shifted from each other by 90o.Such a phase relationship is called quadrature.

Determine the output of a D-type latch for this pair of quadrature signals, applied to the D and Einputs over time:

D

E

Q

VDD

Gnd

VDD

Gnd

VDD

Gnd

Time

Then, determine the output of a D-type latch when the phase relationship is reversed, (D leading E by90o, instead of E leading D by 90o):

D

E

Q

VDD

Gnd

VDD

Gnd

VDD

Gnd

Time

file 01360

26

Question 30

This one-way street is equipped with an alarm to signal drivers going the wrong way. The sensors workby light beams being broken when an automobile passes between them. The distance between the sensorsis less than the length of a normal car, which means as a car passes by, first one beam is broken, then bothbeams become broken, then only the last beam is broken, then neither beam is broken. The sensors arephototransistors sensitive only to the narrow spectrum of light emitted by the laser light sources, so thatambient sunlight will not ”fool” them:

Laser lightsources

A BSensors

Car

Both sensors connect to inputs on a D-type latch, which is then connected to some other circuitry tosound an alarm when a car goes down the road the wrong way:

VDD

Sensor A

Sensor B

Q

QD

E

Siren

The first question is this: which way is the correct way to drive down this street? From left to right, orfrom right to left (as shown in the illustration)?

The second question is, how will the system respond if sensor A’s laser light source fails? What willhappen if sensor B’s laser light source fails?

file 01361

27

Question 31

Usually, propagation delay is considered an undesirable characteristic of logic gates, which we simplyhave to live with. Other times, it is a useful, even necessary, trait. Take for example this circuit:

InputOutput

If the gates constituting this circuit had zero propagation delay, it would perform no useful function atall. To verify this sad fact, analyze its steady-state response to a ”low” input signal, then to a ”high” inputsignal. What state is the AND gate’s output always in?

Now, consider propagation delay in your analysis by completing a timing diagram for each gate’s output,as the input signal transitions from low to high, then from high to low:

InputOutput

InputGnd

VDD

NOT1 NOT2 NOT3

AND

NOT1Gnd

VDD

Gnd

VDD

Gnd

VDD

NOT2

NOT3

Gnd

VDD

AND

What do you notice about the state of the AND gate’s output now?file 01362

Question 32

Explain how you would use an oscilloscope to measure the propagation delay of a semiconductor logicgate. Draw a schematic diagram, if necessary. Are the propagation delay times typically equal for a digitalgate transitioning from ”low” to ”high”, versus from ”high” to ”low”? Consult datasheets to substantiateyour answer.

Also, comment on whether or not electromechanical relays have an equivalent parameter to propagationdelay. If so, how do you suppose the magnitude of a relay’s delay compares to that of a semiconductor gate,and why?

file 01371

28

Question 33

Determine the Q and Q output states of this D-type gated latch, given the following input conditions:

Q

QD

E

A

B

AVDD

Gnd

VDD

GndB

VDD

GndQ

VDD

GndQ

Now, suppose we add a propagation-delay-based one-shot circuit to the Enable line of this D-type gatedlatch. Re-analyze the output of the circuit, given the same input conditions:

29

Q

QD

E

A

B

AVDD

Gnd

VDD

GndB

VDD

GndQ

VDD

GndQ

Comment on the differences between these two circuits’ responses, especially with reference to theenabling input signal (B).

file 01364

Question 34

Shown here are two digital components: a D-type latch and a D-type flip-flop:

Q

QD

E

D

C

Q

Q

D-type latch D-type flip-flop

Other than the silly name, what distinguishes a ”flip-flop” from a latch? How do the two circuits differin function?

file 01365

30

Question 35

Explain how the addition of a propagation-delay-based one-shot circuit to the enable input of an S-Rlatch changes its behavior:

S

R

Q

Q

C

Specifically, reference your answer to a truth table for this circuit.file 01366

Question 36

Plain S-R latch circuits are ”set” by activating the S input and de-activating the R input. Conversely,they are ”reset” by activating the R input and de-activating the S input. Gated latches and flip-flops,however, are a little more complex:

S-R flip-flop

S Q

QR

C

S Q

QR

E

S-R gated latch

Describe what input conditions have to be present to force each of these multivibrator circuits to setand to reset.

For the S-R gated latch:

• Set by . . .• Reset by . . .

For the S-R flip-flop:

• Set by . . .• Reset by . . .

file 02935

31

Question 37

Determine the output states for this S-R flip-flop, given the pulse inputs shown:

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

S

R

C

Q

Q

S

R

VDD

GndC

file 01367

32

Question 38

An extremely popular variation on the theme of an S-R flip-flop is the so-called J-K flip-flop circuitshown here:

Q

Q

CJ

K

Clock pulse detector

Note that an S-R flip-flop becomes a J-K flip-flop by adding another layer of feedback from the outputsback to the enabling NAND gates (which are now three-input, instead of two-input). What does this addedfeedback accomplish? Express your answer in the form of a truth table.

One way to consider the feedback lines going back to the first NAND gates is to regard them as extraenable lines, with the Q and Q outputs selectively enabling just one of those NAND gates at a time.

file 01368

Question 39

Determine what input conditions are necessary to set, reset, and toggle these two J-K flip-flops:

J Q

Q

C

K

J

C

K

Q

Q

Active-high inputs Active-low inputs

For the J-K flip-flop with active-high inputs:

• Set by . . .• Reset by . . .• Toggle by . . .

For the J-K flip-flop with active-low inputs:

• Set by . . .• Reset by . . .• Toggle by . . .

file 02936

33

Question 40

Determine the output states for this J-K flip-flop, given the pulse inputs shown:

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

VDD

GndC

J Q

Q

C

K

J

K

file 02934

34

Question 41

Determine the output states for this D flip-flop, given the pulse inputs shown:

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

D

C

Q

Q

D

C

file 02940

35

Question 42

Determine the output states for this J-K flip-flop, given the pulse inputs shown:

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

VDD

GndC

J

K

J

C

K

Q

Q

file 02939

36

Question 43

Flip-flops often come equipped with asynchronous input lines as well as synchronous input lines. ThisJ-K flip-flop, for example, has both ”preset” and ”clear” asynchronous inputs:

J Q

Q

C

K

PRE

CLR

Describe the functions of these inputs. Why would we ever want to use them in a circuit? Explain whatthe ”synchronous” inputs are, and why they are designated by that term.

Also, note that both of the asynchronous inputs are active-low. As a rule, asynchronous inputs arealmost always active-low rather than active-high, even if all the other inputs on the flip-flop are active-high.Why do you suppose this is?

file 01370

37

Question 44

A scientist is using a microprocessor system to monitor the boolean (”high” or ”low”) status of a particlesensor in her high-speed nuclear experiment. The problem is, the nuclear events detected by the sensor comeand go much faster than the microprocessor is able to sample them. Simply put, the pulses output by thesensor are too brief to be ”caught” by the microprocessor every time:

Sensor

Microprocessor

Vdd

VddReal-time

data Input pin

Brief pulses

She asks several technicians to try and fix the problem. One tries altering the microprocessor’s programto achieve a faster sampling rater, to no avail. Another recalibrates the particle sensor to react slower, butthis only results in missed data (because the real world data does not slow down accordingly!). No solutiontried so far works, because the fundamental problem is that the microprocessor is just too slow to ”catch”the extremely short pulse events coming from the particle sensor. What is required is some kind of externalcircuit to ”read” the sensor’s state at the leading edge of a sample pulse, and then hold that digital statelong enough for the microprocessor to reliably register it.

Finally, another electronics technician comes along and proposes this solution, but then goes on vacation,leaving you to implement it:

Sensor

Microprocessor

Vdd

VddReal-time

data

Input pin

Output pin

D

C

Q

Q

CLR

Vdd

Explain how this D-type flip-flop works to solve the problem, and what action the microprocessor hasto take on the output pin to make the flip-flop function as a detector for multiple pulses.

file 01464

38

Question 45

A common type of rotary encoder is one built to produce a quadrature output:

Light sensor(phototransistor)

Rotary encoder

LED

The two LED/phototransistor pairs are arranged in such a way that their pulse outputs are always 90o

out of phase with each other. Quadrature output encoders are useful because they allow us to determinedirection of motion as well as incremental position.

Building a quadrature direction detector circuit is easy, if you use a D-type flip-flop:

Light sensor(phototransistor)

Rotary encoder

LEDD

C

Q

QCW/CCW

Analyze this circuit, and explain how it works.file 01384

39

Question 46

Suppose a student wants to build a sound-controlled lamp control circuit, whereby a single clap orother loud burst of noise turns the lamp on, and another single clap turns it off. The sound-detection andlamp-drive circuitry is shown here:

Condensermicrophone

VDD

VDD

L1

L2

Lamp

A positive pulse appearshere whenever a clap is heard

Bias voltage set so transistoris in cutoff with no sound

Add a J-K flip-flop to this schematic diagram to implement the toggling function.file 01369

Question 47

If the clock frequency driving this flip-flop is 240 Hz, what is the frequency of the flip-flop’s outputsignals (either Q or Q)?

J

C

K Q

Q

VDD

240 Hz

file 01372

40

Question 48

The flip-flop circuit shown here is classified as synchronous because both flip-flops receive clock pulsesat the exact same time:

J Q

Q

C

K

J Q

Q

C

K

VDDFF1 FF2

Define the following parameters:

• Set-up time• Hold time• Propagation delay time• Minimum clock pulse duration

Then, explain how each of these parameters is relevant in the circuit shown.file 01385

Question 49

Locate a manufacturer’s datasheet for a flip-flop IC, and research the following parameters:

• Flip-flop type (S-R, D, J-K)• Part number• ANSI/IEEE standard symbol• How many asynchronous inputs• Minimum setup and hold times (shown in timing diagrams)

file 02937

41

Question 50

A student has an idea to make a J-K flip-flop toggle: why not just connect the J , K, and Clockinputs together and drive them all with the same square-wave pulse? If the inputs are active-high and theclock is positive edge-triggered, the J and K inputs should both go ”high” at the same moment the clocksignal transitions from low to high, thus establishing the necessary conditions for a toggle (J=1, K=1, clocktransition):

J Q

Q

C

KClock signal

Unfortunately, the J-K flip-flop refuses to toggle when this circuit is built. No matter how many clockpulses it receives, the Q and Q outputs remain in their original states – the flip-flop remains ”latched.”Explain the practical reason why the student’s flip-flop circuit idea will not work.

file 02938

42

Question 51

Version:

Schematic

Truth table

A

B

Predicted Actual

Q Q

Description

Competency: S-R latch circuit

Build an S-R latch circuit using either NAND or NOR gates

Rlimit Rlimit

A B Q Q0 0

0

0

1

1

1 1

A B Q Q0 0

0

0

1

1

1 1

file 01621

43

Question 52

Given conditions

Version:

Parameters

Predicted Measured

Schematic

+V =

-V =

R1 = R2 =

C1 = C2 =

Competency: Astable 555 timer

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

Vout

R1

R2

C1C2

thigh

tlow

fout

Fault analysis

Suppose component fails open

shorted

other

What will happen in the circuit?

file 02861

44

Question 53

Version:

Schematic

Q Q

Description

Rlimit Rlimit

Competency: J-K flip-flop IC

Demonstrate the "set," "reset," and "toggle" modes of aJ-K flip-flop integrated circuit.

J Q

Q

C

K

"Set" mode demonstrated

"Reset" mode demonstrated

"Toggle" mode demonstrated

Parameters

VDD

RpulldownRpulldown

file 02900

45

Question 54

CTR

Display driver IC

abcdefg

Seven-segment display

AB

C

D

a

b

cd

e

fg

Clk

Counter IC

RST

Event switch

ResetU1 U2

Given conditions

Version:

Schematic

Parameters

U1 = U2 =

Competency: Decade counter circuit

YES

NO

Counter increments with each physical event,counting from 0 to 9 and then resetting backto 0 again. Count sequence exhibits no skippedcounts and no missed events.

Details purposely omitted from schematic diagram

file 03851

46

Question 55

Conclusions(i.e. What this tells me . . . )

Troubleshooting log

(i.e. What I did and/or noticed . . . )Actions / Measurements / Observations

file 03933

47

Question 56

NAME: Troubleshooting Grading CriteriaYou will receive the highest score for which all criteria are met.

100 % (Must meet or exceed all criteria listed)A. Absolutely flawless procedureB. No unnecessary actions or measurements taken

90 % (Must meet or exceed these criteria in addition to all criteria for 85% and below)A. No reversals in procedure (i.e. changing mind without sufficient evidence)B. Every single action, measurement, and relevant observation properly documented

80 % (Must meet or exceed these criteria in addition to all criteria for 75% and below)A. No more than one unnecessary action or measurementB. No false conclusions or conceptual errorsC. No missing conclusions (i.e. at least one documented conclusion for action / measurement / observation)

70 % (Must meet or exceed these criteria in addition to all criteria for 65%)A. No more than one false conclusion or conceptual errorB. No more than one conclusion missing (i.e. an action, measurement, or relevant observation without a

corresponding conclusion)

65 % (Must meet or exceed these criteria in addition to all criteria for 60%)A. No more than two false conclusions or conceptual errorsB. No more than two unnecessary actions or measurementsC. No more than one undocumented action, measurement, or relevant observationD. Proper use of all test equipment

60 % (Must meet or exceed these criteria)A. Fault accurately identifiedB. Safe procedures used at all times

50 % (Only applicable where students performed significant development/design work – i.e. not a provencircuit provided with all component values)A. Working prototype circuit built and demonstrated

0 % (If any of the following conditions are true)A. Unsafe procedure(s) used at any point

file 03932

48

Question 57

Identify at least one component fault that would cause the ”Q” LED to always remain off, no matterwhat was done with the input switches.

VDD

Set

Reset

Q

QR1

R2

U1

U2

R3

R4

For each of your proposed faults, explain why it will cause the described problem.file 03892

Question 58

Identify at least one component fault that would cause the ”Q” LED to always stay on, no matter whatwas done with the input switches.

VDD

Set

Reset

Q

QR1

R2

U1

U2

R3

R4


49

Question 59

Predict how the operation of this astable 555 timer circuit will be affected as a result of the followingfaults. Specifically, identify what will happen to the capacitor voltage (VC1) and the output voltage (Vout)for each fault condition. Consider each fault independently (i.e. one at a time, no multiple faults):

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

R1

R2

+V

C1

Vout

• Resistor R1 fails open:

• Solder bridge (short) across resistor R1:


• Solder bridge (short) across resistor R2:

• Capacitor C1 fails shorted:

For each of these conditions, explain why the resulting effects will occur.file 03890

50

Question 60

This circuit uses a ”555” integrated circuit to produce a low-frequency square-wave voltage signal (seenbetween the ”Out” terminal of the chip and ground), which is used to turn a pair of transistors on and offto flash a large lamp. Predict how this circuit will be affected as a result of the following faults. Considereach fault independently (i.e. one at a time, no multiple faults):

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

R1

R2

C1

Lamp

R3

Q1

Q2

• Transistor Q1 fails open (collector-to-emitter):

• Transistor Q2 fails open (collector-to-emitter):


• Transistor Q1 fails shorted (collector-to-emitter):


51

Question 61

What would happen to the operation of this astable 555 timer circuit if a resistor were accidentlyconnected between the ”Control” terminal and ground? Explain the reason for your answer.

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

R1

R2

C1

file 01435

Question 62

A student builds their first astable 555 timer circuit, using a TLC555CP chip. Unfortunately, it seemsto have a problem. Sometimes, the output of the timer simply stops oscillating, with no apparent cause.Stranger yet, the problem often occurs at the precise time anyone moves their hand within a few inches ofthe circuit board (without actually touching anything!).

What could the student have done wrong in assembling this circuit to cause such a problem? Whatsteps would you take to troubleshoot this problem?

file 01433

52

Question 63

Identify at least one component fault that would cause the final 555 timer output to always remain low:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

Inputpulse

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

(no pulse)

R1

C1

C2

R2R3

C3


53

Question 64

Predict how the operation of this sound-activated lamp circuit will be affected as a result of the followingfaults. Consider each fault independently (i.e. one at a time, no multiple faults):

Condensermicrophone

J Q

Q

C

K

VDD

VDD

L1

L2

Lamp

VDD

R1C1

R3

R2

R4

Q1

U1 U2

R5

Q2

D1

RLY1



• Diode D1 fails open:

• Transistor Q2 fails shorted between collector and emitter:

• Solder bridge past resistor R5:


54

Question 65

Identify at least one component fault that would cause the flip-flop to indicate ”clockwise” all the time,regardless of encoder motion:

Rotary encoder

LEDD

C

Q

QCW/CCW

R1 R2

VDD

Q1

Q2U1


Question 66

Identify at least one fault that would cause the motor to turn off immediately once the ”Start”pushbutton switch was released, instead of ”latch” in the run mode as it should:

L1 L2

M1

M1

Start StopM1

motor

To 3-phasepower source

F1

F2T1


55

Question 67

Ideal voltage sources and ideal current sources, while both being sources of electrical power, behave verydifferently from one another:

Current sources

V

Voltage sources

Explain how each type of electrical source would behave if connected to a variable-resistance load. Asthis variable resistance were increased and decreased, how would each type of source respond?

file 03226

Question 68

A very common sort of graph used in electronics work is the load line, showing all possibilities of loadvoltage and load current that a particular power source is able to supply to a load:

Vload

Iload

0

1

2

3

4

5

6

7

8

9

10

11

12

(mA)

0 1 2 3 4

(volts)

5 6 7 8 9 10 11 12

Power source

RinternalRloadVinternal

Each point on the load line representsthe output voltage and current for aunique amount of load resistance.

Note how the load line shows the voltage ”sag” of the power source in relation to the amount of currentdrawn by the load. At high currents, the output voltage will be very low (upper-left end of load line). Atlow currents, the output voltage will be near its maximum (lower-right end of load line). If all internalcomponents of the power source are linear in nature, the load line will always be perfectly straight.

Plot the load line for a power source having an internal voltage (Vinternal) of 11 volts and an internalresistance (Rinternal) of 1.2 kΩ. Superimpose your load line onto the load line graph shown above. Hint: itonly takes two points to define a line!

file 03513

56

Question 69

Give a step-by-step procedure for reducing this circuit to a Norton equivalent circuit (one current sourcein parallel with one resistor):

30 V

1 kΩ

2.2 kΩ

5 kΩ

1 kΩ

Load terminals

file 03230

Question 70

Suppose you had an AC/DC power supply, which performed as follows (open-circuit and loaded testconditions):

OnOff

Lamp

Switch

Switch off:

DC output

Vout = 14.3 volts DC

Iout = 0 mA DC

Switch on:V mA

Vout = 12.8 volts DC

Iout = 845 mA DC

Draw a Thévenin equivalent circuit to model the behavior of this power supply.file 03693

57

Question 71

Qualitatively determine the voltages across all components as well as the current through all componentsin this simple RC circuit at three different times: (1) just before the switch closes, (2) at the instant theswitch contacts touch, and (3) after the switch has been closed for a long time. Assume that the capacitorbegins in a completely discharged state:

R

C

R

C

switch closes:Before the At the instant of

switch closure:

R

C

has closed:Long after the switch

Express your answers qualitatively: ”maximum,” ”minimum,” or perhaps ”zero” if you know that to bethe case.

Before the switch closes:VC =VR =Vswitch =I =

At the instant of switch closure:VC =VR =Vswitch =I =

Long after the switch has closed:VC =VR =Vswitch =I =

Hint: a graph may be a helpful tool for determining the answers!file 01811

58

Question 72

Qualitatively determine the voltages across all components as well as the current through all componentsin this simple LR circuit at three different times: (1) just before the switch closes, (2) at the instant theswitch contacts touch, and (3) after the switch has been closed for a long time.

R R

switch closes:Before the At the instant of

switch closure:

R

has closed:Long after the switch

LLL

Express your answers qualitatively: ”maximum,” ”minimum,” or perhaps ”zero” if you know that to bethe case.

Before the switch closes:VL =VR =Vswitch =I =

At the instant of switch closure:VL =VR =Vswitch =I =

Long after the switch has closed:VL =VR =Vswitch =I =

Hint: a graph may be a helpful tool for determining the answers!file 01812

Question 73

What value of resistor would need to be connected in series with a 33 µF capacitor in order to providea time constant (τ) of 10 seconds? Express your answer in the form of a five-band precision resistor colorcode (with a tolerance of +/- 0.1%).

file 00436

59

Question 74

An electronic service technician prepares to work on a high-voltage power supply circuit containing onelarge capacitor. On the side of this capacitor are the following specifications:

3000 WVDC 0.75µF

Obviously this device poses a certain amount of danger, even with the AC line power secured (lock-out/tag-out). Discharging this capacitor by directly shorting its terminals with a screwdriver or some otherpiece of metal might be dangerous due to the quantity of the stored charge. What needs to be done is todischarge this capacitor at a modest rate.

The technician realizes that she can discharge the capacitor at any rate desired by connecting a resistorin parallel with it (holding the resistor with electrically-insulated pliers, of course, to avoid having to toucheither terminal). What size resistor should she use, if she wants to discharge the capacitor to less than 1%charge in 15 seconds? State your answer using the standard 4-band resistor color code (tolerance = +/-10%).

file 01525

Question 75

The following circuit allows a capacitor to be rapidly discharged and slowly charged:

Charge Discharge

15 V 2µ7

8k1

Suppose that the switch was left in the ”discharge” position for some substantial amount of time. Then,someone moves the switch to the ”charge” position to let the capacitor charge. Calculate the amount ofcapacitor voltage and capacitor current at exactly 45 milliseconds after moving the switch to the ”charge”position.

VC = @ t = 45 ms

IC = @ t = 45 msfile 03557

60

Question 76

Determine the capacitor voltage and capacitor current at the specified times (time t = 0 millisecondsbeing the exact moment the switch contacts close). Assume the capacitor begins in a fully discharged state:

Switch

20 V C = 15 µF

R = 4.7 kΩ

Time VC (volts) IC (mA)0 ms30 ms60 ms90 ms120 ms150 ms

file 03556

Question 77

Calculate the power factor of this circuit:

C = 0.1 µF

400 Hz32 V

R = 7.1 kΩ

file 02179

61

Question 78

An oscilloscope is connected to a low-current AC motor circuit to measure both voltage and current,and plot them against one another as a Lissajous figure:

A B Alt Chop Add

Volts/Div A

Volts/Div B

DC Gnd AC

DC Gnd AC

Invert Intensity Focus

Position

Position

Position

Off

Beam find

LineExt.

AB

ACDC

NormAutoSingle

Slope

Level

Reset

X-Y

Holdoff

LF RejHF Rej

Triggering

Alt

Ext. input

Cal 1 V Gnd Trace rot.

Sec/Div0.5 0.2 0.1

1

10

5

2

20

50 m

20 m

10 m

5 m

2 m

0.5 0.2 0.11

10

5

2

20

50 m

20 m

10 m

5 m

2 m

1 m5 m

25 m

100 m

500 m

2.51

250 µ50 µ

10 µ

2.5 µ

0.5 µ

0.1 µ0.025 µ

off

Rshunt

AC motor

The following Lissajous figure is obtained from this measurement:

From this figure, calculate the phase angle (Θ) and the power factor for this motor circuit.file 02183

62

Question 79

Some of the following transistor switch circuits are properly configured, and some are not. Identifywhich of these circuits will function properly (i.e. turn on the load when the switch closes) and which ofthese circuits are mis-wired:

Circuit 1 Circuit 2

Circuit 3 Circuit 4

Load Load

Load

Load

file 02326

63

Question 80

Choose the right type of bipolar junction transistor for each of these switching applications, drawingthe correct transistor symbol inside each circle:

Load

+V

+V

Switch sourcing currentto transistor Load

+V

Switch sinking currentfrom transistor

Transistor sinkingcurrent from load

current to loadTransistor sourcing

Also, explain why resistors are necessary in both these circuits for the transistors to function withoutbeing damaged.

file 02408

Question 81

The schematic diagram shown here is for a ”buck” converter circuit, a type of DC-DC ”switching” powerconversion circuit:

Drive circuit Vin

Load

In this circuit, the transistor is either fully on or fully off; that is, driven between the extremes ofsaturation or cutoff. By avoiding the transistor’s ”active” mode (where it would drop substantial voltagewhile conducting current), very low transistor power dissipations can be achieved. With little power wastedin the form of heat, ”switching” power conversion circuits are typically very efficient.

Trace all current directions during both states of the transistor. Also, mark the inductor’s voltagepolarity during both states of the transistor.

file 01102

64

Question 82

The schematic diagram shown here is for a ”boost” converter circuit, a type of DC-DC ”switching”power conversion circuit:

Drive circuit Vin

Load

In this circuit, the transistor is either fully on or fully off; that is, driven between the extremes ofsaturation or cutoff. By avoiding the transistor’s ”active” mode (where it would drop substantial voltagewhile conducting current), very low transistor power dissipations can be achieved. With little power wastedin the form of heat, ”switching” power conversion circuits are typically very efficient.

Trace all current directions during both states of the transistor. Also, mark the inductor’s voltagepolarity during both states of the transistor.

file 01103

65

Question 83

Determine the output voltage polarity of this op-amp (with reference to ground), given the followinginput conditions:

−

+

+V

-V

???−

+

+V

-V

???

−

+

+V

-V

???−

+

+V

-V

???

−

+

+V

-V

???

−

+

+V

-V

???

6 V

9 V

8 V

3 V

5 V

2 V

6 V

2 V

6 V

5 V

file 03762

66

Question 84

In this circuit, a solar cell converts light into voltage for the opamp to ”read” on its noninverting input.The opamp’s inverting input connects to the wiper of a potentiometer. Under what conditions does the LEDenergize?

−+

+V

LED

+V

file 00872

Question 85

Explain the operation of this sound-activated relay circuit:

−

+

Microphone

+V+V

Relay+V

-V

file 00879

67

Question 86

Assume that the comparator in this circuit is only capable of ”swinging” its output to within 1 volt ofits power supply rail voltages. Calculate the upper and lower threshold voltages, given the resistor valuesshown:

−

+

Vin

3.3 kΩ

1 kΩ

+10 V

-10 V

VUT = VLT =

file 02662

Question 87

A very common form of latch circuit is the simple ”start-stop” relay circuit used for motor controls,whereby a pair of momentary-contact pushbutton switches control the operation of an electric motor. Inthis particular case, I show a low-voltage control circuit and a 3-phase, higher voltage motor:

L1 L2

M1

M1

Start StopM1

motor

To 3-phasepower source

F1

F2

Explain the operation of this circuit, from the time the ”Start” switch is actuated to the time the ”Stop”switch is actuated. The normally-open M1 contact shown in the low-voltage control circuit is commonlycalled a seal-in contact. Explain what this contact does, and why it might be called a ”seal-in” contact.

file 01347

68

Question 88

A student decides to build a motor start/stop control circuit based on the logic of a NOR gate S-Rlatch, rather than the usual simple ”seal-in” contact circuit:

CR1Start

CR2

CR1

CR2Stop

Mtr

CR1

Power

The circuit works fine, except that sometimes the motor starts all by itself when the circuit is firstpowered up! Other times, the motor remains off after power-up. In other words, the power-up state of thiscircuit is unpredictable.

Explain why this is so, and what might be done to prevent the motor from powering up in the ”run”state.

file 01379

69

Question 89

The following schematic diagram shows a timer circuit made from a UJT and an SCR:

+V

LoadR1R2

R3 R4

C1

C2

Q1

CR1

Together, the combination of R1, C1, R2, R3, and Q1 form a relaxation oscillator, which outputs asquare wave signal. Explain how a square wave oscillation is able to perform a simple time-delay for theload, where the load energizes a certain time after the toggle switch is closed. Also explain the purpose ofthe RC network formed by C2 and R4.

file 03222

70

Question 90

Pulse Width Modulation, or PWM, is a very popular means of controlling power to an electrical loadsuch as a light bulb or a DC motor. With PWM control, the duty cycle of a high-frequency digital (on/off)signal is varied, with the effect of varying power dissipation at the load:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

Mtr

One of the major advantages to using PWM to proportion power to a load is that the final switchingtransistor operates with minimal heat dissipation. If we were to use a transistor in its linear (”active”)mode, it would dissipate far more heat when controlling the speed of this motor! By dissipating less heat,the circuit wastes less power.

Explain why the power transistor in this circuit runs cooler when buffering the PWM signal from the555 timer, rather than if it were operated in linear mode. Also, identify which direction the potentiometerwiper must be moved to increase the speed of the motor.

Challenge question: suppose we needed to control the power of a DC motor, when the motor’s operatingvoltage was far in excess of the 555 timer’s operating voltage. Obviously, we need a separate power supplyfor the motor, but how would we safely interface the 555’s output with the power transistor to control themotor speed? Draw a schematic diagram to accompany your answer.

file 01436

71

Question 91

It is common to see a capacitor connected between the ”Control” terminal and ground in 555 timercircuits, especially when precise timing is important.

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

R1

R2

C1 C2

Explain what purpose the capacitor C2 serves in this circuit.file 01434

Question 92

Special integrated circuits called delay elements or delay gates are manufactured to provide nanoseconds’worth of intentional time delays in digital circuits. Identify a part number for such an IC, research itsdatasheet, and describe an application where one might be needed.

file 02945

72

Question 93

Determine the final output states over time for the following circuit, built from D-type gated latches:

Q

QD

E

Q

QD

E

A

B

AVDD

Gnd

VDD

GndB

Output

VDD

GndOutput

At what specific times in the pulse diagram does the final output assume the input’s state? How doesthis behavior differ from the normal response of a D-type latch?

file 01363

73

Question 94

A common topology for DC-AC power converter circuits uses a pair of transistors to switch DC currentthrough the center-tapped winding of a step-up transformer, like this:

On

Off

On

Off

AC output

Note: protective devices to guard againsttransient overvoltages have been omittedfrom this diagram for simplicity!

In order for this form of circuit to function properly, the transistor ”firing” signals must be preciselysynchronized to ensure the two are never turned on simultaneously. The following schematic diagram showsa circuit to generate the necessary signals:

555Disch

Thresh

Trig

Gnd

Vcc RST

Out

Ctrl

+V

J Q

Q

C

K

−

+

+V

+V

To transistor #1

To transistor #2

Explain how this circuit works, and identify the locations of the frequency control and pulse duty-cyclecontrol potentiometers.

file 03452

74

Question 95

Although the toggle function of the J-K flip-flop is one of its most popular uses, this is not the onlytype of flip-flop capable of performing a toggle function. Behold the surprisingly versatile D-type flip-flopconfigured to do the same thing:

D

C

Q

QQ

Q

Explain how this circuit performs the ”toggle” function more commonly associated with J-K flip-flops.file 03453

75

Answers

Answer 1

The first circuit will ”latch” in whatever logic state it powers up in. The second circuit will be ”set”or ”reset” according to which pushbutton switch is actuated, then latch in that state when neither switch isbeing pressed. The resistor prevents the gate from ”seeing” a short circuit at its output when a pushbuttonswitch is actuated to change states.

Challenge question: how would you determine an appropriate size for the resistor? Don’t just guess –base your answer on specific performance parameters of the gate!

Answer 2

A latch is considered set when its output (Q) is high, and reset when its output (Q) is low.

Answer 3

Set Reset0

01

1 1

Q Q

0 1

0

1

1

0 0

0

0

Latch

Follow-up question: The final state of this truth table (where the ”Set” and ”Reset” inputs are bothhigh) is usually referred to as invalid. Explain why.

76

Answer 4

An ”active-low” input is one where that particular gate function is activated or invoked on a low logicstate. Active-low inputs are identified by inversion bubbles (or inversion wedges) drawn at the IC inputterminals. For example, the Enable input (EN) for the following integrated circuit is active-low, meaningthe chip is enabled when that input line is held at ground potential:

A

B

C

D

1

2

4

8

G

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

G015

EN

01

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Output

Active-lowenable input

This S-R latch circuit has active-low preset (PRE) and clear (CLR) inputs, meaning the latch circuitwill be preset and cleared when each of these inputs are grounded, respectively:

77

S Q

QR

PRE

CLR

preset input

clear input

Active-low

Active-low

Active-high inputs, conversely, engage their respective functions when brought to power supply rail(VDD or VCC) potential. As one might expect, an active-high input will not have an inversion bubble orwedge next to the input terminal.

Challenge question: to the surprise of many students, there are a great number of digital logic circuittypes built with active-low inputs. Explain why. Hint: most of these circuit types and functions werepioneered with TTL logic rather than CMOS logic.

78

Answer 5

Q

Q

Set

Reset

Set Reset0

01

1 1

Q Q

0 1

0

Latch

1 1

1 0

10

Follow-up question: why are the inputs referred to as Set and Reset, rather than just Set and Reset?

Answer 6

This is a bit of a trick question. If NOR and NAND are the only gate choices available, then the leftlatch is made from NOR gates and the right latch is made from NAND gates. However, it is possible tomake S-R latches out of gates other than NOR or NAND.

Challenge question: can you think of other gate types that could be used to build S-R latch circuits?Hint: there are at least two alternatives to NOR and NAND!

79

Answer 7

Start

Stop

VDD

Mtr

Follow-up question: why is the ”Stop” switch always normally-closed in motor control circuits, whetherit be relay logic or semiconductor logic? It is easy enough to invert a signal if we wish to, either by using arelay or by using a NOT gate, so shouldn’t the choice of switch ”normal” status be arbitrary?

Challenge question: why not operate the electric motor off the same VDD power source that the gatesare powered by? If we had to do such a thing, what circuit additions would you propose to minimize anypotential trouble?

Answer 8

The ”latching” ability of the S-R latch circuit holds the output state steady during the mechanicalswitch’s bouncing action, allowing a ”clean” output transition to take place.

Connecting the input probe of an oscilloscope to either the S or R input of the latch will show bounce,if it occurs. To capture this event, the ’scope would have to be configured for single-sweep mode, and havethe triggering controls properly set. A digital storage oscilloscope is essential for this type of work!

Follow-up question: how do you suggest choosing appropriate pull-down resistor sizes for this circuit,or any CMOS circuit for that matter?

80

Answer 9

SetActuated

Released

Actuated

Released

Reset

QHigh

Low

Time

Follow-up question: complete a schematic diagram showing how the Q output of the latch could turnon an electric motor through a bipolar junction transistor. Also, determine whether the latch circuit wouldbe sourcing or sinking current to the transistor when the motor is running:

VDD

S Q

QR

Set

Reset

VDD

Mtr

Answer 10

The circuit is fine, and working properly. The normal power-up state of a latch circuit is unpredictable,so long as both the inputs are inactive.

Answer 11

Whether the variable in question is increasing or decreasing over time, the expression e−t

τ describes thepercentage that a variable has left to change before it reaches its final value.

Follow-up question: what could you add to or modify about the expression to make it describe thepercentage that a variable has already changed from its initial value? In other words, alter the expressionso that it is equal to 0% at t = 0 and approaches 100% as t grows larger (t → ∞).

81

Answer 12

EC = 3.537 volts @ t = 9 seconds.

9 s = 1.915 time constants (1.915τ)

Answer 13

0.591 seconds

Answer 14

40 VDC C = 4.7 µF

R = 220 kΩSwitch

(electron flow)

+−

VC Time0 volts 0 ms10 volts 297.5 ms20 volts 716.7 ms30 volts 1.433 s40 volts > 5 s

Answer 15

Switch

(electron flow)12 V

R = 190 kΩ

C = 17 µF

VC Time10 volts 588.9 ms8 volts 1.31 s6 volts 2.24 s4 volts 3.55 s2 volts 5.79 s

82

Answer 16

When the output is high, the capacitor is charging through the two resistors, its voltage increasing.When the output is low, the capacitor is discharging through one resistor, current sinking through the 555’s”Disch” terminal.

Follow-up question: algebraically manipulate the equation for this astable circuit’s operating frequency,so as to solve for R2.

f =1

(ln 2)(R1 + 2R2)C

Challenge question: explain why the duty cycle of this circuit’s output is always greater than 50%.

Answer 17

tcharge = − ln 0.5(R1 + R2)C

tdischarge = − ln 0.5R2C

Answer 18

The diode allows part of the potentiometer’s resistance to be bypassed during the capacitor’s chargingcycle, allowing (potentially) less resistance in the charging circuit than in the discharging circuit.

To decrease the duty cycle, move the wiper up (toward the fixed resistor, away from the capacitor).

Challenge question: write an equation solving for the average current drawn by the 555 timer circuit asit charges and discharges the capacitor while generating a 50% duty cycle pulse. Assume that no current isdrawn from the power supply by the circuit while the capacitor is discharging, and use this approximationof the capacitor ”Ohm’s Law” equation for figuring average current through the charge cycle:

i = Cdv

dtTrue ”Ohm’s Law” for a capacitor

Iavg = C∆V

∆tCapacitive ”Ohm’s Law” solving for average current

Answer 19

The triggering pulse must dip below 13 of the supply voltage in order to initiate the timing sequence.

tpulse = 1.1RC

Answer 20

Each 555 timer’s cycle is triggered by the negative edge of the pulse on the trigger terminal. A passivedifferentiator network between each 555 timer ensures that only a brief negative-going pulse is sent to thetrigger terminal of the next timer from the output terminal of the one before it.

Follow-up question: when timer circuits are cascaded like this, do their time delays add or multiply tomake the total delay time? Be sure to explain your reasoning.

83

Answer 21

When the Enable input is low (0), the circuit ignores the Set and Reset inputs:

E S R Q Q0

1

0 0

0 0

0

0

1

1

1

1

0

0

1

1

1

1

1

0

1

0

1

0

LatchLatchLatchLatchLatch0 1

1 0

00

Answer 22

Q

QS

R

E

E S R Q Q0

1

0 0

0 0

0

0

1

1

1

1

0

0

1

1

1

1

1

0

1

0

1

0

LatchLatchLatchLatchLatch0 1

1 0

1 1

Follow-up question: explain why the inputs to the latch circuit are not active-low as they were beforethe addition of the two extra NAND gates. In other words, why does this latch now have S and R inputsrather than S and R inputs as it did before?

84

Answer 23

The ”Lockout” switch effectively disables the ”On” and ”Off” controls when it sends a ”low” signal tothe latch’s Enable input.

This circuit uses both a solid-state relay (SSR) and an electromechanical relay for interposing betweenthe latch and the lamp. These devices allow the low-power latch circuit to exert control over the high-powerlamp.

Here is one possibility for the door lock control:

S Q

QR

E

VDDLockout On

Off

L1 L2

SSR

Lamp

120 VAC

Control signalto solenoid

circuitry

Follow-up question: there are better (safer) ways to accomplish this same function. For instance, supposethe TRIAC inside the SSR were to fail shorted, maintaining power to the lamp even when the latch goesinto the ”reset” mode. Would the door-lock logic shown here prevent someone from opening the door andgetting exposed to the strong ultraviolet light? Explain your answer!

Challenge question: why not just use one interposing device: either an SSR, or an electromagnetic relay?Why both types of devices in the same circuit?

85

Answer 24

E Q Q0 0

0

01

1

1

1

DLatchLatch

1

1

0

0

ResetSet

Answer 25

Actuated

Released

Actuated

Released

QHigh

Low

Time

D

Enable

Follow-up question: complete a schematic diagram showing how this latch circuit could turn a motoron and off through a MOSFET.

VDDVDDD

Q

QD

E

Enable

Mtr

+−

Motorpowersource

Also, comment on whether your MOSFET sources current to the motor or sinks current from the motor.

86

Answer 26

Actuated

Released

Actuated

Released

QHigh

Low

Time

Enable

S Q

QR

E

S

Actuated

Released

R

Answer 27

When the Sample/Hold switch is in the ”low” position, the D latches all fall into the ”latch” state,holding that last valid input states on their Q outputs.

Answer 28

Inputs C1 and C2 perform the standard ”Enabling” function for the D-type latches within thisintegrated circuit. The 1EN and 2EN inputs control the tri-state outputs. Their ”wedge” symbols mean”complemented,” and are equivalent to the ”bubbles” seen on traditional gate symbols.

To make all sixteen latches enable and disable as one, bridge the enable inputs as such:

1EN

C1

2EN

C2

1D1D1 1Q11

OE

LE

. . .

87

Answer 29

D

E

Q

VDD

Gnd

VDD

Gnd

VDD

Gnd

Time

D

E

Q

VDD

Gnd

VDD

Gnd

VDD

Gnd

Time

Answer 30

Left-to-right is the correct driving direction for this street.

If sensor A’s light source fails, the alarm will never activate. A failed light source for sensor B will havedifferent effects on the system, depending on whether sensor A was sending a ”high” or a ”low” signal tothe latch circuit at the time B’s light source failed. I’ll let you figure out which way triggers the alarm!

88

Answer 31

InputOutput

InputGnd

VDD

NOT1 NOT2 NOT3

AND

NOT1Gnd

VDD

Gnd

VDD

Gnd

VDD

NOT2

NOT3

Gnd

VDD

AND

Follow-up question: describe exactly what conditions are necessary to obtain a ”high” signal from theoutput of this circuit, and what determines the duration of this ”high” pulse.

Answer 32

I’ll leave the experimental design details up to you. However, I will tell you that you do not necessarilyhave to use a digital storage oscilloscope to ”capture” a transient waveform to measure propagation delay, ifyou apply a little creativity. Hint: use a signal generator to send a high-frequency square wave to the gateof your choice, and use a non-storage oscilloscope to monitor the results.

And yes, electromechanical relays also have intrinsic delay times, which tend to be far greater thanthose encountered with semiconductor logic gates.

89

Answer 33

Q

QD

E

A

B

AVDD

Gnd

VDD

GndB

VDD

GndQ

VDD

GndQ

Q

QD

E

A

B

AVDD

Gnd

VDD

GndB

VDD

GndQ

VDD

GndQ

90

Follow-up question: one of these circuits is referred to as edge-triggered. Which one is it?

Challenge question: in reality, the output waveforms for both these scenarios will be shifted slightly dueto propagation delays within the constituent gates. Re-draw the true outputs, accounting for these delays.

Answer 34

A ”flip-flop” is a latch that changes output only at the rising or falling edge of the clock pulse.

Answer 35

The outputs of this device are allowed to change state only when the ”clock” signal (C) is transitioningfrom low to high:

S R Q Q

1

0 0

0

1

1 1

0 1

1

0

0

Latch

Invalid

C

Challenge question: what exactly happens in the ”invalid” state for this S-R flip-flop?

Answer 36

For the S-R gated latch:

• Set by making S high, R low, and E high.• Reset by making R high, S low, and E high.

For the S-R flip-flop:

• Set by making S high, R low, and C transition from low to high.• Reset by making R high, S low, and C transition from low to high.

91

Answer 37

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

S

R

C

Q

Q

S

R

VDD

GndC

Answer 38

Q Q

1

0 0

0

1

1 1

0 1

1

0

0

LatchC J K

Toggle

Follow-up question: comment on the difference between this truth table, and the truth table for an S-Rflip-flop. Are there any operational advantages you see to J-K flip-flops over S-R flip-flops that makes themso much more popular?

92

Answer 39

In either case, you cause the flip-flop to go into these three modes by doing the following:

• Set by activating J , deactivating K, and clocking C.• Reset by activating K, deactivating J , and clocking C.• Toggle by activating J and K simultaneously, and clocking C.

Specifically, though, here is what you would need to do to each flip-flop, stated in terms of ”high” and”low” logic states:

For the J-K flip-flop with active-high inputs:

• Set by making J high, K low, and C transition from low to high.• Reset by making K high, J low, and C transition from low to high.• Toggle by making J high, K high, and C transition from low to high.

For the J-K flip-flop with active-low inputs:

• Set by making K high, J low, and C transition from high to low.• Reset by making J high, K low, and C transition from high to low.• Toggle by making J low, K low, and C transition from high to low.

Answer 40

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

VDD

GndC

J Q

Q

C

K

J

K

93

Answer 41

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

D

C

Q

Q

D

C

94

Answer 42

VDD

Gnd

VDD

Gnd

VDD

GndQ

VDD

GndQ

VDD

GndC

J

K

J

C

K

Q

Q

Answer 43

”Asynchronous” inputs force the outputs to either the ”set” or ”reset” state independent of the clock.”Synchronous” inputs have control over the flip-flop’s outputs only when the clock pulse allows.

As for why the asynchronous inputs are active-low, I won’t directly give you the answer. But I will giveyou a hint: consider a TTL implementation of this flip-flop.

Answer 44

The flip-flop becomes ”set” every time a pulse comes from the sensor. The microprocessor must clearthe flip-flop after reading the captured pulse, so the flip-flop will be ready to capture and hold a new pulse.

Challenge question: what logic family of flip-flop would you recommend be used for this application,given the need for extremely fast response? Don’t just say ”TTL,” either. Research the fastest modern logicfamily in current manufacture!

Answer 45

The operation of this circuit is quite easy to understand if you draw a pulse diagram for it and analyzethe flip-flop’s output over time. When the encoder disk spins clockwise, the Q output goes high; whencounterclockwise, the Q goes low.

Follow-up question: comment on the notation used for this circuit’s output. What does the label”CW/CCW” tell you, without having to analyze the circuit at all?

95

Answer 46

Condensermicrophone

J Q

Q

C

K

VDD

VDD

L1

L2

Lamp

VDD

Answer 47

fout = 120 Hz

Follow-up question: how could you use another flip-flop to obtain a square-wave signal of 60 Hz fromthis circuit?

Answer 48

The clock frequency must be slow enough that there is adequate set-up time before the next clock pulse.The propagation delay time of FF1 must also be larger than the hold time of FF2. And, of course, the pulsewidth of the clock signal must be long enough for both flip-flops to reliably ”clock.”

Answer 49

I’ll let you do the research on this question!

Answer 50

With all inputs tied together, there is zero setup time on the J and K inputs before the clock pulserises.

Answer 51

Use circuit simulation software to verify your predicted and actual truth tables.

Answer 52

Use circuit simulation software to verify your predicted and measured parameter values.

Answer 53

Use circuit simulation software to verify your predicted and actual truth tables.

Answer 54

Use circuit simulation software to verify your predicted and measured parameter values.

96

Answer 55

I do not provide a grading rubric here, but elsewhere.

Answer 56

Be sure to document all steps taken and conclusions made in your troubleshooting!

Answer 57

• Resistor R3 failed open.

• NOR gate U1 output failed low.

• Resistor R1 failed open (provided enough ambient electrical noise to activate a floating gate input).

• ”Set” switch contacts failed shorted.

Answer 58

• NOR gate U2 output failed high.

• Wire break between ”Reset” switch and resistor R2 (although if this was the only fault it may allow theQ LED to energize at power-up, just not de-energize after the ”Set” button had been pressed).

Follow-up question: explain why the nature of the problem rules out the possibility of the only faultbeing something related to the feedback connections between U1 and U2.

Answer 59

• Resistor R1 fails open: Capacitor voltage holds at last value, output voltage holds at last value.

• Solder bridge (short) across resistor R1: Timer IC will become damaged at the first discharge cycle.

• Resistor R2 fails open: Capacitor voltage holds at last value, output voltage holds at last value.

• Solder bridge (short) across resistor R2: Oscillation frequency nearly doubles, and the duty cycle increasesto nearly 100%.

• Capacitor C1 fails shorted: Capacitor voltage goes to 0 volts DC, output voltage stays ”high”.

Answer 60

• Transistor Q1 fails open (collector-to-emitter): Lamp remains off, no current through any terminal ofQ2.

• Transistor Q2 fails open (collector-to-emitter): Lamp remains off, no current through any terminal ofQ2, normal base current through Q1, no current through collector of Q1.

• Resistor R3 fails open: Lamp remains off, no current through any terminal of Q1 or Q2.

• Transistor Q1 fails shorted (collector-to-emitter): Lamp remains on, full ”on” current levels throughterminals of Q1 and Q2.

97

Answer 61

The addition of a resistor between the Control terminal and ground would increase the frequency ofthe circuit, as well as decrease the peak-to-peak amplitude of the ”sawtooth” wave signal across the timingcapacitor.

Follow-up question: does the addition of this resistor affect the output signal (pin 3) amplitude as well?Explain why or why not. If it amplitude is affected, does it increase or decrease with the resistor in place?

Answer 62

I won’t reveal the most probable cause, but I will give you this hint: the TLC555CP integrated circuit(”chip”) uses CMOS technology.

Answer 63


• Solder bridge past resistor R2.

• No power to either 555 timer IC.

Answer 64

• Resistor R1 fails open: Lamp status does not change.

• Resistor R3 fails open: Lamp status does not change.

• Diode D1 fails open: Circuit works fine for a few cycles, then fails with the lamp either remaining onor remaining off (due to failed transistor Q2).

• Transistor Q2 fails shorted between collector and emitter: Lamp remains on.

• Solder bridge past resistor R5: Possible failure of flip-flop U2 or transistor Q2 after extended periods oftime with the lamp on.

Answer 65

• Phototransistor Q1 failed shorted.


• Flipflop U1 output failed high.

Follow-up question: explain why the presence of ambient light near the phototransistors could also causethis problem to occur.

Answer 66

• M1 control contact failed open.

• Wire(s) between M1 control contact and control circuit broken open.

Answer 67

An ideal voltage source will output as much or as little current as necessary to maintain a constantvoltage across its output terminals, for any given load resistance. An ideal current source will output asmuch or as little voltage as necessary to maintain a constant current through it, for any given load resistance.

98

Answer 68

Vload

Iload

0

1

2

3

4

5

6

7

8

9

10

11

12

(mA)

0 1 2 3 4

(volts)

5 6 7 8 9 10 11 12

eltr 145 (digital 2), section 1 recommended schedule · eia raising the standard; electronics...

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