ELEN 468 Lecture 18 1

ELEN 468Advanced Logic Design

Lecture 18MIPS Microprocessor

ELEN 468 Lecture 18 2

Computer Architecture

CISC Complex Instruction Set Computer Intel’s x86, Motorola’s 680x0

RISC Reduced Instruction Set Computer Any computer architecture defined after 1984 MIPS

Microcomputer without Interlocked Pipeline Stages Millions of Instructions Per Second Strongly pipelined architecture DEC’s Alpha, HP’s Precision

ELEN 468 Lecture 18 3

Registers 32 32-bit (word) registers $a0 - $a3: argument registers $v0 - $v1: return values $ra: return address register $sp: stack pointer $fp: frame pointer $gp: global pointer $zero: always equals 0 $s0 - $s7: preserved on a procedural call $t0 - $t9: not preserved by callee on a

procedural call

ELEN 468 Lecture 18 4

Arithmetic Operations

add a, b, c # a = b + c add $t0, $s1, $s2 sub a, b, c # a = b – c sub $s0, $t0, $t1

Arithmetic operations occur only on registers

ELEN 468 Lecture 18 5

Data Transfer

lw $t0, 8($s3) # load $t0 with data from memory

# base address in $s3, offset 8 sw $t0, 48($s3) # store word

101

110

10

1001

Address

Memory

0

4

8

12

… …Byte – 8 bits

Word – 32 bits

Memory in words

Address to byte level

ELEN 468 Lecture 18 6

MIPS Fields

op: basic operation, also called opcode rs: the first register source operand rt:

R-type: the second register source operand I-type: destination register

rd: the register destination operand shamt: shift amount in shift instructions funct: selects the specific variant of the operation in op field, also called function code address: offset of memory address in data transfer instructions

op rs rt rd shamt funct

op rs rt address

R-type

I-type

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

ELEN 468 Lecture 18 7

Examples of Machine Code

op rs rt rd shamt

funct

op rs rt address

0 18 19 17 0 32

0 18 19 17 0 34

35 18 17 100

43 18 17 100

add $s1, $s2, $s3

sub $s1, $s2, $s3

lw $s1, 100($s2)

sw $s1, 100($s2)

ELEN 468 Lecture 18 8

Some Other Instructions

beq $s3, $s4, L1 # go to branch L1, if equal bne $s3, $s4, L1 # go to branch L1, if not equal j L1 # jump to branch L1 jr $t0 # jump based on $t0 slt $t0, $s1, $s2 # set value of $t0 to 1, if less than sll $t2, $s0, 8 # reg $t2 = reg $s0 << 8 bits srl $t2, $s0, 8 # reg $t2 = reg $s0 >> 8 bits addi $sp, $sp, 4 # $sp = $sp + 4 nop # do nothing

ELEN 468 Lecture 18 9

MIPS Addressing Mode

Register addressing: the operand is a registerBase or displacement addressing: the operand is at the memory whose address is the sum of a register and a constantImmediate addressing: the operand is a constantPC (Program Counter)-relative addressing: address is the sum of PC and a constant in the instruction

ELEN 468 Lecture 18 10

Steps for MIPS Instructions

1. Fetch instruction from memory2. Read registers while decoding the

instruction3. Execute the operation or

calculate an address4. Access an operand in data

memory (for lw and sw)5. Write the result into a register

ELEN 468 Lecture 18 11

Implement Instruction Fetch

PC

4

Add

Read address

Instruction

Instruction memory

ELEN 468 Lecture 18 12

Datapath for R-type Instructions

Instruction

Read register 1

Read register 2

Write register

Write data

5

5

5

Read data 2

Read data 1

Registers

32

32

Reg_write

Control

32Result

ALU

ELEN 468 Lecture 18 13

Example of Instruction Execution Time

Instruction

Instruction fetch

Register read

ALU operatio

n

Memory

access

Register write

Total time

lw 2 1 2 2 1 8

sw 2 1 2 2 7

R-format (add, sub)

2 1 2 1 6

Branch 2 1 2 5

ELEN 468 Lecture 18 14

Unpipelined vs. Pipelined

lw $t1, 8($s1)

lw $t2, 16($s2)

lw $t3, 12($s3)

2 4 6 8 10

12

14

16

18

IF ID ALU MEM WB

IF ID ALU MEM WB

IF

lw $t1, 8($s1)

lw $t2, 16($s2)

lw $t3, 12($s3)

IF: Instruction fetchID: Instruction decode

and read registerALU: Execution or

address calculation

MEM: Memory accessWB: Write back to reg

IF ID ALU MEM WB

IF ID ALU MEM WB

IF ID ALU MEM WB

ELEN 468 Lecture 18 15

Instruction Sets for Pipelining

All instructions have the same lengthThere are only a few instruction formatsMemory operands only appear in loads or storesOperands must be aligned in memory

ELEN 468 Lecture 18 16

Pipeline Hazards

Situations when the next instruction cannot execute in the following clock cycle Structural hazards Control hazards Data hazards

ELEN 468 Lecture 18 17

Structural Hazards

Hardware cannot support the combined instructions that we want to execute in the same clock cycleExample: if there is only one memory, then memory access and instruction fetch cannot be executed simultaneouslySolution: add hardware

ELEN 468 Lecture 18 18

Control Hazards

Decision-making depends on the result of an instruction that has not been finishedExample: PC following a branch instruction depends if branch is taken or notSolutions Predict: execute next instruction anyway, if

branch is taken, retract the decision Dynamic prediction based on smart guess

ELEN 468 Lecture 18 19

Data Hazards

An instruction cannot be executed until a data is available from another instructionExample: add $s0, $t1, $t2

sub $t2, $s0, $t3Solution: Bypassing: result can be fed to next

instruction execution without loading to a register