ELEN 468 Lecture 8 1

ELEN 468Advanced Logic Design

Lecture 8 Behavioral Descriptions II

ELEN 468 Lecture 8 2

Procedural Timing Control

Delay controlEvent controlNamed events“wait” construct

ELEN 468 Lecture 8 3

Delay Control Operator (#)

initialbegin#0 in1 = 0; in2 = 1;#10 in3 = 1;#40 in4 = 0; in5 = 1;#60 in3 = 0;end

initialbegin#0 in1 = 0; in2 = 1;#10 in3 = 1;#40 in4 = 0; in5 = 1;#60 in3 = 0;end

ELEN 468 Lecture 8 4

Event Control Operator (@)

…@ ( eventA or eventB )

begin … @ ( eventC ) begin … endend

…@ ( eventA or eventB )

begin … @ ( eventC ) begin … endend

Event -> identifier or expressionWhen “@” is reached

Activity flow is suspended The event is monitored Other processes keep going

posedge: 0->1, 0->x, x->1negedge: 1->0, 1->x, x->0Cannot assign value to the event variable inside the synchronized behavior

ELEN 468 Lecture 8 5

Named Eventmodule modA (…);… event sth_happens; //

declaration always

…->sth_happens; // trigger eventend

endmodule

module modB(…);… always @

(top_mod.modA.sth_happens)…

endmodule

module modA (…);… event sth_happens; //

declaration always

…->sth_happens; // trigger eventend

endmodule

module modB(…);… always @

(top_mod.modA.sth_happens)…

endmodule

Also called abstract eventDeclared only in module with keyword eventMust be declared before it is usedEvent is triggered by “->”Provide high level inter-module communication without physical details

ELEN 468 Lecture 8 6

Example of Named Eventmodule flop_event ( clk, reset, data, q,

q_bar );input clk, reset, data;output q, q_bar;reg q;event up_edge;

assign q_bar = ~q;

always @ ( posedge clk ) -> up_edge;

always @ ( up_edge or negedge reset ) begin

if ( reset == 0 ) q = 0; else q = data; end

endmodule

module flop_event ( clk, reset, data, q, q_bar );input clk, reset, data;output q, q_bar;reg q;event up_edge;

assign q_bar = ~q;

always @ ( posedge clk ) -> up_edge;

always @ ( up_edge or negedge reset ) begin

if ( reset == 0 ) q = 0; else q = data; end

endmodule

ELEN 468 Lecture 8 7

The “wait” Construct

module modA (…);…

always begin … wait ( enable ) ra = rb; … end

endmodule

module modA (…);…

always begin … wait ( enable ) ra = rb; … end

endmodule

Activity flow is suspended if expression is falseIt resumes when the expression is trueOther processes keep going

ELEN 468 Lecture 8 8

Intra-assignment Delay: Blocking Assignment

// B = 0 at time 0// B = 1 at time 4…#5 A = B; // A = 1C = D;…A = #5 B; // A = 0C = D;…A = @(enable) B;C = D;…A = @(named_event) B;C= D;…

// B = 0 at time 0// B = 1 at time 4…#5 A = B; // A = 1C = D;…A = #5 B; // A = 0C = D;…A = @(enable) B;C = D;…A = @(named_event) B;C= D;…

If timing control operator(#,@) on LHS Blocking delay RHS evaluated at (#,@) Assignment at (#,@)

If timing control operator(#,@) on RHS Intra-assignment delay RHS evaluated

immediately Assignment at (#,@)

ELEN 468 Lecture 8 9

Intra-assignment Delay: Non-blocking Assignment

always begin @ ( posedge clk )

G <= @ (bus) acc; C <= D; // not blockedend

always begin @ ( posedge clk )

G <= @ (bus) acc; C <= D; // not blockedend

Sampling RHS immediately in the latest cycleWait for time control to execute assignmentSubsequent assignments are not blocked

In 1st cycle, “acc” is sampledWhat if no “bus” change in the same cycle?In next cycle, “acc” is sampled againValue of “acc” from previous cycle is overwrittenWarning message

ELEN 468 Lecture 8 10

Be Cautious

module or8( y, a, b );

input [7:0] a, b; output [7:0] y; reg [7:0] y;

initial begin assign y = a | b; endendmodule

module or8( y, a, b );

input [7:0] a, b; output [7:0] y; reg [7:0] y;

initial begin assign y = a | b; endendmodule

Model combinational logic by one-shot (initial) behaviorValidNot preferredNot accepted by synthesis tool

ELEN 468 Lecture 8 11

Example

initial begin a = #10 1; b = #2 0; c = #3 1; end

initial begin d <= #10 1; e <= #2 0; f <= #3 1; end

initial begin a = #10 1; b = #2 0; c = #3 1; end

initial begin d <= #10 1; e <= #2 0; f <= #3 1; end

t a b c d e f 0 x x x x x x 2 x x x x 0 x 3 x x x x 0 110 1 x x 1 0 112 1 0 x 1 0 115 1 0 1 1 0 1

ELEN 468 Lecture 8 12

Tell the Differences

always @ (a or b) y = a|b; always @ (a or b) #5 y = a|b;

always @ (a or b) y = #5 a|b;

always @ (a or b) y <= #5 a|b;

always @ (a or b) y = a|b; always @ (a or b) #5 y = a|b;

always @ (a or b) y = #5 a|b;

always @ (a or b) y <= #5 a|b;

Event control is blocked

Which one describes or gate?

ELEN 468 Lecture 8 13

Simulation of Assignments

For each given time step Evaluate all Right-Hand-Side Execute blocking assignment Execute non-blocking assignment that do

not have intra-assignment timing control Execute past non-blocking assignment that

is scheduled at this time Execute $monitor. However, $display is

executed whenever it is encountered. Increment time step

ELEN 468 Lecture 8 14

Simulation of Non-blocking Assignment

Normally the last assignment at certain simulation time stepIf it triggers other blocking assignments, it is executed before the blocking assignment it triggers

always … begin A <= B; end …always … begin C = @(A) D; end

always … begin A <= B; end …always … begin C = @(A) D; end

ELEN 468 Lecture 8 15

Example

initial begin a = 1; b = 0; a <= b; b <= a; $display(“a=%b b=%b”, a, b);end

initial begin a = 1; b = 0; a <= b; b <= a; $display(“a=%b b=%b”, a, b);end

initial begin a = 1; b = 0; a <= b; b <= a; $monitor(“a=%b b=%b”, a, b);end

initial begin a = 1; b = 0; a <= b; b <= a; $monitor(“a=%b b=%b”, a, b);end

a=1 b=0 a=0 b=1

ELEN 468 Lecture 8 16

Repeated Intra-assignment Delay

regA = repeat (5) @ ( negedge clk ) regB;regA = repeat (5) @ ( negedge clk ) regB;

begin tmp = regB; @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); regA = tmp;end

begin tmp = regB; @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); @ ( negedge clk ); regA = tmp;end

ELEN 468 Lecture 8 17

Indeterminate Assignmentmodule multi_assign();

reg a, b, c, d;initial begin #5 a = 1; b = 0; endalways @ ( posedge a ) begin c = a;

endalways @ ( posedge a ) begin c = b;

endalways @ ( posedge a ) begin d = b;

endalways @ ( posedge a ) begin d = a;

endendmodule

module multi_assign();reg a, b, c, d;initial begin #5 a = 1; b = 0; endalways @ ( posedge a ) begin c = a;

endalways @ ( posedge a ) begin c = b;

endalways @ ( posedge a ) begin d = b;

endalways @ ( posedge a ) begin d = a;

endendmodule

Multiple assignments are made to same variable in different behaviorValue depends on code order or vendor specificationsSimilar to race-conditions in hardware