elements of fpgas-what design engineers need to know

7/30/2019 Elements of Fpgas-What Design Engineers Need To Know

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Welcome

Elements of FPGA:What Design Engineers Need To Know


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Basic FPGA Structures

System Design Considerations

Tools and Design Flow

Lattice FPGAs


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FPGA Field Programmable Gate Array

Customizable IC that isASIC alternative

High capacity andperformance suitablefor SOC

No Mask Cost Configurable after

manufacture

Quick designimplementation and

revision From-stock delivery

Shared volume pricing


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Major Elements of an FPGA

Array of Logic Blocks(not simply gates)

Programmable

Interconnect

I/O

System elements

Serial I/O

Memory

Processor/CPU

MAC/DSP


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FPGA Logic Cells

Many different names (LE, LC)

LUT (look up table)

3-6 inputs

MUX (multiplexer)

Extends LUT input range

Register/Latch/Storage

Synchronous design

Other elements vary with

vendorFast carry logic

Full adder

Counter

Shift Register


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Replaces what once really were gates

3-6 inputs

Output determined by truth table

LUT Provides Combinatorial Logic

a b c d y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 01 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1


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LUT Implies Memory

4-input LUT gives 16-bit storage

Combine LEs for various

configurationsNxM single port RAM

Nx(M/2) dual port RAM

NMx1 single port RAM

ROM

Etc.


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Programmable Logic Hierarchy

Necessary to reduce interconnectoverhead (more later)

Terminology varies with vendor

and generation

Logic Cell

One LUT and latch

Slice

Two or more tightly-

interconnected logic cells

May include additional MUX Logic Block

Locally interconnected slices

Largest tightly-connected unit


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and generation

Logic Cell

One LUT and latch

Slice



May include additional MUX Logic Block





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and generation

Logic Cell

One LUT and latch

Slice



May include additional MUX

Logic Block





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Dedicated memory structures (versus LUT)

For larger/faster memory needs

Configurable

Width/depth Type (single/dual port)

Amount varies with vendor and device

Embedded Memory Blocks


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General purpose I/O Configurable single-ended/differential

Configurable logic level

Configurable input termination

Configurable edge rate

SERDES

For high-speed serial protocols

Includes PHY

Includes PCS

Physical coding sub-layer, i.e., 8b/10b, etc.

Analog

Specialty devices that also include ADC/DAC, etc.

Input/Output


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Multiply and Accumulate (MAC)

Supports DSP functionality

Depth, resolution vary by

vendor


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For complex, relatively slow operations

Often industry-standard architecture like ARM

Varies by vendor

Processor Core


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Programmable Interconnect


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S =

Programmable Interconnect


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Interconnection Hierarchy

Local to global

Within a slice to

across the chip

Balances loading, trace

length/delay, connectivity

Part of vendor secret

sauce


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Power/speed/cost/density

Overhead in FPGA compared to ASIC in same process

Generally only a generation behind

Device power

Typically different voltage needs for core, I/O

FPGA Configuration

RAM-based

Flash-based

Antifuse

FPGA Architecture

System Design Considerations


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RAM-based FPGA

SRAM stores configuration

Quick programming and

reprogramming in circuit

Volatile (needs power to

maintain configuration)

Typically needs

supporting device for

configuration storage

Configuration data accessible


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Flash-based FPGA

EEPROM stores configuration

Non-volatile

Can be programmed off-

board

Slower programming and

reprogramming in circuit

Needs additional

programming voltage

Configuration data more secure

Requires effort to extract


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Antifuse-based FPGA

Antifuse is insulator you

burn out to make

conductive

Non-volatile

One-time programmableonly, off board

Configuration data secure

Needs electron

microscope to probe


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Other FPGA Architectural Features to

Consider

Granularity

Block size and embedded IP affect complexity, speed,

utilization tradeoffs

Embedded Memory Block size and placement, memory structure (multiport)

affect speed

Power Control

Reduce average power by shutting down circuits not in use

Clock Distribution/Domains

Affects design flexibility, skew, power (via clock gating)


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Forget about the underlying logic details (mostly)

Tools handle the fine details Be prepared to override/force choices tools make

Design at high level

Verilog, VHDL

MathLab

Schematic capture (mostly block level)

Use IP libraries

Pre-designed common functions

Vendor and 3rd party supplied

Your companys unique IP

Soft vs Firm IP

Soft is circuit description only

Firm includes implementation constraints

Designing with FPGAs


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Design Capture Place and Route

Timing and

Functional

Simulation

Program andTest in-circuit

Design Tools and Flow

Many 3rd-partytools available

Vendor-specifictools

May need toOver-ride P&R

Burn and Turn


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Mid-Range Low Density Mixed Signal

Intellectual

Property (IP)

Development

Boards

Design

Software

SRAM AND Flash-Based Programmable Solutions

i C 3 S d G


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3rd Generation Value-based FPGA

65nm SRAM Process

1.2v Core Voltage

17K to 150K LUTs

Up to 7Mb Embedded RAM

16 Channels SERDES, ~110mW/Channel 250Mbps to 3.2Gbps Data Rates

Supports PCIe, CPRI, GbE, XAUI, SMPTE

High Performance I/Os 1Gbps LVDS, DDR1/2/3

Full DSP Blocks up to 320 18x18 Multipliers

Bank6

Bank7

Bank 0 Bank 1 Bank8

SERDES

Bank2

Bank3

Bank

Bank

Bank BankBank

SERDES

Bank

Bank

330MHz Fabric 3.2Gbps SERDES >400MHz DSP Blocks 1Gbps I/Os

Lowest power SERDES- enabled FPGA

LatticeECP3: SRAM Based FPGA


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MACHXO2: Low-Cost, Low-Power Flash-based FPGA

Low cost

65-nm embedded Flash process Cost optimized architecture

Low power

As low as 19uW

High system integration 256 to 7K LUT logic density

Up to 240K bits embedded memory

User Flash memory

Hardened I2C, SPI, timer/counter

Saves up to 600LUTs THE DO-IT-ALL PLD

C O G S G OO


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LATTICE DIAMOND FPGA DESIGN TOOL

Built on existing foundation for cost sensitive,low power applications

Key new features

Design exploration, Ease of use, Design flow

improvement Enhancements across all integrated tool views


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Summary

You are now ready to explore your own FPGA design

We covered

FPGA Silicon Features

Software Capabilities

Associated Embedded and Soft IPs

For more details on Lattice products:

www.latticesemi.com

Co-sponsors site with ECP3/XO2 promotional offers: www.em.avnet.com/latecp3offer

www.em.avnet.com/latmachxo2
http://www.latticesemi.com/http://www.em.avnet.com/latecp3offerhttp://www.em.avnet.com/latmachxo2http://www.em.avnet.com/latmachxo2http://www.em.avnet.com/latecp3offerhttp://www.latticesemi.com/

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