electronic pack….. chapter 4 components for electronic systems slide 1 chapter 4 components for...

Electronic Pack….. Chapter 4

Components for Electronic Systems Slide 1

Chapter 4 Components for Electronic Systems

• Description of geometrical, thermal and some electrical properties of main types of components. No description of electrical properties of monolithic circuits.

The course material was developed in INSIGTH II, a project sponsored by the Leonardo da Vinci program of the European Union



Hole Mounted Resistors

•Mature design, fig. 4.1:–Carbon composite (a)–Metal film (b)–Wire wound (c)



Surface Mounted Resistors

• Fig.4.2.a: Thick film layers on ceramic substrate, rectangular shape




Fig. 4.2 b): Metal system for termination on SMD resistors.




Fig. 4.2 c): MELF-resistors have cylindrical body.(MELF is acronym for Metal Electrode Face Bonding)




• Table 4.1: Properties of SMD resistorsTable 4.1. Properties of SMD resistors (Philips).Resistance range and tolerance 10 ohm to 1 Mohm (E24* series) ± 2%

1 ohm to 10 Mohm (E24 series) ± 5%1 ohm to 10 Mohm (E12 series) ±10%

Dimensions 3,2 x 1,6 x 0,6 mmOperating temperature range -55°C to + 155°CTemperature coefficient (-40°C to 125°C) <+200 x 10-6/KAbsolute max. dissipation at Tamb= 70°C 0,25 W

Maximum permissible voltage 200 V (r.m.s.)Climatic category (IEC68) 55/155/56Jumper resistance = 50 mohmMaximum current 2 A*See Table 4.2




• Table 4.2: The resistance series E24, 12 and 6

Table. 4.2: The resistance series E24, E12 and E6. The numbers mean that forexample in series E6 there are 6 resistance values for each decade: 10,15, 22, 33, 47 and 68 x10n ohms.

E24 10 11 12 13 15 16 18 20 22 24 27 30 33 36 39 43 47 51 56 62 68 75 82 91

E12 10 12 15 18 22 27 33 39 47 56 68 82

E6 10 15 22 33 47 68



Hole Mounted Resistors

• Coding: Color Value MultiplierTolerance

(%)

Black 0 0 -

Brown 1 1 ±1

Red 2 2 ±2

Orange 3 3 ±0.05

Yellow 4 4 -

Green 5 5 ±0.5

Blue 6 6 ±0.25

Violet 7 7 ±0.1

Gray 8 8 -

White 9 9 -

Gold - -1 ±5

Silver - -2 ±10

None - - ±20



Capacitors• In addition the capacitance, the following properties are

important:• Maximum voltage rating

• Temperature dependence of the capacitance (temperature coefficient)

• Loss tangent (tan δ), see below

• Equivalent series resistance

• Long term stability and ageing phenomena

• High frequency properties

• Leakage current

• Ability to withstand various production processes (high temperature, etc.)

• Price, physical size, etc.

• Web: www.interq.or.jp/japan/se-inoue/e_capa.htm

http://www.interq.or.jp/japan/se-inoue/e_capa.htm



Capacitors, continued• Main types:

–Ceramic multilayer–Electrolytic dry, polarized–Electrolytic, wet, polarized–Metallized plastic film–Mica

http://www.answers.com/main/ntquery;jsessionid=176lt15pg6lan?method=4&dsname=Wikipedia+Images&dekey=Dielectric.png&gwp=8&sbid=lc07a



Capacitors, continued

• Electrical model:C = (o r • A) /d

| Z | = [ Rs

2 + (L - 1/C)2]1/2

Rs = series resistance (Rp neglected),L = inductance, fig. 4.5

Resonance frequency will be when:

L = 1/C

Loss tangent:

tan = R / | Im Z | = { Rp + Rs [1+ (CRp)2 ]} / [ CRp2 - L (1+ (CRp)2]

Rp

L RsC

A = electrode area

d= electrode distance

C



Capacitors, continued• Fig. 4.3: Electrical

equivalent model for capacitor. If Rp can be neglected the impedance is given by:

| Z | = [Rs2 + (L - 1/C)2]1/2

• Fig. 4.4: The frequency dependence of impedance for multilayer ceramic capacitors (below) and tantalum electrolytic capacitors (top), all having 100 nF capacitance value.

Rp

L RsC




Fig. 4.5: Frequency dependence of the loss tangent tan schematically.

tan = R / |Im Z | = [Rp + Rs ( 1+ ( CRp)2) ] / ( CRp2 - L (1+ ( CRp)2) ]



Capacitors, continued• Multilayer Ceramic Capacitors

Fig. 4.7.a: SMD Multilayer Ceramic Capacitor

Fig. 4.7.b: Metal system for the endtermination of multilayer ceramic capacitors.



Multilayer Ceramic Capacitor, continued

• Class 1: Low capacitance, good electrical properties, types NP0, N220, N750, COG, etc.

• Class 2: High capacitance, poorer electrical behaviour, types X7R, Z5U

Fig. 4.8: Relative dielectric constant for ferroelectric ceramic compositions (class 2), as a function of temperature, near the Curie point



Multilayer Ceramic Capacitors, continued

Fig. 4.9: Properties of dielectrics of the types NP0, X7R and Z5U in SMD ceramic multilayer capacitors.

Top: The voltage dependence of capacitance.

Middle: Loss tangent as function of temperature.

Bottom: The temperature coefficient of the capacitance (Philips).



Multilayer Ceramic Capacitors, continued

Fig. 4.10: Crack formation because of thermal stress in ceramic capacitors



Capacitors, continued• Tantalum, Dry Electrolytic–Very high capacitance, low voltages, low leakage current

Fig. 4.11 a): Tantalum SMD electrolytic capacitor (Philips), and hole mounted tantalum capacitors (Siemens) Tantalum oxide is Ta2O5.



Capacitors, continued• Electrolytic Capacitors – why they are polarised:

– The capacitance is the oxidised surface of the anode– Reversed polarity will remove the oxide by reduction reaction

at the anode and loss of dielectric isolation leading to short-circuiting

Fig. 4.11 a): Tantalum SMD electrolytic capacitor (Philips), and hole mounted tantalum capacitors (Siemens)




• Tantalum, Dry Electrolytic

Fig. 4.11 b): Electrical properties of dry tantalum electrolytic capacitors. (Data from Philips)

Dissipation factors vary with temperature: Maximum values which are not exceeded by any capacitorare as follows.

Temperature -55 C 25 C 85 C 125 CRated Voltage 4 to 10 V d.c. 10% 12% 12% 12%Rated Voltage 15 to 50 V d.c. 8% 6% 6% 6%

The d.c. leakage current (at rated voltage) is within the limit set below

25 C < 0,01 µA/µF V or < 1 µA whichever is greater85 C < 0,10 µA/µF V or < 10 µA whichever is greater125 C < 0,125 µA/µF V or < 12,5 µA whichever is greater



Wet Electrolytic Aluminium Capacitors

Fig. 4.12 a): Aluminium electrolytic capacitor for SMD mounting. (From Philips)



Wet Electrolytic Aluminium Capacitors

Fig. 4.12 b): Aluminium electrolytic capacitor properties (Philips).

Top: Temperature dependence of the capacitance, relative to the value at 20 °C.

Middle: Temperature dependence of tan

Bottom: Temperature dependence of impedance at a frequency of 10 kHz.



Diodes and Transistors

Fig. 4.13: Axial, plastic encapsulated, hole mounted diodes to the left. Centre: A plastic can with metal base for power diodes. It can be hole mounted or surface mounted, depending on how the leads are bent. The base is screwed to the substrate. Right: A higher power diode in a metal can. Screw mounted to the substrate for efficient thermal contact.



Diodes and Transistors, continued

Fig. 4.14: Various types of hole mounted transistor packages: a) Left: Plastic packages, b) Centre: Low power metal packages c) Right: Metal package for high power transistors. For the high power package, the collector is connected to the metal body.



Diodes and Transistors , continued

Fig. 4.15: MELF-package for SMD diodes. The standard size is designated SOD-80, with dimensions shown to the right. (MELF: Metal Electrode Face Bonding)



Diodes and Transistors, continued

Fig. 4.16: SOT-packages for SMD diodes and transistors: The most common, SOT-23 top left, SOT-89 for power transistors in the middle, and SOT-143 with four terminals to the right. The dimensions for SOT-23 are shown bottom left, and a cut-through SOT-89 in the middle. Ceramic SMD transistor packages with terminal placement like for SOT-23 are shown bottom right.



IC Packages• Plastic or Ceramic IC Packages?

• Plastic:– Not hermetic– Low price in large quantities– High initial cost – Low thermal conductivity – Limited time at high temperature– Thermal mismatch to Si chip and metals – Not suitable for for high frequency circuits

• Ceramic:– Hermetic, good reliability– Costly, but OK for prototyping– Good thermal conductivity – Low thermal coefficient of expansion, matches well with Si, mismatch

to organic substrates– Gold metallization must be removed – Well defined high frequency properties



Packages for Hole Mounted ICs

Fig. 4.17:a) DIP (Dual-in-line) IC package. b) Partly cross-sectioned DIP package which shows the silicon chip, bonding wires, lead frame and plastic body. c) The terminal organisation for 4 two-input NOR gates in a 14 pins package.



Packages for Hole Mounted ICs, continued

Fig. 4.18: Pin grid packages: To the left a cavity up ceramic package, and to the right a plastic moulded package.



SMD IC Packages

• Small Outline (SO)

• Plastic Leaded Chip Carrier (PLCC)

• Leadless Chip Carrier (LLCC)

• Leaded Ceramic Chip Carrier (LDCC)

• Flatpack, mini-flatpack

• TapePak

• Chip Scale Packages



SMD IC Packages, continued

Fig. 4.19: Surface mounted SO (Small Outline) IC package. (From Philips)



SMD IC Packages, continued

Table 4.3: Dimensions for SO- and VSO packages. Centre-to-centre lead distance is normally 50 mils, except for VSO-40 with 30 mils and VSO-56 with 0.75 mm.

Outline Encapsulation Maximum widthSO Maximum width Maximum length Lead end to lead end

[mm] [mm] [mm]SO-8 4,0 5,00 6,2SO-8 7,6 7,6 12,4SO-14 4,0 8,75 6,2SO-16 4,0 10,00 6,2SO-16L 7,6 10,5 10,65SO-20 7,6 13,0 10,65SO-24 7,6 15,6 10,65SO-28 7,6 18,1 10,65VLO-40 7,6 15,5 12,8VSO-56 11,1 21,6 15,8



SMD IC Packages:Plastic Leaded Chip Carrier (PLCC)

Fig. 4.20: Plastic leaded chip carrier with (PLCC). They are normally square with an equal number of terminals on all four sides (top). For large DRAMs, the package has terminals on only two sides, also being called SOJ. The bottom figure shows a 1 or 4 Mbit DRAM package.



SMD IC Packages:Plastic Leaded Chip Carrier (PLCC)

Table 4.4: Dimensions for PLCC packages. Format means the number of terminals on two neighbouring sides.

Leads Format Lead pitch

[mm]

Maximum bodydimensions [AxB][mm]

Maximum DeviceDimensions (LxW)[mm]

TypicalHeight (C)[mm]

20 5x5 1,27 9,1x9,1 10,1x10,1 3,5-4,728 7x7 1,27 11,6x11,6 12,6x12,6 3,5-4,744 11x11 1,27 16,8x16,8 17,8x17,8 3,5-4,752 13x13 1,27 19,3x19,3 20,3x20,3 3,5-4,768 17x17 1,27 24,4x24,4 25,4x25,4 3,5-4,718 5x4 1,27 10,9x7,5 11,9x8,5 3,5-4,728 9x5 1,27 14,1x9,0 15,1x10,0 3,5-4,732 9x7 1,27 14,1x11,6 15,1x12,6 3,5-4,7



Leadless Chip Carrier (LLCC)Leaded Ceramic Chip Carrier (LDCC)

Fig. 4.21 a): The various types of ceramic chip carriers [4.15]. Types A -D to the left are leadless (LLCC), whereas types A and B to the right are meant for mounting leads (LDCC).



Leadless Chip Carrier (LLCC)

Fig. 4.21 b): LLCC packages, additional details. The longest terminal is to designate electrical terminal number 1 in the circuit.



Leadless Chip Carrier (LLCC), continued

Table 4.5. LLCCs, dimensions.

Leads Format Pad Pitch (p)[mm]

Maximum Dimension (AxB)[mm]

20 5x5 1,27 9,1x9,128 7x7 1,27 11,6x11,644 11x11 1,27 16,8x16,852 13x13 1,27 19,3x19,368 17x17 1,27 24,4x24,484 21x21 1,27 29,6x29,618 5x4 1,27 10,9x7,528 9x5 1,27 14,1x9,032 9x7 1,27 14,1x11,6



Leaded Ceramic Chip Carrier (LDCC)

Fig. 4.22: Leaded ceramic chip carriers.



Leaded Ceramic Chip Carrier (LDCC), continued

Fig. 4.23: Various shapes of the leads, and leadless termination for comparison.



Flatpacks

Fig. 4.24: Quad flatpack with leads on all four sides. Flatpacks are usually made of plastic or ceramic. They have

leads on four or two sides.



Mini-flatpacks

Fig. 4.25: Mini-flatpacks is a name for higher density flatpacks: Typically 84 - 244 terminals and a pitch of 25 mils.



TapePak

Fig. 4.26: National Semiconductor´s TapePak component packages are specified with terminal numbers between 40 and close to 600. To the left we see a 40 leads TapePak in the form it is received by the user with a protective ring around it, and test points outside the ring. To the right is TapePak 40 after excising and lead bending, seen from above and from the side.



High Performance Packages

• Multilayer ceramic, Al2O3 or AlN

–Ground planes–Controlled characteristic impedance–Thermal vias




Fig. 4.27: Thermal via-holes in the printed circuit board, for better heat conduction.




Fig. 4.28: Multilayer package for high frequency GaAs circuits with 3 ground planes, 2 voltage planes, 1 signal layer and a top conductor layer

for contacts and sealing (Triquint).



High Performance Packages, continued

Fig. 4.29: Multichip package for memory module in a Hitachi high-performance computer [4.18]. The module

contains 6 ECL chips, mounted by flip chip.



Packages: Future Trends

Fig. 4.30: Comparison between the size of various package forms for an integrated circuit with approximately 64

terminals.



Packages: Future Trends, continued

Fig. 4.31: History and prognosis for the use of various sizes of passive SMD components, in percentage of the total

number.



Metallization of Terminals

• Passives–Ag in alloy with Pd, Ni barrier, Sn/Pb–Ag in solder alloy–With adhesive mounting:

• No Sn/Pb on terminal

• ICs–Au removed–Sn/Pb coating



Terminal Metallization, Solderability and Reliability

Fig. 4.32: Strain at fracture of solder fillet as function of gold concentration in the solder metal, relative to value without gold.



Electrostatic Discharges (ESD)

• Unprotected MOS: Max 5 - 80 V on input before destroyed

• Triboelectricity: >>1000 V discharge

• Billions of $ damage annually

• Protected circuits tolerate 500 - 8000 V

• Extensive precautions in industry, handling and packing



Electrostatic Discharges - Component Damages and Precautions

Fig. 4.33: MOS transistor schematically. The gate oxide is very vulnerable for damage by electrostatic discharge. Gate

oxides down below 200 Å (20 nm) are now used.



Electrostatic Discharges - Component Damages and Precautions, continued

Fig. 4.34: CMOS circuit exposed to electrostatic damage: Silicon has molten in a small area. Picture size 5m x 5m.



Electrostatic Discharges - Component Damages and Precautions, continued

Fig. 4.35: ESD protection circuit at in- and outputs for MOS and for bipolar circuits.



Component Packaging

• Paper tape (hole mounted passives)

• Blister tape (SMD passives, discretes, small ICs)

• Sticks (DIPs, SMD ICs)

• Waffle trays (Flatpacks)

• Stack magazine

• Bulk: Not suited for automatic mounting



Component Packaging for Automatic Placement

Fig. 4.36: Blister tape for surface mounted components. Standard dimensions for 8 mm wide tape.



Component Packagingfor Automatic Placement

Fig. 4.37: Plastic sticks as packaging for SMD integrated circuits.



Component Packagingfor Automatic Placement

Fig. 4.38: Waffle trays packaging for flatpacks to the left, frame for stacking of single component to the right.



End of Chapter 4 Components for Electronic Systems

• Important issues:–Components:

• Distinguish between the different components

–Packages for electronic devices :• Distinguish between the different packages

–Electrostatic discharges–Component packaging:

• Used for automatic assembly machines

electronic pack….. chapter 4 components for electronic systems slide 1 chapter 4 components for...

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