Electronic Engineering Final Year Project 2008

By Claire Mc Kenna

Title: Point of Load (POL) Power Supply Design

Supervisor: Dr Maeve Duffy

Overview Project Outline Background Research Buck and Multiphase Buck Converter Simulation Vicor V.I Chip Simulation Buck Converter Vs V.I Chips

Project Outline Objective is to compare the industry used

Dc-Dc Voltage Regulator Module (VRM) the (Interleaved Buck Converter) with an alternative ‘Factorised Power’ solution.

Factorised power converters V.I Chips, PRM and VTM made by Vicor Corporation.

Pre-Regulator Module (PRM) and Voltage Transformation Module (VTM) chips.

Background Operating voltages for microprocessors are

getting smaller e.g. 1V. As the operating voltage is reduced the current

drawn is increased. Higher current results in higher dissipated losses

in MOSFETs and copper paths. Challenge to maintain a constant output voltage

under steady state and transient load conditions

Background When the processor switches from one

state to another voltage drops and spikes occur.

Vicor have proposed a factorised power solution, providing low voltage (0.8V) and high current (100A) direct from 48V input.

Compare the V.I chips and the industry used interleaved buck under steady state and transient load conditions.

Factorised Power Solution

Research Review of VRM issues for future

microprocessor requirements. Research on the PRM and VTM V.I chips. Review of Buck converter using Pspice. Review of Synchronous Buck Converter Review of the Multiphase Interleaved

Buck Converter.

Buck Converter Simulation Required Buck Converter Specification

Input Voltage – 12VOutput Voltage – 1.3VFrequency – 500KHzOutput Current – 100A

Inductor and Capacitor values were calculated. The duty cycle D was found to be 0.108, T = 2us,

Ton = 0.216us

Buck Converter Simulation Pspice representation of the Buck Converter

circuit

The MOSFET used was 200V/120A vendor model found in the Pspice library.

V 11 2 V d c

M 1

V 2

TD = 0

TF = 1 nP W = 1 . 4 uP E R = 2 u

V 1 = 0

TR = 1 n

V 2 = 1 0 v

0

L 1

2 3 . 1 8 n H

1 2

C 11 5 3 8 u F

R 10 . 0 1 3 o h m

D 1

0

Buck Converter Simulation Results Vout was less than 1.3V due to the

switching losses and voltage drops from the MOSFET and diodes.

By varying the ON time to 1.4us, 1.3V was obtained at the output.

The output current measured was 100A. The output power measured was 140W. The efficiency was found to be 93%.

Buck Converter Simulation Results Current ripple was calculated to be 99.7A and the

measured value obtained was 99.6A.

Time

0s 20us 40us 60us 80us 100us 120us 140us 160us 180us 200us-I(R1) I(L1)

0A

10A

20A

30A

Multiphase Interleaved Buck Converter Using the same specification as the Buck a

2-Phase Interleaved Buck was simulated.

0

C

L 11 2

V d c

L 21 2

0

0

0

R

M 1

M 2

D 1

D 2

Multiphase Buck Converter Simulation Results Driving the MOSFETS 1us apart introduced the

interleaving effect which is the ripple cancellation in the output capacitor.

The duty was adjusted and the correct output

voltage and current was obtained.

Multiphase Buck Converter Simulation Results Transient load change was also simulated and

the circuit goes through transient response before it settles back down.

Time

0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90msV(U7:1)

0V

0.5V

1.0V

1.5V

2.0V

Zero Voltage Switching (ZVS) Buck-Boost Converter The ZVS buck boost is the topology used by the

PRM chip. It is a discontinuous topology in which the

inductor current IL essentially returns to zero regardless of the load.

The ZVS enables high frequency operation with high efficiency.

A switching cycle for the ZVS buck-boost consists of four phases. The Input Phase, In-Out Phase, Freewheel Phase and the Clamped Phase.

ZVS Buck-Boost Converter Simulation The required specification for the ZVS Buck-Boost

Input Voltage – 48V

Output Voltage – 35V

Output Current – 3.12A

Frequency – 1.5MHz

Here is the Pspice representation of the ZVS Buck-Boost.

L 1

1 u H

1 2V 1

4 8 V d c

0

V 2

TD = 0 . 2 9 uTF = 1 nP W = 0 . 2 2 uP E R = 0 . 5 2 uV 1 = 0TR = 1 nV 2 = 1 2

V 3

TD = 0 . 3 5 uTF = 1 nP W = 0 . 2 6 uP E R = 0 . 5 2 uV 1 = 0TR = 1 nV 2 = 1 2

V 4TD = 0

TF = 1 nP W = 0 . 2 6 uP E R = 0 . 5 2 u

V 1 = 0

TR = 1 n

V 2 = 5 0

V 5

TD = 0 . 0 7 u

TF = 1 nP W = 0 . 2 6 uP E R = 0 . 5 2 u

V 1 = 0

TR = 1 n

V 2 = 1 2

R 11 0

0

0

0

M 1

M 2

M 3

M 4

0

C 11 0 u F

ZVS Buck-Boost Converter Simulation Results The ZVS Buck-Boost circuit was simulated using

the switching sequence below.Switches Input

PhaseIn-Out Phase

Freewheel Phase

Clamp Phase

S1 ON ON OFF OFF

S2 OFF OFF ON ON

S3 OFF ON ON OFF

S4 ON OFF OFF ON

ZVS Buck-Boost Converter Simulation Results

When the circuit was simulated the output voltage was found to be 35V.

Output current 3.5A. Output power 125W. The efficiency was calculated and found to

be 98%.

ZVS Buck-Boost Converter Simulation Results

A frequency of 1MHz was also simulated but was found to have bigger voltage ripple at the output.

It was also found that varying the duration of the switches, the output voltage could be controlled.

Sine Amplitude Converter (SAC) This is the topology used by the VTM chip. SAC uses a high frequency resonant tank to

move energy from the input to output. The resonant tank is formed by the resonant

capacitance, inductance and leakage inductance in the power transformer windings.

MOSFETS are switched at resonant frequency and resonant current through the tank is rectified by diodes and filtered by the output capacitor.

The switching has two power transfer intervals and two 20ns energy recycling intervals.

Sine Amplitude Converter (SAC) Simulation It can be implemented as a half-bride or a full-

bridge resonant converter. The required specification for the SAC is;

Input Voltage – 35VOutput Voltage – 1VOutput Current – 100AFrequency – 1.5MHz

The resonant capacitance (CR) is 52nF and the resonant inductance (LR) is 200nH which gives a resonant frequency (FR) of 1.5 MHz

Sine Amplitude Converter (SAC) Simulation Below is the Pspice representation of the half-

bridge SAC.

L 1

2 0 0 n H

1 2

C 12 6 n F

C 22 6 n F

C 35 6 0 u F

R 10 . 0 1

V 13 5 V d c

V 2

TD = 0

TF = 1 nP W = 3 3 1 . 5 nP E R = 7 0 7 n

V 1 = 0

TR = 1 n

V 2 = 5 0

V 3

TD = 3 5 3 . 5 n

TF = 1 nP W = 3 3 1 . 5 nP E R = 7 0 7 n

V 1 = 0

TR = 1 n

V 2 = 2 0

0

0

D 1 D 2

0

Lp

Ls1

Ls2

TX1

0

M 1

M 2

Sine Amplitude Converter (SAC) Simulation Results The transformer used is a centre tapped

secondary Pspice model. The MOSFETS were switched synchronously. When simulated the output voltage was found to

be 1V. Output current 100A and the output power 101W . The efficiency was found to be 99%.

Sine Amplitude Converter (SAC) Simulation Results The full-bridge was also simulated.

S1 was switched with S4, S2 switched with S3.

D 1 D 2

L 1

2 0 0 n H

1 2

C 1 8 0 0 u F

C 2

5 2 n F

R 1 0 . 0 1

0

Lp

Ls1

Ls2

TX1

0

0

0

V 13 5 V d c

TD = 0

TF = 1 nP W = 3 3 1 . 5 n

P E R = 7 0 7 n

V 1 = 0

TR = 1 n

V 2 = 8 0

TD = 3 5 3 . 5 n

TF = 1 nP W = 3 3 1 . 5 n

P E R = 7 0 7 n

V 1 = 0

TR = 1 n

V 2 = 1 2

TD = 3 5 3 . 5 n

TF = 1 nP W = 3 3 1 . 5 nP E R = 7 0 7 n

V 1 = 0

TR = 1 n

V 2 = 8 0

TD = 0

TF = 1 nP W = 3 3 1 . 5 nP E R = 7 0 7 n

V 1 = 0

TR = 1 n

V 2 = 1 2

0

0

M 3

M 4

M 1

M 2

Sine Amplitude Converter (SAC) Simulation Results

The output voltage was found to be 1V. Output current 100A and the output power

105W. The efficiency was found to be 95%.

Full-bridge Vs Half-bridge SAC The full-bridge has slightly bigger voltage ripple

than the half-bridge. The full-bridge has an efficiency of 95% and the

half-bridge an efficiency of 99% and therefore is slightly more efficient than the full-bridge.

If these circuits were to be built in the laboratory the full-bridge would have bigger losses and noise than the half-bridge due to the full-bridge having more switching elements.

Depends on application

Buck Converter Vs V.I Chips Multiphase has ripple cancellation. Can be redesigned to account for the effects of

non-ideal active and passive components. ZVS Buck-Boost is an efficient regulator at high

frequency switching. SAC is single phase unlike interleaved which

uses multiple phases to achieve high frequency switching.

Buck Converter Vs V.I Chips In terms of size the buck topology requires a bulky

15,000uF output capacitor to eliminate the ripple and the SAC requires an 80uF output capacitor.

Overall the V•I chip combination achieves high switching frequency which means using small magnetics.

Reduced size due to surface mount technology and printed circuit transformer incorporated in the SAC embodiment.

Summary Microprocessor operating voltages decreasing

and current is increasing. Compare Buck Converter with ‘factorised power

solution’ by Vicor Corporation. Pre-regulator provides efficient regulation at

high switching frequency. Voltage Transformation enables high operating

frequency, reduced losses and smaller size.

Thank you.

Any Questions?