electrochemical processes for microelectronics …– poor adhesion to dielectrics – rapid...
TRANSCRIPT
1Y. Shacham-Diamand, Sept. 04
Electrochemical processes for Electrochemical processes for Microelectronics ApplicationsMicroelectronics Applications
Prof. Yosi Shacham-Diamand
2Y. Shacham-Diamand, Sept. 04
Middle east
3Y. Shacham-Diamand, Sept. 04
Why the middle east is relevant to Cu ULSI technology ?
The origin of the Damascene technology, now used for ULSI metallization, is in the middle east.The name “Damascene” means “from Damascus”
4Y. Shacham-Diamand, Sept. 04
Eastern Roman Empire, ~ 1500 years ago
5Y. Shacham-Diamand, Sept. 04
Damascene: From Damascus
6Y. Shacham-Diamand, Sept. 04
Zichron-Yaakov – my hometown
7Y. Shacham-Diamand, Sept. 04
Tel-Aviv university – Faculty of engineering
8Y. Shacham-Diamand, Sept. 04
List of content
IntroductionThe chip wiring problemCu wiring - the current solution
Cu electroplating – basics and resultsElectroless plating:
Electroless Cu technologyBarrier and capping layers
Summary
9Y. Shacham-Diamand, Sept. 04
Introduction
The chip wiring problemCu wiring - the current solution
10Y. Shacham-Diamand, Sept. 04
Cross section of ULSI interconnect scheme (ITRS 2001)
Hierarchical Scaling
11Y. Shacham-Diamand, Sept. 04
Typical Very Large Scale Integration (VLSI) Chip includes many layers of metallization, however most of them are made by sputtering. For example, multi-level aluminum interconnect (DEC Alpha AXP 21164)
12Y. Shacham-Diamand, Sept. 04
Another example, Intel technology
Intel 2000
13Y. Shacham-Diamand, Sept. 04
- Those examples were all with aluminum technology.- Aluminum metallization dominated VLSI integrated circuits manufacturing for more than 20 years.
14Y. Shacham-Diamand, Sept. 04
Not anymore….Plating is finding its place again as a useful technology for modern VLSI technology…..
15Y. Shacham-Diamand, Sept. 04
Subtractive vs. additive patterning
16Y. Shacham-Diamand, Sept. 04
Copper multi-level metallization: 0.25 µm electroplating technology made by IBM
17Y. Shacham-Diamand, Sept. 04
IBM CMOS 7S process
18Y. Shacham-Diamand, Sept. 04
IBM PowerPC 750
19Y. Shacham-Diamand, Sept. 04
If Aluminum technology is so good why switching to copper?
Al reliability problems:ElectromigrationStress voidingContact electromigration
Al resistivity becomes too high Al structure is actually TiN/Al/TiN/Ti with W plugs…..it’s complicated and expensive.
20Y. Shacham-Diamand, Sept. 04
Moore’ s law“ The number of transistors in a chip doubles every 18 -24 months”
Doubling time of fitted line is 2.3 years
21Y. Shacham-Diamand, Sept. 04
Feature size reduction
22Y. Shacham-Diamand, Sept. 04
Wafer size growth
23Y. Shacham-Diamand, Sept. 04
Gate and interconnect delay versus feature size. Interconnect delay versus feature size. Interconnect delay is shown for repeater spacing (L) of 3000 and 5000
Havermann, 2001
24Y. Shacham-Diamand, Sept. 04
Local vs. global wiring
Havermann, 2001
25Y. Shacham-Diamand, Sept. 04
Interconnect capacitance
The effective are of capacitors is larger than their projected area Capacitance is not scaled down linearly !!!
26Y. Shacham-Diamand, Sept. 04
Interconnect capacitance: line to line vs. line to ground capacitance
27Y. Shacham-Diamand, Sept. 04
Microprocessor speed as function of feature size and technology (Haverman, 2001)
28Y. Shacham-Diamand, Sept. 04
The “long line” problem
29Y. Shacham-Diamand, Sept. 04
The ultimate limits…until further notice
Davis, 2001
30Y. Shacham-Diamand, Sept. 04
31Y. Shacham-Diamand, Sept. 04
The Cu solution to the ULSI metallization scaling problem.
32Y. Shacham-Diamand, Sept. 04
Why copper?Why copper?– Copper resistivity (1.7µΩ-cm) much lower thanaluminum (2.6 µΩ-cm)– Electrical reliability >10x greater than aluminum(electromigration + stress voiding)
What are the issues?What are the issues?– Difficult to Etch– Poor Adhesion to dielectrics– Rapid Diffusion through SiO2– Forms mid-gap energy level in Si
33Y. Shacham-Diamand, Sept. 04
34Y. Shacham-Diamand, Sept. 04
Electroplating Based Process Sequence
Simple, Low-cost, Hybrid, Robust Fill Solution
Pre-clean IMP barrier + Copper Electroplating CMP
25 nm 10-20 nm + 100-200 nm
35Y. Shacham-Diamand, Sept. 04
Electroplating solutions
• Cu ions - Cu sulfate
• Acid - H2 SO4 for pH adjustment
• HCl - Affects Cu surface adsorption; Halide ad-layer drives Cu growth. It also acts as a surfactant and stabilizes grain growth. Cu deposition is driven by the desorption of the halides.
36Y. Shacham-Diamand, Sept. 04
Additives
Wetting agents - penetration into deep feature
Suppressors (Inhibitors)Carriers - Poly Ethylene Glycol (PEG) , MW ~ 2000-5000. Forms thin film that inhibits charge transfer, diffuses slowly.
Levelers - Adsorbed at corners and edges and slow surface diffusion & growth, improve step coverage.
AcceleratorsBrightners - Organo-sulfides, diffuses rapidly, Catalyzes charge transfer.
37Y. Shacham-Diamand, Sept. 04
Single vs. dual Damascene
38Y. Shacham-Diamand, Sept. 04
39Y. Shacham-Diamand, Sept. 04
40Y. Shacham-Diamand, Sept. 04
41Y. Shacham-Diamand, Sept. 04
Damascene: Damascus Scenery
It is an ancient art from the Byzantine empire (East Roman)Damascus, now in Syria, was a big metallurgical center 2000 years agoThey invented the embedded gold art, now you can find it near Toledo in Spain. (Spain was under Arabic invasion ~ 1200 years ago)
http://www.tf.uni-kiel.de/matwis/amat/def_en/kap_5/advanced/t5_1_1.html
42Y. Shacham-Diamand, Sept. 04
Damascene Technique in Metal Working
Metal was inlaid with silver or gold
43Y. Shacham-Diamand, Sept. 04
Damascene technology
The "steel" part - Iron rich in Phosphorous and not necessarily Carbon The forge welding - folding over the same basic material which, however, may have been quite inhomogeneous. Lots of folding and forge welding created a homogeneous looking material - this is the Japanese way.The welding technique was not only continued (and somewhat irregular) folding and hammering, but a more complicated technique, called "pattern welding". Was used.
44Y. Shacham-Diamand, Sept. 04
Part of a very old damascene (= pattern welded) sword blade. )from the Internet article "Blade Patterns Intrinsic to Steel Edged
Weapons ")from Lee .A .Jones
45Y. Shacham-Diamand, Sept. 04
In Japan, around 600 A.D., smelting technology was introduced from China and Korea. The Japanese specialty was the mass production of (impure) steel, which was folded so many times and forge welded again that all the impurities were driven out of the steel and the carbon became as evenly distributed as modern steels we have today
46Y. Shacham-Diamand, Sept. 04
Cu electroplating basics
47Y. Shacham-Diamand, Sept. 04
48Y. Shacham-Diamand, Sept. 04
49Y. Shacham-Diamand, Sept. 04
50Y. Shacham-Diamand, Sept. 04
Tafel plot for Cu electrodepositing from aqueous solution CuSO4 (0.15 N) and H2SO4 (1.0N)
51Y. Shacham-Diamand, Sept. 04
Anodic and cathodic currents of Cu electrode
In aqueous solution CuSO4 (0.15 N) and H2SO4 (1.0N)
52Y. Shacham-Diamand, Sept. 04
Plating regions of operation
53Y. Shacham-Diamand, Sept. 04
Deposition systems types
Fountain type – horizontal waferImmersion type – vertical wafer
54Y. Shacham-Diamand, Sept. 04
Fountain type
55Y. Shacham-Diamand, Sept. 04
Electroplating solutions – Acid bath
• Cu ions - Cu sulfate
• Acid - H2 SO4 for pH adjustment
• HCl - Affects Cu surface adsorption; Halide ad-layer drives Cu growth. It also acts as a surfactant and stabilizes grain growth. Cu deposition is driven by the desorption of the halides.
56Y. Shacham-Diamand, Sept. 04
Electroplating Based Process Sequence
Simple, Low-cost, Hybrid, Robust Fill Solution
Pre-clean IMP barrier + Copper Electroplating CMP
25 nm 10-20 nm + 100-200 nm
57Y. Shacham-Diamand, Sept. 04
Electroplating solutions – Basic bath
• Cu ions - Cu sulfate
• Pyrophosphate (P2O7)4-
• Nitrate, NO3-
• Ammonia
• Orthophosphate (HPO4)2-
• Additives
pH ~8.0-8.8
T=50-60C
58Y. Shacham-Diamand, Sept. 04
Additives
Wetting agents - penetration into deep feature
Suppressors (Inhibitors)Carriers - Poly Ethylene Glycol (PEG) , MW ~ 2000-5000. Forms thin film that inhibits charge transfer, diffuses slowly.
Levelers - Adsorbs at Corners and slows surface diffusion & growth, improve step coverage, Amidofunctional groups.
AcceleratorsBrightners - Organo-sulfides, diffuses rapidly, Catalyzes charge transfer.
5959
Applications for plating
On-chip wiring3D integrationPackaging
60Y. Shacham-Diamand, Sept. 04
Dual Damascene integration scheme
61Y. Shacham-Diamand, Sept. 04
Problems in a Damascene process
62Y. Shacham-Diamand, Sept. 04
Dual Damascene with trench first
63Y. Shacham-Diamand, Sept. 04
Cu+low-K technologyFully planar - better lithographyFaster - lower resistivity and capacitanceMore reliable lower power - P=1/2 CV2fLower cost - Dual damascene process has fewer steps and its capital and tool investment is ~40% less than Al process.Electroplating is compatible with Electroplating is compatible with lowlow--K technologyK technology
64Y. Shacham-Diamand, Sept. 04
65Y. Shacham-Diamand, Sept. 04
Low-K materials for Cu interconnects
66Y. Shacham-Diamand, Sept. 04
Sub-100 nm interconnects (a)
Problems:Materials properties – texture, morphologyProcess – coverage, uniformity.Integration – compatibility, integrabilityTools – new processes require new toolsResistivity – dimension effects: Narrow Line
Resistivity Increase (NLRI) effectReliability: voiding, delamination, electromigration, corrosionHigh complexity, large chips with high lead counts packaging
All this lead to long learning time, high NRE, low yield and eventually, to cost problems
67Y. Shacham-Diamand, Sept. 04
Sub-100 nm interconnects (b)
Solutions:Better deposition methods – ALD, seedless electrolessClever integration methods - Integrated barrierAlloying –.
Conducting metal - barrier-less metallization, better conductivity for sub-50 nm linesBarriers: Better materials. e.g. Co(W,P) is a better barrier than Co(P), electroless barriers offer high selectivity and save process steps
68Y. Shacham-Diamand, Sept. 04
Narrow Line Resistivity Increase (NLRI) effect is aggravated by the presence of the barrier
Linewidth, nm40 60 80 100 120 140
Res
ista
nce
per u
nit l
engt
h, Ω
m-1
0
1000
2000
3000
4000
5000"Barrierless" Cu "Barrierless" Ag Cu with 10 nm barrierCu with 5 nm barrier
“barrierless” metallization
Conventional Dual Damascene
69Y. Shacham-Diamand, Sept. 04
Cu is better than Al–ReliabilityCu alloys are better than pure Cu
70Y. Shacham-Diamand, Sept. 04
Cu technology main problemsCu technology main problems
Difficult to EtchPoor Adhesion to dielectricsRapid Diffusion through SiO2 and low-K
inter-level-dielectrics (ILD)Forms mid-gap energy level in SiVia/trench fillingPost CMP damageCorrosion
71Y. Shacham-Diamand, Sept. 04
A Cu interconnect process for the 130nm process technology nodeP. Moon, INTEL (AMC, 2001)
72Y. Shacham-Diamand, Sept. 04
Sub-100 nm Cu interconnects - A
Modified metallization process
• 10 nm Ta barrier PVD• 30 nm Cu seed PVD• 700 nm Cu ECD• CMP
100 nm
Extending Copper Metallization Technology for Wiring to End-of-Roadmap Feature SizesM. Engelhardt1, G. Schindler1, K. Mosig1,2, G. Steinlesberger1,W. Steinhögl1, G. Gebara2
1: Infineon Technologies, Corporate Research, CPR NP, Otto-Hahn-Ring 6, D-81730 Munich, Germany2: International Sematech , 2706 Montopolis Drive, Austin, TX 78741-6499, USA
Trenches remain open for ECD
73Y. Shacham-Diamand, Sept. 04
SiO2
Si3N4
25 nm Ta100 nm Cu seed
10 nm Ta30 nm Cu seed
Sub-100 nm Cu interconnects - B
74Y. Shacham-Diamand, Sept. 04
sFull Cu Vertical Interconnect
2.5x2.5 µm2 Through-wafer Via-Chain
P. Ramm, D. Bonfert, R. Ecke *, F. Iberl, A. Klumpp, S. Riedel *, S.E. Schulz *, R. Wieland, M. Zacher *, and T. Gessner *
Fraunhofer Institute Reliability and Microintegration, Munich, Germany * Chemnitz University of Technology, Germany
Challenge:
Via filling of deep and high aspect ratio features
75Y. Shacham-Diamand, Sept. 04
Additive ConcentrationCS
TOP0
Height
CSBOTTOM
CONSUMPTION
INFLOW
Step-coverage and filling modeling –Explain super-filling, voids
Few groups work on modeling, for example -
• T. Moffet et al. (NIST, USA)
•T. Smy (Carlton Univ., Canada)
•N. Kovarsky et al (AMAT)
The models include
• Solution components transport modeling
• Additive effects
• Curvature effects
• Modeling at various scales – tool, trench
76Y. Shacham-Diamand, Sept. 04
attribute Cr TiN TiN/Ti Ti/TiN TiN/Ta TaN β-Ta TaN/α-Ta TaSiN WNx
Cu barrier X a a a a a a a a a
Liner adhesion to ILD a a a a a a X a a a
Cu adhesion to liner a X a X a X a a X ?/XLiner adhesion onto Cu a ? ? a ? a a a a ?Low in-plane resistivity a X a a ? X X a X Xno Cu poisoning a a X a a a a a ? a
CMP - high yield ? X X X X/ a a a a a ?single chamber a a a a X a a a a a
Low via resistance a a X ? a a a a a ? aLow contact-resistance a a a a a a a a ?No Cu corrosion ? X X X X/ a a a a a ?Thermal stability ? a X X a a a a ? a
Low stress, no cracking X a a a a a a a a a
Good step coverage ? a a a a a a a a a
Final X X X X X X X a X X
Evaluation Criteria for Cu Liner,D. Edelstaein et al, IBM, AMC 2001
77Y. Shacham-Diamand, Sept. 04*E. Cooney III, et al., AVS (1999)
PVD TaN/Ta/Cu-seedPVD TaN/Ta/Cu-seed
I-PVD TaN/Ta/Cu-seed, plated-Cu fill*I-PVD TaN/Ta/Cu-seed, plated-Cu fill*
SEMs of > 4:1 Cu dual-Damascene.SEMs of > 4:1 Cu dual-Damascene.
Cu Dual-Damascene Metallization (D. Edelstein, AMC 2002)
78Y. Shacham-Diamand, Sept. 04
90±5 nm
500C
400CAs dep.
nm
NixW1-x Cu
SIMS profiles of thin NiW films on Cu before and after 30 min. anneal. Example: Ni60W40
7979
Electroless Plating for ULSI and MEMS Applications
80Y. Shacham-Diamand, Sept. 04
Metal displacement reactionExample: when Zinc is immersed in a Copper Sulfate solution:
V 0.76E 2 020 =+→ −+ eZnZn
V 0.34-E 2 002 =→+ −+ CueCu
1. Anodic oxidation of Zinc
2. Cathodic reduction of Cu
Result:
Cu is deposited on the Zn sample
After all the Zn sample is coated with Cu the deposited stops.
E0 = 0.76 (Oxidation)
E0 = +0.34 (Reduction)
81Y. Shacham-Diamand, Sept. 04
Pourbaix Diagram for Cu
82Y. Shacham-Diamand, Sept. 04
Nernst equation
E0 – the potential versus a standard hydrogen electrode (SHE)
Note that E0 is defined for the standard RedOx reaction
[ ][ ]d
OxnFRTdneOx Re
0 lnEE Re +=→+ −
Therefore E0 is defined for [Ox]=[Red]=1M
E is the RedOx potential; it is related to the free energy change of the reaction as
∆G=-nqE
83Y. Shacham-Diamand, Sept. 04
Electroless plating solution1. Cu salt – Cu is reduced
Cu+2 + 2e- Cu0 E0Cu = 0.34 eV
2. Reducing agent – oxidized at the interface
Red-n Red-n+2 + 2e- Oxidation potential = -Ered
(Red-n+2 + 2e- Red-n , -Ered < Ecu
3. Total reaction – Cu+2 + Red—n Cu0 + Red-n+2
∆E= ECu+ Ered >0 ∆G=-2q∆E < 0,
i.e. spontaneous deposition !!!
84Y. Shacham-Diamand, Sept. 04
Typical Cu electroless deposition solutions
85Y. Shacham-Diamand, Sept. 04
Component Aim Cu deposition
Co(W,P) deposition
Metal salt metal ion source CuSO4•5H2O CoSO4•6H2O Na2WO4•2H2O
Reducing agent
reducing the metal ion HCOH Na2H2PO2
Complexing agent
reducing electrochemical potential difference
EDTA Na3C6H4O7•H2O
pH adjustments
electrochemical potential, rate and mechanism
N(C2H5)4OH,
KOH or TMAH
Stabilizer stabilizing the solution, preventing hydrogen inclusion
N(CH3)4CN 2,2'-dipyridyl
Surfactant reducing surface tension, extracting H2
RE-610 RE-610
Electroless Cu and Co(W,P) for VLSI metallization
86Y. Shacham-Diamand, Sept. 04
I [A]
Electroless solution potential, V
Oxidation of the reducer
ia
Ic Reduction of the metal ions
E0Mz+
E0red
Mixed potential
Emp
Total current
In electroless plating the total current = 0
Therefore, the anodic current balances the cathodic current
87Y. Shacham-Diamand, Sept. 04
88Y. Shacham-Diamand, Sept. 04
89Y. Shacham-Diamand, Sept. 04
Cu dep. Rate vs pH (Cu2+, HCOH solution)
90Y. Shacham-Diamand, Sept. 04
Solution composition for electroless Cu deposition with Glyoxylic acid
Components Concentration
CuSO4·5H2O 0.0305 M
EDTA 0.0351 M
Glyoxylic acid 0.054 – 0.11 M
Surfactant RE-610 0.004 g/l
KOH or TMAH Adjust pH to 12.3-12.7
91Y. Shacham-Diamand, Sept. 04
ab
cSEM pictures of via contacts (a) before
deposition (with seed layer), (b) after 1 min
electroless copper film deposition, and (c) after 2
minutes of ELD Cu.
92Y. Shacham-Diamand, Sept. 04
Electroless deposition of alloys is also possible for VLSI applications…..
93Y. Shacham-Diamand, Sept. 04Source: J.A. Cunningham, SI, April 2000
9494
, Zn, Co & Ni, Zn, Co & NiSnSnSolutions a for Cu alloys with Solutions a for Cu alloys with
• CuSO4 and Cu(NO3) 2 based solutions,
• EDTA or Rochelle salt (sodium-potassium tartrate) as complexing agents
• SnCl2.2H2O, ZnCl2 CoSO4 or NiCl2 as a source of alloy-metal ions.
• Formaldehyde or sodium borohydride (NaBH4).
• pH ~ 12-13
• T = RT to 90C
95Y. Shacham-Diamand, Sept. 04
Thickness of electroless deposited thin films (A)
0 200 400 600 800 1000 1200 1400
Elec
trol
ess
depo
site
d th
in fi
lms
resi
stiv
ity, Ω
.cm
1e-5
1e-4
1e-3
CuCo/Co CuNi/Co
Resistivity of electroless Cu-Co & Cu-Ni as a function of film thickness
96Y. Shacham-Diamand, Sept. 04
Molar ratio [Cu++]/[Ni++] in bath
0.00 .05 .10 .15 .20 .25 .30 .35 .40
Res
istiv
ity o
f ele
ctro
less
dep
osite
dth
in C
u-N
i film
s, Ω
.cm
0e+0
1e-6
2e-6
3e-6
4e-6
5e-6
6e-6
7e-6
8e-6
9e-6
1e-5on Cu as depositedon Co as depositedon Cu(2500C) on Co(2500C)
Resistivity of Cu-Ni films as a function of The molar ratio [Ni++]/[Cu++]
97Y. Shacham-Diamand, Sept. 04
Electroless Co and Ni alloys
98Y. Shacham-Diamand, Sept. 04
Advantage of Electroless barriers
ConformalLow costGood quality - low ρ, low stress can be integrated with electroless copper
Barrier
Cu
ILD
99Y. Shacham-Diamand, Sept. 04
Requirements from barrier layers
• Step coverage on high aspect ratio holes and trenches
• Low thin film resistivity
• Adhesion to the ILD
• Adhesion to Cu
• Stable at all process temperatures
• Process compatible to the ILD
• Process compatible to CMP
• Act as a good barrier
100Y. Shacham-Diamand, Sept. 04
101101
Conformal deposition of electroless Co0.9W0.02P0.08
Deposition on periodic structure of 0.35 µm wide trenches with
0.7 µm pitch(a) several trenches and (b) close up trench(Shacham-Diamand et. al. Microelectronic Engineering 37/38 (1997) 77-88)
102Y. Shacham-Diamand, Sept. 04
CoWB capping, (Itabashi 2002)
103Y. Shacham-Diamand, Sept. 04
Dewetting of Cu from the underlying barrier material during high temperature and short time heat stress, which is typically observed after post-ECP annealing and post dielectric deposition/coating curing processes [T. Oshirnaet al, IEDM 2000].
104Y. Shacham-Diamand, Sept. 04
CoWP capping layer (IBM) slow down electrmigration: The resistance of a damascene Cu conductor, with and without a thin metal film on the top surface, vs time.
105Y. Shacham-Diamand, Sept. 04
Bright Field cross sectional
TEM micrographs of IMPTa/TaNx, IMP Cu andelectroless Co0.9W0.02P0.08
deposited into a damascene
trench structure.
overview
sidewall of a
trench
bottom and sidewall of a trench
top of a
trench
A. Kohn¤ and M. Eizenberg Y. Shacham-Diamand , To be published, 2002
106Y. Shacham-Diamand, Sept. 04
Summary
•• Electroplating and electroless plating are viable Electroplating and electroless plating are viable technology for metal deposition for microelectronicstechnology for metal deposition for microelectronics
•• It can be used also for MEMS and MEOMS It can be used also for MEMS and MEOMS applicationsapplications
•• Electroplating: typically acid bath, low pH, current Electroplating: typically acid bath, low pH, current dependent, superdependent, super--filling is possiblefilling is possible
•• Cu Basic bath can complement the acid bathCu Basic bath can complement the acid bath
••Electroless plating: Basic bath, high pHElectroless plating: Basic bath, high pH
•• Electroless plating: conformal, surface reaction rate Electroless plating: conformal, surface reaction rate dependentdependent