Thin Solid Films 429(2003) 231–237

0040-6090/03/$ - see front matter� 2003 Elsevier Science B.V. All rights reserved.doi:10.1016/S0040-6090(03)00407-3

Electrical and mechanical properties of low temperature evaporatedsilicon dioxideypolyimide dual-layer insulator for plastic-based polymer

transistor

Sung Kyu Park*, Yong Hoon Kim, Jeong In Han, Dae Gyu Moon, Won Keun Kim

Information Display Research Center, Korea Electronics Technology Institute, Pyungtaek, Kyunggi, South Korea

Received 17 October 2002; received in revised form 10 February 2003; accepted 14 February 2003

Abstract

Conjugated polymer thin film transistors have been prepared using silicon dioxide(SiO ) and polyimide films as the dual layer2

gate dielectric on a plastic substrate. The dielectric layers were evaluated to investigate mechanical properties, surface morphology,capacitance–voltage and current–voltage characteristics. Spun polyimide and low temperature ion-beam deposited silicon dioxidelayers were used as the gate dielectric, forming a dual layer structure. The organic layer with appropriate Young’s modulus wasfound not only to improve the roughness of the SiO surface, but also to relieve the mechanical stress of the dielectric, and2

accordingly bring about enhanced device performance. The dual layer gate dielectric indicated a good insulating property of10 Aycm at 3 MVycm, flat band voltage of 0.5 V, and root-mean-square surface roughness of 0.6;1.2 nm. Based on they5 2

experiments, we built high performance plastic-based P3HT transistor including 0.007 cmyVØs in carrier mobility and onyoff2

current ratio of approximately 10 .3

� 2003 Elsevier Science B.V. All rights reserved.

Keywords: Insulator; Silicon dioxide; Polyimide; Polymer; Transistor

1. Introduction

Recently, organic electron device based on a plasticsubstrate has been envisioned as a viable alternative tomore traditional, mainstream electron device with inor-ganic substrates such as glass and silicon substratesw1,2x. The performance of organic and silicon semi-conductor thin film transistor(TFT) on a plastic sub-strate has continuously improved in line with the requestof polymer electronic components. However, the appli-cations of the device on a plastic substrate are at anearly stage at present and the performance is much lessthan the device on silicon and glass substrates. Most ofall, the low thermal tolerance, poor surface morphologyand non-rigidness of a plastic substrate mainly accountfor the poor device performance. SiO films deposited2

on a plastic substrate by prevalently used plasma-enhanced chemical vapor deposition(PECVD) or sput-

*Corresponding author. Tel.:q82-31-610-4085; fax:q82-31-610-4126.

E-mail address: skpark@keti.re.kr(S.K. Park).

tering would suffer from high-energy ion damages, aswell as inherent hydrogen inclusionw3,4x. Moreover,mechanical distortion causes the compliant substrate tobend elastically showing considerable degradation in theintrinsic properties and adhesion of the oxide films.Particularly, when the SiO films are adapted to the2

dielectric of TFT device, the compositional and mechan-ical degradation induce considerable problems con-cerned with electrical performance of the devicew5–7x.In other words, the ion damages and hydrogen inclusionlead the dielectric to show high leakage current andhighly biased flat band voltage. As well, the mechanicalstress and rough surface of the substrate also cause thedevice to indicate poor electrical performance or failure.In this paper, we suggest an e-gun evaporated SiO gate2

insulator stacked with organic layer to relieve the stressand modify the rough surface, as well as for little troublefrom hydrogen atoms and low ion damage. Finally,based on the experimental results, we fabricated plastic-based polymer TFT device, and then investigate theinfluences of the composite insulator on the deviceperformance.

232 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237

Fig. 1. Schematic view of polymer thin film transistor using printed poly(3-hexylthiophene) semiconductor on plastic substrate.

2. Experimental

The poly-3-hexylthiophene(P3HT) TFTs reportedhere used a bottom electrode structure fabricated onplastic substrate as shown in Fig. 1. Preliminary, poly-carbonate substrate was pre-annealed for the reductionof polymer shrinkage and successively, SiO film with2

50 nm thicknesses was sputtered on the substrate surfaceas an adhesion layer of metal thin film and also as agas barrier layer. As a gate electrode, aluminum(Al)was deposited on the substrate. The Al metal waspreferred for its high coefficient of thermal expansionrate (25 ppmyK) and ductile property compatible withplastic substrate. Polyimide(PI) and SiO films, used2

as the dual layer gate insulator, were prepared sequen-tially with thickness of 40 and 210 nm, respectively.The PI solution(Nissan 5291) developed for low tem-perature curing applications, was spun and annealed at150 8C under vacuum atmosphere for 4 h by using alower gradient heating and cooling process. The heatingand cooling process used for all the device fabricationprocess were developed for minimizing the thermalexpansion problems and reported in detail in our previ-ous resultsw8,9x. After a vacuum chamber was evacuatedto a base pressure of approximately 10 torr, the SiOy6

2

powders were evaporated on the PI layer by e-gunsource at a pressure of approximately 10 torr. They5

acceleration voltage of e-gun source was 7 kV and theemission current was approximately 80 mA. E-gunevaporation method was preferred for little trouble fromhydrogen atoms and low ion damage. As a reference,SiO films were also prepared using RF magnetron2

sputter at 1208C with SiO target. Following the2

insulation layer deposition, thermal annealing at 1508Cwas carried out in nitrogen atmosphere. Gold source

and drain electrodes were deposited by lift-off in orderto prevent the electrodes from acid contamination. Final-ly, the solution processable polymer semiconductor wasdeposited using contact printing method under ambient.HP 4156B semiconductor parameter analyzer and HP8256 capacitance meter conducted all of the measure-ments concerned with current–voltage and capacitance–voltage characteristics. Morphology of gate dielectricwas measured by atomic force microscopy(AFM, Ther-mo Microscope Instruments). The measurements wereaccomplished with a silicon cantilever for contact AFM(ULCT-AUMT-B; contact mounted ultralever; forceconstant of 4 Nym and resonance frequency of 45 kHz),and the scan rate and area were 1;4 Hz and 3=3 mm,respectively.Mechanical evaluations were also performed using

the e-gun evaporated SiO films and indium–tin–oxide2

(ITO) films on plastic substrates. The film–substratecouples are placed over a rectangular hole and clampedby a ring. Pressurized gas is then used to deform thecouple into a cylindrical shape, which is carried outusing a miniature mechanical testing machine. Astraightforward calculation can estimate the radius ofcurvature. For quantitative analysis of the mechanicalevaluation, the stress–strain relations are monitored bymeasuring the variations of electrical resistance in theITO films using a four-point measurement technique asthe function of the mechanical stress(bendingcurvature).

3. Results and discussion

3.1. Mechanical characteristics

In this section, the mechanical properties of the SiO2

gate insulator including organic buffer layer are inves-

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Fig. 2. Crack or delaminating images of SiO film when bending2

momentum(bending curvature of 4 cm) was applied;(a) deeper crackand more crack density of the SiO film without polyimide buffer2

layer and(b) shallower crack and less crack density of the SiO film2

with polyimide buffer layer.

tigated. We assume the substrate to be isotropic in theplane of the substrates. If the plastic substrate is thinand compliant, the film–substrate couple bends into acylindrical roll instead of a spherical cap. Hence, weignore the coefficient of Poisson’s ratio in the followinganalysis. Under a specific tensile or compression force,the film–substrate couple bends and consequently, thebending momentum elongates the sheet in the uppersection of the film–substrate couple and compresses thesheets in the lower section. Between the elongated andthe compressed parts, there is a ‘neutral layer’ at theposition z where it is free from any stress. The neutraln

layer position ofz is derived from the condition thatn

there is no net elongation force acting on the film–substrate couplew5,9x.

t RØs Øts f fz s Ø (1)n 2 E Øts s

If a buffer layer is inserted between the thin oxidefilm and plastic substrate, the mechanism of stress–strain relation in triple layers can be analyzed in thesame manner. In the case of the sheet containing bufferlayer, the triple layer structure leads the neutral layer tobe located at a new positionw9x.

E Øt qE Ø t qtŽ .s s b s b RØs Øtf fz s q (2)n 2Ø E qE E qE ØtŽ . Ž .s b s b s

where s is the stress of an oxide thin film on af

substrate andR is the bending curvature of film–substrate couple.t , t andt , mean thickness of substrate,s b f

buffer layer, and oxide thin film.E , E and E means b f

Young’s modulus of substrate, buffer layer and oxidethin film, respectively. As shown in Eq.(2), inserting abuffer layer with Young’s modulus ofE , can changeb

the position of neutral layer. In the case ofE sE andb s

t <t , the neutral layer position moves toward metallicf s

film by t y4 compared to a film-substrate couple withoutb

buffer layer. In the case ofE /E and t <t , as theb s f s

value ofE decreases the position of neutral layer shiftsb

from mid-surface toward thin films. It is supposed torelieve the stress imposed on the films.When bending momentum or external force(bending

curvature of 4 cm) was applied to SiO films(210 nm-2

thickness) without a buffer layer, crack or delaminatingphenomena is occurred in SiO films as shown in Fig.2

2a, while Fig. 2b indicates the release of the phenomenaby using organic buffer layer(PI, 40 nm-thickness). Asmentioned above, theoretical consideration, the Young’smodulus of the PI was controlled by diluting withg-Butyrolactone(solvent) from 4 to 2.5 GPa. For morequantitative analysis on stress release, Bulge test corre-lating with stress–strain relations was carried out usingconductive oxide films such as indium–tin–oxide

(ITO), assuming that resistivity is increased linearlywith increasing of strain which is originated frombending stress. The changes of the resistivity weremeasured in a steady state by standard four-point probemethod after the stressing procedure and compared themeasured values with those of as-deposited films. Asshown in Fig. 3, the results are in excellent agreementwith the above expectations. In other words, the ITOfilms with appropriate organic buffer layer show a lessresistivity change corresponding to lower crack density.We think that the buffer layer plays a role of relievingthe mechanical stress. From these experiments, it issupposed that the composite gate dielectric allows themechanical stress that was generated during devicefabrication to be reduced, leading to high performanceof plastic-based polymer TFT device. Among variousorganic materials, PI was selected not only for highinsulating property but also for relatively lower Young’smodulus and low ion mobility at device operatingtemperatures.

4. Dielectric characteristics and device performance

P3HT-based polymer TFTs have been prepared usinga dual layer gate dielectric of PI(40 nm) and e-beam

234 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237

Fig. 3. Dependence of electrical resistivity increment of ITO films on vending curvatures and buffer materials.

evaporated SiO films(210 nm). The dielectric layer2

was evaluated to determine the best deposition conditionwith regard to the dielectric characteristics and theinterface morphology between the dielectric and thesemiconductor. The SiO films deposited on a plastic2

substrate by prevalently used PECVD or sputteringwould suffer from hydrogen traps and high-energy iondamage. The inherent hydrogen atoms from silane(SiH ) gas are not released by the low temperature4

deposition and consequently may cause a considerableamount of the traps associated with Si–H, O–H, Si–OH bondsw3,4x. We used e-beam evaporated SiO films2

with a refractive index approximately 1.3;1.5 similarto the refractive index of thermally grown SiO films.2

The refractive index was obtained by ellipsometry meas-urement. The ion-beam deposited SiO films on a plastic2

substrate, however, are quite rough with a peak-to-valleyroughness of 10;15 nm and a root-mean-square(RMS)roughness of 3;5 nm. The poor roughness of SiO2films on a plastic substrate is considered to be respon-sible for the rough surface of the plastic substrateincluding a peak-to-valley roughness of 10;20 nm anda RMS roughness of 5;8 nm. It is well known that themorphology of the gate dielectric is one of the influentialfactors determining the carrier mobility and insulatingproperties in a polymer TFT devicew2x. We have foundthat using PI films with a dielectric constant of 3.0,Young’s modulus of 2.5 GPa, solution viscosity of12"2.5 and thickness of 40 nm as an interlevel dielec-tric to planarize substrate topographies, the ion-beamdeposited SiO films have relatively smooth surfaces2

with a peak-to-valley roughness of 5;8 nm and a RMSroughness of 0.6;1.2 nm. Fig. 4a,b shows AFM 3-Dimages of the dielectric layer surfaces and they indicatethat stacked gate insulator composed of polyimide and

SiO is much more smooth than only SiO gate2, 2

insulator.Fig. 5a,b depicts the insulating properties and the

capacitance vs. voltage characteristics(C–V) of variousgate dielectrics prepared with metal(Al)–insulator–metal (Al) (MIM ) on the plastic substrates and metal(Al)—oxide-p-type silicon substrate(MOS) capacitor,respectively. The dielectrics used in the devices aresingle layer SiO film with 250 nm-thickness and dual2

layer PIySiO films with 40y210 nm-thickness. It should2

be noted that the leakage current and flat band voltagecharacteristics are improved by employing e-gun evap-orated SiO films subjected to N annealing. We think2 2

the low-energy ion damage of the evaporation process,and fewer electron traps associated with hydrogen atomsmay enhance the electrical characteristics. Moreover, thebeneficial role of the nitrogen annealing is probablyattributed to the replacement of some Si–O bonds withstronger Si–N bonds. However, because low temperatureevaporated SiO films have essentially lower atomic2

bonding energy, during high voltage stressing the atomicbonds are apt to be broken resulting in traps beinggenerated inside the oxide layer and at the oxideinterface w10–12x. They induce higher leakage currentand lower breakdown voltage compared with thermallygrown and high temperature generated SiO films. As2

well, poor asperity of bottom electrode, originating fromintrinsic substrate surface, induces high field emissionpoint and accordingly may accelerate trap generationinside the oxide layer and at the metal–oxide interface,leading to high leakage current. In the device fabrication,it should be mentioned that the composite dielectriccomposed of polyimide layer and SiO films leads to2

relatively lower leakage current. One possible mecha-nism on the phenomena is supposed to be due to the

235S.K. Park et al. / Thin Solid Films 429 (2003) 231–237

Fig. 4. Atomic force microscope images of gate insulator surface;(a) only SiO gate insulator, and(b) stacked gate insulator composed of2

polyimide and SiO .2

diminishment of surface asperities of the SiO insulator.2

In other words, the high field emission points nearasperities at the PIySiO interface will modulate the2

local trap generation rate and may lead to the reductionof sudden leakage flow. However, detailed experimentsabout the phenomenon are now working out separatelyand we will pronounce the results with enough discus-sions on the possible mechanisms.Whereas, as shown in Fig. 5b, the positive shift of

flat band voltage is supposed to be attributed to addi-tional charges existed in the polyimide–oxide interface.Sessler et al.w13x, Dumin et al. w14x and Hook et al.w15x have shown that polyimide exhibits various typesof conduction under various field and temperature andthus, ionic, electronic, or polarization currents are pres-ent. As well, Neuhaus et al. have suggested that becausesilicon dioxide is essentially impervious to penetrationby moisture or ionic charges, any conduction in thepolyimide produces effective sodium charges at theSiO –polyimide interface.w16,17x As a result, it was2

found that the flat band voltage of MOS capacitor withsingle layer of SiO isy2.5;y1.5 V, while the dual2

layer dielectric induces the positive flat band voltage

shift. The polyimideySiO composite dielectric indicates2

an insulating property of below 10 Aycm at 3 MVyy5 2

cm and flat band voltage of 0.5 V as well as a RMSsurface roughness of 0.6;1.2 nm.Fig. 6a delineates the electrical characteristics of a

printed P3HT TFT constructed on a plastic substratewith a gate length of 25mm, a gate width of 500mm,a composite gate dielectric thickness of 250 nm, and asemiconductor thickness of 0.25;0.5 mm. The satura-tion field effect mobility, threshold voltage and onyoffcurrent ratio of the device are 0.007 cmyVØs, 0.5;2.52

V and approximately 10 , respectively. Fig. 6b shows2

the output current curves of the device with SiO film2

as the dielectric. The device shows carrier mobility of0.00015 cmyVØs, threshold voltage ofy2.5 V, and ony2

off current ratio of 10. The increasingly negativex-intercepts with increased gate voltage are due to leakagecurrent through the dielectric, causing lower onyoffcurrent ratio, and poorer carrier mobility is attributed tothe poor flatness of the SiO films. The rough surface2

suffers from defects and voids, which are acting as trapsin semiconductoryinsulator interface, and leads to poorlyordered semiconductor layer on the surface that are now

236 S.K. Park et al. / Thin Solid Films 429 (2003) 231–237

Fig. 5. (a) Insulating properties of the gate dielectrics deposited onplastic substrate, and(b) capacitance vs. voltage characteristics of thedielectrics deposited on p-type silicon substrate.

Fig. 6. Electrical characteristics of contact printed polymer TFTs fab-ricated on plastic substrates including(a) polyimideySiO as a gate2

dielectric, and(b) only SiO films as a gate dielectric.2

investigating using wide viewing angle X-ray diffractionmeasurements. The poor ordering and defects probablyimpede the movement of charge carriers through thesemiconductor layer and the interface region by scatter-ing and momentum transfer of the carriers to phononsin the polymer semiconductorw2x. It is considered thatthe employment of polyimide layer causes the gatedielectric to platen and to close the holes of the SiO2

and thus the leakage current drops. The device with thedual layer dielectric indicates constantx-interceptsaround 0 V regardless of gate voltage, showing relativelygood carrier mobility. As shown in these experiments,in the case of a plastic substrate with poor surfacemorphology as a base back plate of polymer TFTdevices, a polyimide interlevel dielectric improves theelectrical properties of the devices although being acertain potential for transfer of contaminant ions fromPI to SiO films. Reducing PI thickness and adjusting2

of annealing temperature lead the devices to show theminimal flat band voltage shift, which has negligibleeffect on the device performance.

5. Conclusions

Conjugated polymer TFT was fabricated successfullyon a plastic substrate using organic and inorganic filmsas a dual layer dielectric. SiO films deposited on a2

plastic substrate by widely used sputtering would sufferfrom high-energy ion damage, leading to high leakagecurrent and much negative-biased flat band voltage. E-gun evaporated SiO films subjected to N annealing2 2

show enhanced insulating and capacitance vs. voltagecharacteristics. The low-energy ion damage, few electrontraps associated with hydrogen inclusion, and nitrogenradicals are proposed to account for the improvedproperties. Also, the significant rough surface and verycompliant property of plastic substrate are also respon-sible for the poor performance of the polymer TFTdevices, such as low field-effect mobility, low onyoffcurrent ratio, and unstable output current behaviors.Spun PI films are proposed as an interlevel dielectricnot only for relieving the mechanical stress imposed one-gun evaporated SiO films but also for plannerizing2

the rough surface of the plastic substrate. As a result,we obtained high performance plastic-based polymer

237S.K. Park et al. / Thin Solid Films 429 (2003) 231–237

TFT device including 0.007 cmyVØs in carrier mobility2

and onyoff current ratio near 10 with a typical transistor3

behavior.

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