~~x~*~~+*~~~±*A*~~~~

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The following equations are for drain current in a nMOSFET. They may be useful in your answering the following questions.

Io(triode)=k0(WIL)n ((V Gs-Vtn)V os-0.5V os2)

l 0 (saturation)=0.5kn(WIL)n (V Gs-V1n)2(1 +AVos)

where kn =J..LnCox· V1n is threshold voltage. The subscript n denotes a n-type MOSFET. A= lN A is the channel length modulation factor.

(1) In the following circuit (Fig. 1), Q2=Q3 (matched), V1n (threshold voltage) =IVtpl=l V; J.lnCox=2J..LpCox=20J!AfV2, (WIL)p=2(WIL)n=l00/10; V An(Early voltage)=!V).ri=40V. Neglect the Early effect for DC analysis and when evaluating the transconductance gm.

(a) Find R to obtain lR=200J..LA. (3%) (b) For the circuit to have maximum small signal voltage gain, find the DC bias VI, the DC output current Im, the mode of operation of Q 1 and Q2, and the small-signal voltage gain of this amplifier. (9%) (c) If the DC bias VI=2V, find the DC output current In 1, the DC output voltage Vo, the Ql and Q2 operation mode. (3%)

\ '!

~· .!'.'

(2) In the following TIL gate (Fig. 2), assume all thansistors arc identical. VBE(active)=0.7V, VBE(saturation)=0.8V, V CE(saturation)=O.l V, t3F=l00, f3R=O.l. fan-out= I.

(a) Specify which region (forward-active, reverse-active, off, saturation) each transistor is in when Yin is logic "1 II. ( 4%) ~n~Q11: ~n:l '/aso.n. (b) Specify which region each transistor is in when Vin is logic -I - I r\~u. .... J r.u 11

011

(4%) -- 1---f~ ut"T J"' I n., ~3Sk-l (c) At tJ1e instant when Vin switches from II l" to "0", specify · V;t~____.tf':'t,\-. ~u..- .1. 1;---~ V .. which region the tf::l_nsistor Q 1 &'1d Q6 are in. (2%) • '"' 1 ::. I ..

. I ,): a; (d) If Q6 is removed (i.e., R2 and R5 connected to ground directlv). sketch Vo versus Vin and srecifv the voltages at the break~ints. (6%) • ~ ~ ~- 1- -~' ~: ~~ JKs< ~·J~!

_,'l(QG,

h-,.2 ~

m~~~*•~+•~&4~•A•~~~~

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(3) The following four circuits have errors. Please briefly point out the error in each circuit and redraw the correct circuit. ( i2%)

( U) BJT Ckt~ ~imr (b; 8JT CE-C6 C1.r~ ~l.frer

Vee

Re

{d) 8J7 C E .J,,t.-j-e,.. ~c

86

(4) Assuming the Op-Amp is ideal in the circuits in Fig. 4(a) and 4{b) with +5V and -5V output saturation levels.

no· +<~ ~- +<") (a) Sketch and level the transfer characteristic of v0 versus vi for each circuit. (9%) (b) For a lOOmV-amplitude sine-wave input having zero average, what will be the waveform of V0 t and V0 2, respectively. (6%)

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(5) In Fig. 5, the Op-Amp is ideal but with the input offset voltage V 05• The power supply voltages of the 0p-Amp are +5V and -5V.

(a) Assume that VI=0.5V, Vz:::::l V and Vos=:OV. If the switch S is closed, calculate Vo. ( 4%) (b) The same as in (a) but with the switch S open and 1-negJigible switch transients, calculate Vo. (4%) : V, +

(c) The same as in (a) but with Vos=+5mV, calculate Vo. (4%)

'

(6) The following circuit (Fig. 6) shows a feedback amplifier,

(7)

(a) Identify the feddback topology of the above amplifier. Calculate the feedback factor fl (7%) ---------1

~

(b) Identify the feedback type, positive or negative feedback? + why? (3%)

(c) Replace the NMOS device Q3 by a pMOS device and keep all other circuits unchanged Draw the PMOS Q3 amplifier stage. Identify the feedback type. (5%)

In the following CMOS inverters, assume the k and WIL of ail nMOSFEfs and pMOSFETs are the same . V m==0.8V and Vtp=-0.8V. A=O Voo ~ SV

'

= -(a) Determine the range of V0 1 for which Nl and PI are biased in the saturation region. (5%) (b) IfVo2=0.6V, determine the values ofV03, Vol and VI. (10%)

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I. The source follower in Fig. I has a saturated load_ The transistor parameters are Vt(threshold

voltage)= ! V, and k=2mAN2

for transistor Ql and Vt= IV and k={)_2mAN1 for transistor Q2.

Assume that the channel length modulation factor A.=O for both transistors and V0D=9V

(a) (4%) Determine V GG such that the quiescent value of V 05 ofQ2 is 4V

(b) (4%) Assume RL = oo, please derive the small signal voltage gain.

(c)(6%) Please calculate the small signal voltage gain for R1. = I Okn

(d)~) Please detennine the output resistance R., .

The current equations in nMOSf-ET are in the following:

lo(triode)=k((V Gs-Vt)V 05-0.5V0 s ::?.)

10 (saturation)=0.5k(V Gs-Vt)2

v~ -..L..

_I 1J· I

2. Consider the current mirror shown below, in which I a = I rnA is an ideal current source. The

BJTs, Q I and Q2, are identical, and have the following 1-V characteristics in the forward-active

region:

where Is is the saturation current, V,. = kTj q is the thermal voltage, VA is the Early

voltage, and {3 1_. is the forward current gain. Assume V1u:

1.,

11, = 0.8V and V

0 = 2V

a. [6%J Find 111 if {3,.. = 20, and VA = oo .

b. [8%] Find 10 if {3,.. = 20, and VA = l 0 V. ;; ..

vee

mA

VFF

R ..

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3. Consider the transimpedance amplifier shown below, where I, is the current input and V, is

the voltage output. Assume all transistors are biased in the forward-active region. Let

g 1111 = gm"2 = g,J = 4 mA/V. Assume r, = oo for all transistors, and consider only C,

and C1 for capacitive effects.

a. [6%] Let R2 = I k 0, calculate the de loop gain A[J of this feedback circuit.

b. [6%] Let C 1 = 0 and R2 is adjusted so that the de loop gain A[J =50, what is

the - 3dB bandwidth of this transimpedance amplifier?

c. [7%] Let R2 be adjusted so that the de loop gain A[J =50, what is the maximum value

of cl to achieve at least 45"phase margin for the feedback loop? Hint: cl < C,.

VOD T

R1 1k.Q

VDD

R4

11<.0.

R3 1k.Q

,.,. ;.~, ..... ' . . :.- t;

,) ,.:' I' • ~

4. The following is a push-pull power amplifier. The input signal has a triangular waveform as

shown below. The load RL is 5D.. The average powe1 dissipated in the load is I OW.

a (5%) What is the minimum value of the suprly voltage, (Ycc)min

b (5%) When Vcc-=(Vcc)min, what is the average power dissiration in transistors Q I and Q2?

c (5%) When Vcc=(Vcc)min+5V, what is the average power dissipation in Q l and Q2.

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,,

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5. A CMOS astable circuit is shown in the following. Clamping diodes are connected at the input

terminals to prevent the input signal from rising above V00+V0 and falling below - V0 (Vn is ihe

diode voltage drop). Assume ~m<<R and Y,h=0.5Y00 where R0~ ;md V,h arc the output

resistance and the threshold voltage of the CMOS gates respectively.

a. (6%) For Y n"'OY (Clamping diodes arc assumed ideal), sketch the waveforms of Y ll· Y 01

andY 02 and derive the period T Is the period T a function of V oo?

b. (6%) Repeat (a), but now for V 0 =0.5V, is the period T a function of Y 00 ?

R

c .......

L----------------+----~t--~

6. A circuit of a NAND gate is shown below. Inputs A and Bare connected. Assume 13~=30, f3R=O.l,

VsE(sai)=O.SV, VcE<satJ=0.2V and neglect leakage currents.

a. (5%) For Yr=OV, find numerical values for 101 , 102 , 103 and Yo

b. (3%) Estimate a numerical value for Y1 when V 0 switches to logic zero.

c. (14%) For Y1=4.5Y and use Y0c 1=0.6V, find otHnerical values for In" ls2, ln. 11n, ICJ and

Yo and determi;1e the region of operation for Q I, Q2 and QJ.

l I ~lo~D. I· Io: (He,

--~-, Q).

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:i •j ;l ,l ~ ;

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(I}Considerthe following circuit and its input waveform V1 shown below.

(a) [6%] Draw the V0

wavefonn. Assume the operational amplifier is id.eal, and without input offset

voltage and bilas current, i.e., V0s = 0 V and I 8 = 0 rnA . (b} [7%J Draw the V., waveform. Assume the operational amplifier is ideal, except that it has a non-zero

input offset voltage, i.e., V os = 0.5 V and I 8 = 0 rnA. \ . (c) [7%] Draw the ~ waveform. Assume the operational ampHfter is ideal, except that it has a non-zero

input bias currtllt, i.e., 18 = 0.5 rnA and V os = 0 V.

Vt (Volt)

R1 +2

+1

Cj Ia 11&

vi-; 1J.IF Vo. Vo (Volt}

-

4 • • ~ - - ~ · 1 msec · 1 msec · 1 msec ·

\ \~·- ' > ,' ;' '~ {(,,1

(2) In the following circuit, the current equation for a MOSFET in saturation region i:~to~sk(v~~:~)'~. VtCnMOS)= -V1(pMOS)=2V, k(nMOS)=k(pMOS}=50~2• R=lOMfl and Cis sufficiently large.

(a) [6%} What are the DC current and transconductance (g.,) ofQl and Q2?

(b} [100/o) lfV A(Early voltage)=l80V, what is the small signal voltage gain vJv,?

(c:} (4%} For what range of output voltage do Ql and Q2 remain in the saturation region?

Jt(,V r-4~ Q.:t r-TrtJ :~v.

Vs~ ·~· Q' L

-1+'1/

t

t

1

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(J) Consider the amplifier shown below (Fig. 3). Let g.,1=&n2= 5mAN. and g,3 = 2.5 mA/V when switch is

closed. All the MOSFETs are operated in saturation region. Neglect channel length modulation effect .

A. ff switch is open, aruwer the following questions.

(a) f5%J Small signal DC gain VoNi = ?.

(b) [5%] - 3 dB bandwidth ofVo;Vi ~?

B. If switch is closed, answer tlte following questions.

(c) [3%] What kind of feedback topology (shunt-shunt, series-shunt, shunt-series, series-series) is utilized in tiis amplifier ?

(d) [7%] Smafl signal DC gain Vo/Vi = ?.

(e) [5%}-3 dB bandwidth ofVoNi =?

VDD

10k.Q 1k.Q

10nF

c Vi +--j

r 'switch

M3 J t-j --~-...•- + f Vo v v-

Fig. 3

L---:-----___...,_.- - -

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(4) A circuit ofMwtooth waveform generator is shewn m Fig.. 4{~) with a Schmitt trigger followed by an

integrator. The limiting levels of the Schmitt trigger are +Vz and -Vo. The output tciangul,a.r wavci'Of1!1 is

shown in Fig. 4(b).

VTH-- --I

I ' I

: I Vn .. ___ -:- ---- ---- r .

~1\lt-- T,. )o[

(a) [l(}QAt.) Find Vn.. Vm. T1 and T2 in tenns ofVz, Vo. R" R2, Rand C.

(b) [S%} For V~.JV, V0=!>.7V, R~1'=3n and RC=2.lxl0-J sec., sketch and level the triangular_

waveform. What is the frequency of oscillation of the circuit ? .-.:·i" . . .. ' ~ ...... ,. '•

lS:···. . ~ ~~::. :;c (S) For the ECL circuit in Fig. 5(a). assume that the base-emitter drop of an ON trans:isror is 0.8\f""a:li(fcut-in--~-

voltage is 0.6V. VM

~\... \hl1 th

---·------

Vo" hd· 5'(~)

Vs

0...

1',.= -l v -Ya(-S.2V) Yr=-2V

~.S'(') J..

(a) [6%] Cal.culate Vu... Voc. Vm, VOH and noise margin NMn and NMc:. of the OR transfer characteristic as

shown in fig. S(b ). Ignoring the base current when cakulating V oc. but using P=99 to calculate Voo.

(b) [4%] Recalculate Va, Voc., Vm, Voo, NMa and NMLwhen the 500 resistor RT isreplaa:dby 50k!l.

(c) {S%] The NOR transfer characteristre is shown in Fig. S(c). It bas four distinct regions as indicated by

segments ab, lx; cd and de. What are the corresponding transistor modes of operation (cut-oft

active or saturation) of Q,.. Qa and Q3 for each segment?

(d) (2%) Explain why the ECL circuit employs a negative power suppty and the Vee line is COMected to ground?

lloti

VoL

~CIIt

~

e

(l) For the circuit shov•<11 bdm.,·, assume th~ opemtional amplifiers are ideal.

~ R I

,

(a) Find and plot the transfer characteristic V01 as a function ofVt. (8%) (b) Find and plot the tran..sfer characteristic Vc as a function ofV1 (8%)

(2) Consider the differential amplifier shown below. Let (\V/L)Ms : (W!Lhto '""'· i :4. Assume ali the devices are operated in saturation region. and R;_ is much greater than :,.

• I i l

25mA ~

vna

t T T

~Fhv• + -- u: f.t1 M2 p ~ VI 'l ! I

t-. J M5 ~ t-! _.l,.__ _ ____, 4, M6

~ ~

{a) lf~ll and r-.n. M3 and M4 are perfectly matched, rc,= r"2 = r~3 = ra-1= r.,o =lOOk~), f5_-r.,

= g"'.: = &n3 = g.,,4 = : mA/V. Derive <he small signal diiferentiaf mode ·voltage gain Adn

and common mode voh.age gain A:.rr.· (12%) (b) If\W/Lh,~: (\Vil.) l\c? = 100: 99, (W/L)~.n: (\V/L ) ~t4 = 99: lOO, I.L nCox(\V.'L.h!· ~~ 0.1 mAfV·, and .u.nC,x (WtL)Mz =0.099 mAN2 ~eglect channel length modulation etlect (r0 ). find the input offset voltage . (4%)

......

t3) A pass-transistor logic circuit is shown be!o·w ,..> (

,•.

.:;_::

\_a) Determii:.:: the truth tab;e for this circuit. \\ihat logic funcrion does it imp!ement"~ (8%j (b) In this circuit, the p-MOSFET Mp is a weak pull-high device. Assume the input signal

at nodes A orB has a voltage level of SV for togic "1", a.'ld a voltage level of OV for logic ·~o··,)J.n=3Jl.o, and the threshold 'vOltage :Vrpj=Vtn=0.6V. Without considering the fan-out effect at the node Y, how to design the ratio of [ (\V/L)n / (WiL)p } to get a 'oltage level of iogic "0" belo\v 0.5\! at the ouiput node Y? (8%)

I !

~ ?fl" J)l >i1] : itt -f-~ 1E F1T * ft: $ fltr, tt ;'cA~ itt~~ ,

(.f) tn the fullO\\ ing C\10S circuus. the current equation in the nMOSFET i~ as follows:

lo=k {Vas-V J" !n=k (2(Yos-Vt)Yns-V,;/)

{saturation region) (triode region)

where k=0.5pC0 x(W/L) and V\ is the threshold voltage of the n\'lOSFET. The current equation in the pMOSFET can be derived likewise. V 00=5V, k(nMOS)=2mA!V2

.

k(p\-fOS)=0.5mAtV:_ V:(nMOS)=0.6V, V,(pMOS)= -0.8V

(a)

~eki~l flr,e

\ ' --- ~

t~ v, v~.J

(b) (C)

{a) For a Cl'vfOS inverter (Fig. (a)). the Yo versus Vi is sho ... vn in Fig. (b). Please calculate the values ofV~, Y:. Y;. V4 . (8%)

(b) In a C:VIOS amplifier (fig. (c)), what is the \aluc of \'\;c that the small-signa! voltage gain A,=vjv, has a largest Yalue ? For RL=lOkO, C=x, what is the maximum small-signal voltage gain? (8%)

(5) Consider the feedback amplifier sh0\\!1 belov •. Assume all ihe ~10SFEE are operated m saturation region, grr: 1 -== gm: = I mA 'V2

•

( \

von

~ 10kQ

-d ' Cp ~Vo1 '" <t-l' 't l M2

1nF t-- Vo2

I ' r I I I cbls I r I

.... v OOkQ. ~1kQ

(a) If the output voltage is taken at V 0 :, which feedback t-ype is adopted !n the ;:;ir(uir lshunt-shunt. shunt -senes, series-shunt. series-series). (3%)

(b) If the output voltage is taken at V02, wh1ch feedback type is adopted in the circuit (shunt -shunt, shunt -series, serics-sbunt, series-series). (3%)

{c) Find the low frequenc) small signa.! gain ofV, 1/f,. (7%) (d) Tf Cp = i nf and neglect a!! the other parasiTic capacitances. Find the -3 dB

bandwidth ofV~~/ls. (7%)

·-----1

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, (6) Consider the class B output stage, as shown below. Assume the devices have JV1i=JV, }lC0 ,(WiL)=200mA!V2

, and the load resistance is very high, i.e., Rr-+o::·; +WV

v,~~v, '+'

-!OV

(a) Plot the transfer curve \ 0 versus v, and indicate the input vcltage range and the output voltage range. (8%)

( b) When a bias voltage V G{j is applied bet·ween the gates of the two MOSFETs, the circuit becomes a class AB output stage. What value of V GG is required to reduce the incremental output resistance R, in the quiescent state to l OQ '! (8%}

' .. _;;.•

I

i I i

_____________ ___j

·--

(1) A differential to single-ended amplifier is constructed as shown in Fig 1. The amplifier

incorporates Wilson current mirror as active loads. Assuming all of the transistors are in

saturation, Jl. nCox = 80 Jl. AN2, Jl. pCox. = 30 Jl. NV2, IVTI = 0.8 V for both NMOS and

PMOS, (WIL)M1 = (W/L)M2 =320/0.6, (W/L)M3 = (WIL)M,. =(WIL)Ms = (W/L)M6 =20/0.9,

(WIL)M7 =80/0.6, (WIL)Ms =160/0.6. Neglect channel length modulation effect.

(a) (3%)What kind of feedback mechanism is applied in the Wilson current mirror 1

(shunt-shunt, series-series, shunt-series, series-shunt)

(b) (8%) Find out the input common mode rages Vicm(max), Vicm(min) of this amplifier.

(c) (6%) Consider the circuit shown in Fig 2. Assume that (WIL)M3 = (W/L)M6 =2110.9,

(WIL)M• = (y/IL}Ms =19/0.9, and the other devices' sizes remain unchanged. If Vi =

2.5 V, find Vo. (lbe OP's input offset voltage must be taken into account).

(d) (8%) Follow (c) and neglect all the parasitic capacitances of MOSFETs. If Vi is a

rising step from 2 V to 3V, find the slew rate ofVo. If Vi is a falling step from 3 V to

2V, find the slew rate ofVo.

5V 5V

(c) VI 2.5V

" ·' ' '.

Flg2 ~~. ,.

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(2) A two-stage cascade amplifier and its small signal equivalent circuit are shown below.

The first stage is a common source amplifier with source degenerated resistor. The

second stage is a shunt-shunt feedback amplifier. Assume that the MOS has infinite

output resistance. Here &nt=~= 10 mAN, Cgs,=Css2=20 tF, C&d1=Csc12=0 fF, Rsig=45 k!l,

~= 5 k!l, RF 45 kn and R.r5 ill.

The voltage transfer function can be expressed as follows.

A iol ( ) V out ( )

( 1+~](1+_s J = Vsig s i:;- 8

mP, mp2

(a) Please calculate Avo. the de voltage gain. (6%)

(b) Please calculate the first pole,c.op" corresponding the first stage io1Nsi&· (6%)

(c) Please calculate the second pole, c.op2, corresponding to the second stage Vourfio1• (6%)

Note: The effect of gate-to-drain capacitances on the frequency response can be neglected

because the shunt-shunt feedback reduces the input and output impeda_l!Ces of the second J

stage.

' . ,, ;..'•.

l

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-!ts\:. a ltlJ : 94 !- 4 A 10 a J 2 !P J. olf.:z. *' rJtJ)!.$'1 : ~ ~ e. 8 1-£ m)JIJ : m ~ 3 J!, *' 4 J! *1f$1W.tt;t.~f.f~,t!" $*4 (~4) 1!-iit~~J:..:t..PJTMI.JJ•l$!.~~#§ Jl1l~1~!!

(3) A Wien-Bridge Oscillator is shown below where Op-Amp and diodes are assumed ideal.

LetR3 =5 kQ andR.= 1 kQ.

+15V

01 R3

Rl

R4 R2 1'>1' •.•• "-.\\

."1~ .•

!i

10k

R4

-15V

(a) (8%) Derive the expressions for the oscillation criterion and the oscillation frequency in

terms of R" R2, R, and C. Also calculate the minimum value of R 1 and oscillation

frequency fo.

(b) (8%) Derive the expression to estimate the amplitude of the output oscillation voltage

and calculate the amplitude.

(c) (4%) Assume that R 1 is greater than the value required for the oscillation criterion with

the clamped amplitude, V ..,.. Note that without suitable design of R3 and R4 the clamping

circuit will not work properly. Derive the expression for the clamping criterion in tenns of

R., R2, R3, and R..

(4) For the circuit shown below, the OP-amp is assumed to be ideal. And the diodes are also assumed to be ideal but with the cut-in voltage of0.7V.

R1=2Kn Vi ~ R4=8K.n

01 Vi2=2V __ _, ~J...---@

Vi2=4V _j_ ideal OP amp

(a) What is the maximum output voltage (Vo)? [4%] (b) If the input voltage (Vi) is 0.2V, what is the output voltage (Vo)? (4%] (c) If the input voltage (Vi) is 3V, what is the output voltage (Vo)? [4%]

Vo

(5) In the following enhancement load amplifier, the two transistors are identical. V 00==5V

and V GG=2.5V. vi is a small-signal voltage source.

The measured transistor I-V characteristics are shown below,

Vos{Volts)

3

3

2

Vos(Volts)

3

4

4

los( rnA)

82.4

83.2

20.8

(a) Calculate the threshold voltage Vt and channel length modulation factor A of the

transistor. (6%)

(b) What are the output resistance and the small-signal voltage gain Av==vJvi of the

amplifier? (9%)

(6) In a given CMOS process, assume the propagation delay of a specified inverter is 11101

nano-second under the supply voltage V 00 of 3V. This specified inverter has an input

capacitance ofO.lpF and an output capacitance of0.3pF.

(a) What is the output frequency of the ring oscillator that is formed by such specified

inverters with 101 stages in cascade? (5%) (b) Neglecting the short-circuit cu."Tent, what is t.i-}.e averaged power consumption of the

ring oscillator that is formed by such specified iuv~~ v.'it.ltlOl st.ages in cascade? (5%)

(&~t~Jiff~95- 1 ···· ·· ···· ·· · ·· ·········-· ···· ·- -··· ····· ····· ····· ···· ·· ····· · ·· ··- ····· ·· ······· ··· ·· ···· ---··· --- ·-····· ··· ···· .. ······ ···· ·············· ·········· ·•· ·· ··· .. ·· ·· ··· ··············"''''''' ' ' ' '

---'L,:.Immm ~~!smmm ~~m~T:J ?Jil.l~ : ~~PJT(Efl, Z*Il)

1. *~;f£~k~ '1Jt.1."t- MOSFET it1f-_z_ W, L ~Gate Oxide Jl-)j_ 1§-f,ffi

~~~*~-~,~~~~*it#~--#~~ o M~~~_z_~~t ~T~ MOSFET,(l)Id tf_~~ *~ ~1%? (2)Cgs ~~~ *~ ~1%? (5%)

2. ~ T ~ iL t ~11§J n-Channel MOSFET ~ ~ $ t ~ V1 JS] ~ 0.5V ' ~g_

:1f Body Effect' it1f- JZ. -t ~(WI L)Q1

= 4(W IL)Q2

= 4(W I L)Q3

' ~-M;it1f- .$-

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5V

' 4V~

,c I.

.\ ... \.' ...

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Saturation) o (I)'&" Vi = OV a-t; (2)'&-Vi = 5V a-t; (3)'&-Vi =Voai- o (5%)

4. -100 CMOS &.i!:l ~(Inverter)~'ltt~~T~iLF!f-F o '&-~.ti.Jtl:l flUlJ

~ iX. it Z- (CL) ~ lpF Bi- ' ~.ti.J tl:l1t ~ (VouJ ~ Fall Time (90% Vnn f 1]

10% Vnn _z_a-t.f~)~ 2ns o -;ko ;Jfd~&.i!:l ~ pq ~NMOS (M,.) it14- JZ. -t (WI L)

~*~~;f-.~ ~m1% ' PMOS (Mp ) it14- JZ. -t ~ ~ ' JL.ti.J tl:l f.&.~~ iX. it Z. (CL) fit fiX.~ 2pF' ~Jjt~-f;f,j tl:l1t~flJ Fall Time~% ~y ns? ( Mp ~ Mn it1f­

a9 '* .1.. t z..~,~~ tt) (5%)

.. ?!5..~~-~~ .. §.!t~~t.~~~@#~~ .................................................................. ................ .............................................. .

VDD

rl:I ,:·~" V._j ~V""' :

I . ~ 1 2 sv ----------+-- -y c '' M T I. i i . ' '

' ' ~----+-+-4===~~ GND OV 3V 3.5V 4V 5V

5V

v,

OV

5. E. 9;o - 100 CMOS &.. ;f§ 5 &.. ;f§ 5 (Inverter) ff-1 Voltage Transfer

Characteristic *0 ..l.. ~ ii .PIT iG 0 ro, J:!:.&.;f§ 5 ff-1 Noise Margins (1) NM H ' ~

(2) NML ~~ !P y? (5%)

6. ~ r &i] .P!TiG '1f liB100 ~~(~a~~ b);f~ -k jfJJi CMOS Logic .z..NOR

Gate, J:c~100~~ff.J7(Af-JZ-t(DeviceSize)'*';f§~ oro, (5%)

(1) ·~-100 ~~-t":il:if& Body Effect ff.Jt.J~? (2) Body Effect -t"ftil:c

NOR Gate .Z.. tPHL .tkl& 1t Jf t.J ~ ? (Pg /}fl , /F ~ , ~-ki~Y )(3) Body

Effect -t"ft Jl:c NOR Gate .Z.. t PLH .tkl& 1t }j, t,J ~ ? (J'.!t /]fJ ' /F ~ ' ~ -ki~ y)

• ..

'\.1 ,.., ...

(~a) CliMb)

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~ o tt t~ J±: M 1 ~ M 2 -Z... (WI L) 1R.. #- ~ (b).Z.. 3f! ~ ~ ~ 1f ;f§ ~ ff.J *ft. 2

...... .. .................................................... .............................................................................. ~~-~f.!..~-~-9..?.~} ..

(Worst-Case)J:_ ft-Bi- M ~;l!:. T Ff-Bi- M o (5%) VDIJ

15/1

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v, V. A --1 8/1

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8. -_ko J..:l. T it ~ IE i£ f'fT 7r- o 1~1 i'~ Ql it a8a ft. fA VBE(on) = 0. 7 V J..:l. .&.

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2mA

21ill

lkD

9. J:.. ~ ;fJ rf C--+ 00 ° ~ s8afit-Z... VBE(on) = 0.7 V ' VCE(sat) = 0.2 V ' /3 =50 '

Them1al Voltage Vr = 25 m V o t~ J~ tl:: Jl:c 1Ji ;k ~ f!] '1, -m ~J}t it ~ :I:W ~ '

Au= V0

lui o (5%)

10. T ~ 'f .1! ~ 1Ji :k. H ,~ JJ. !l ' Slew Rate -~ S ' ~A 't l!f_

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c R vi ---11---...-'V\J'v---....--- vo

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'-------+---v;,

lOk.Q

5V

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4

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14. J:_ lli] ;5 't Iii-k -100 Common-Source Amplifier with Active Load o 't a8a H. Ml .&. 't ;)fiUlt. I I J!-:13 {EJ liD a1 Output Resistance ' ro 0 4'- vi ~ft ~Jt;)J,t ai] tf? t!:: F.li~Jl:.~ 0 ' 5!Jl Jl:I::.;QtA E 81 Transfer Function or~ J#.. : A (s) = V0 (s) = A M l + slmz

u ui(s ) l +s l mP

.5K(l) AM ; (2) mz ; (3) mp -Z_ /~ A 0 J.-:l-. g m ' ro ' c gs ' c gd :f<..7F 0 (5%) •

15. 1f -@J~;QtA E ~Tllil f'IT7G o %--It Loop Gain ILI = IA.BI » l ' ->R Jl:I::.;Qt;k.~-Z...'t~J:>gJ;aAuf =U0 1ui EJ10.:i( 0 £J.R1 'R2 'R3 'R4 'R5 'R6

:R7G o (5%) -·.,

R s

R,

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5

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9 ?..~?-~~--~~~?!~1i!l~~~W!.~ ................................................................................................................................ .

16. T IE .Z. 't 4-ft. :r.fJ fiE. 7~:Jl¥- 't ~fit I i ~ ;f~ 1.!; 't ~ Vo o 't ~i'fd; ~ - J.! !l 't ~~oiE~~A~-t~&AS'-ft-~Am~~oo'~ilim~~O'~

Jt~oo ''%~:!:'3~1.l;Av o 'tJi:C.'%4-Z.:!J;~J[(Bandwidth)~m8 =10 9 rad/s Bi- ' tt:A ill fJT ',W; .Z.&;k ~ ~ + Av {itt ' ~;?JL.R, Au min ° (5%)

10kn

17. :ko r;. T ~&A B 't41E fiT 7F o IE ~ ~ ~100.1!Jt.&A B ~ R; = oo • Ro = o ' rriJ -ft. Open-Loop Voltage Gain :ko IE .:6 fiT 7F ' 1f -100 1 OOI-Iz siJ Pole o Ji:C.&A S ~ Transfer Function Of~ 1#. : A(f)=vo(jf)=A 1

v J U;(jf) M (1+jff(p1 )(1+jff(p2)

-''R(l) AM ; (2) fp1 ; (3) fp2 .Z. {t o (5%)

A,(dB)

1201----,.

18. 1f -&A~ ' -ft. Open-Loop Gain 1.!; : 105

A = ----;-----c-;-----c:-:-------:-

" (1 + j -4)(1 + j ~)(1 + j ~) 10 10 101

100 freq(Hz)

1i * ~ @1 #'::Ot ;k ~ Bi- ' A" /F & ~ ' rriJ Feedback Factor fJ k jf it o

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6

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tt .J:.J.. Piecewise Linear Z. Bode Plot .;t_M ' r.J.. r~ 1b tt 4 o

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mW ~1;-1ft o (5%)

5V

.,_

" '· ' ' , .. ~( r :·, .:)

20. -ku ~.J.. T 'tll!i! f!T-F o 11k -1~ JfJ &..:fEI E(Inverter)jJl~ EI-J.:f&j{_ E o liD ~k&.~BEI-J#tlo•aill~.:J.&j{,EEI-J.:f&~M$-o~o~lli~~~o

tk)i- ;t ' &..:fEI E EA tif.J AA'i'r; ~~~ /Ju J:..1£10J Clamping it li! ' jt.fif.J AY#6 Ef] 't ~or~ t1:: o~5v E~-J j[ oo o (5%)

7

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~~tl:l? 2R

IH((JJ ) I (dB) R

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2. ~o J:~J::_ 't$E ~ ' -!t- 'f EIJ ~100.1{$-:a*-(Operational Amplifier)~:£.!

tB 0 ;~-; it i!f ~ilK JBir ~ A = Vo 0 ~~ .,....J'.. / "' "'t:.. 1'1£. a .:on. v

~ 3. ~oJ:~T't$~£f'!TiG o Jt'f~.!f$.&*-~(Operationa1Amplifier)1f

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foJ1~~(Forward Bias) Hi- ' Vo=0.7V o 1; Vi=2V Bi- ' tt~ tl:l V0 ~ 't~ o

5V

v.

v;-j

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ro = oo ' V oo=2V ' #.]A i!t J!f ~ 0< Vi <V DD ~II] 0J ft. it ~fit i ~ 1f -Jl'k ;k

11 ipeak' %~1~ ipeakifo\+~~*-2:..114' ;Jt?!T't2:.. Yon i!t& o

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8. -100 CMOS &.;fJ:J ~ (Inverter)a\1 't~:ko __L mJ -:6 ?IT iG , ;(f_ ;'t -;j~ Jt a1 CMOS tL;t£ T ' ft. Logic Threshold (Vth) t:.;flt't9:tt ;(f_ V oo/2 o

2

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~;f..fi-Jtt~~~-/Fff-~k*~)?

9. - Clocked SR flip-flop it ~~o TIll !L. .PIT 7G ' -1t 4' Inverters pq ~it a8s

M.7t14JZ W/L ~ &!] tf .PITt~iG o Voo=5V' GND=OV 'PMOS it s8s1ltfi-J

Threshold Voltage Vtp=-0.7V ' NMOS it Is 1lt fi-J Threshold Voltage

Vtn=0.7V 0 NMOS it Is 1Jt ffJ f-LnCox = 60 ,uA/V2

' PMOS it s8s ·Jtll ffJ

f-l pcox = 20 ,uA I V 2 o tt r,, -t:-tl ~ flip-flop 1J5~{;; ~ M (switch state) , itt Is 1lt

Mn, ~ Mn2 PIT 1#; -1- fi-J J!l,J, Jt14 JZ -t(W/L),=(W/L)2 k} j' ?

10. - BiCMOS Logic itt~~oJ:..IIJ.E.PITiG 'Voo=5V' GND=OV 'PMOS

't Ia -H. fi-J Threshold Voltage V tp=-0.5V ' NMOS it s8s 1lt fi-J Threshold

Voltage Vtn=0.5V ' R1 =R2= lKD o tt M

(1)~ #:) A~3i.f!f-1t Mt, A 1.9 logic 1 (V oo)' li3i.f!f-1t ~t B 1.9 logic 0 (GND)

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v 1fl~t:t£J'3 ~ Av =; o

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1~:JY~+1t~JE1/J't£~~Adm =(Vo+-Vok+-V;-) o (:1f3ttit~ 31ft)

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15

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11 o ~ ~ tt 1!9 #-li. A .f_ +it.~ T ~ .::..1iL o

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Modulation ~X. ft.!~ Body Effect o t}ft)(. tl:l.J:l:. itiifr€8 #{~it /t:!tW ~(Common-Mode Voltage

Gain), Acm =(val +vo2)1(v;l +v;2), ~'fv;J =vi2 o

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+!OV

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V8EcoN) = 0.7v o ttJi:.tl:l RE(Q.) o

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.t:-~~.1!tfoli2t~ft.!(Channel Length Modulation Effect)~£.M.S<±fi.!(Body Effect) o M 2 .Z..

Wcs- ~) it/tjq 0.2V 0 t~#. tl:l :/&1l3..:t..ffi tl:l it& vo(min) HU!T1f Jt1Ht£~~t:'-~%~ 0

= = =

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:im$ ' UJ_3dB o JJ;Ji:$-'{trlq Radian/Sec.

14.;ff-:&A~ '~Open-LoopGain.:t..JJ;Ji:.:flJ¥ft.!lq:

3

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1 05 . 1 06 10 7

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15. -:ko T 't 4 ~£FIT 7G o ~ <f E8 .1! .1} ffi:. :f:... ~ ~ ft_ 1JJ ~A. f.H. .f!L (Differential Input

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~~ -=rct----wv---+- 1 ·" I lOOiill

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;/!L ' Rin (Q) o

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g 111 3 = 1 mAN • g"' 4 = 2 rnA IV o 1R~&.;1r Channel-Length Modulation ~{.J.11!,~ Body

Effect o ~w ~ tl:l 11:1:. it 4 ft-J ft_ 1h it £ .l:W .11 (Differential-Mode Voltage Gain) •

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18 . .j(a .r;, __!:_ i!t ~ ~ ;;6" PIT 7G o Jt t a9 MOSFET i!t .!'a 1l:lt ~ ~~ 1~ /!f: 4 ~ ;;fo r& (Saturation

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Channel-Length Modulation 5&.fi.11 ~ Body Effect o ~it n tl:l Jl:l:. i!t ~ SiJ i!t fM_ pt ~(Voltage

Gain) , A = v I v o V 0 I

5V

+2V +4V

- 5V

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Early Effect' VT = kT I q = 25mV o v81 = vd 12 ..!i v 82 = -vd 12 ' vd k-1!§l+ ~ft~

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~~=u0 /uio(5%)

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2. -!{o J:. ~ tJ Pff 7G .Z itt~ ' .:::. :f!id$. (Dl' D 2 ) .Z :if faJ iE::fo itt )f,t (15

) ~ 5 X 10-16 A.&.

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3. t.:> J.:J. T &iJ £..PIT 7G -Z tl il,t itt~ ' 1~H9:. i8 1@ .:::.;f.-3! :lit -Z ~ 1@. itt J!. ~ ~ 0. 7 V , JL r.f..J 1gJ.:::.

t!i 1lt ~ ii! ilt ~Ji~ OQ , _,j<_ ilt J!. Vo (V) o (5%)

l5V

4kn · ..

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3kD

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Milt s8a·JIUtH~:ii!AiEfo !&(saturation region)Hi- ' V1 ff.I{K~? (V) (5%)

5.. ~o it~~ fiT :iG o tt ..:::..;f..Jdlt(Diodes)~J£ ~ o 1; t = 0 a;t ' V0

= 0 V o ~ V, ff.; ilt 7fHo

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v,

BV- j_ ____ I II

* + +

~C( vo 2V

Time t=O l=l t = 2

6. ~o .~.-:;.Tit~~ iLf!T:iG ' MOSFET z V, = 1 V, f-lnCox = 100 ~A/V2 , L = 1 ~m,

W = 10 ~m o .t:-~i!i!tlll~~i.J,i!(Channel Length Modulation Effect)~ls.M;.:iii.h!(Body

Effect) o *{\ t±: V0

ff.; it~ o (5%)

5V lOkn

8k0 5k0

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Modulation Effect)~ls.~?tt~(Body Effect) o tit .;R t±: ill: ~JW.@. ~ = V0

IV, ff.; 1ft o (5%)

8. ~11 .~.-:;. T it lit ~ £ fiT :iG ' MOSFET z V, = 1 V , f-lnCox = 100 ~A /V2 ,

L1 =L2 =1~m, ~ =W2 =2~m o .t:-~i!i!tlll~~i.J,i!(Channel Length Modulation

Effect)~~~:ii±J.i!(Body Effect) o tit{\ t±: V0

ff.; it~ o (5%) - . ...

= 2

9. -J(u J..:l. J:_ 't 4@] .:5 fiT~ , $,- 'f i'f.J MOSFETs -1*11 :¥2-~;fu l& JL$,- + 1fl.lJit $-tHo T :

gm =lmAIV 'T0 = lOkQ 'gmb =0. lgm(BodyEffect) o1tJ\tl::'tJ!Vi$Ja.A,, =Vol~

!A -3dB -#i-f'. ' m_3dB o !t~$1J11.tr%.9 Radian/sec o (5%)

10. -JiuJ..:l.T'it4ml£.P!T~, MOSFETs ~~" =1 V, ~P =-l V, l?.n =2.5 /?.P o %-$.­

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5V

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(A) :l>g /Jo ~ 100 i!t a8a ')Jt i'f.J A iffd~ ;1,t

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3

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tij-Jfi Bode Plot ti-J:liii:-o"RJW. o (5%)

5