I. T. S. Heikkinena, P. Repob, V. Vähänissib, T. Pasanenb, V. Malinena, and H. Savinb

aBeneq Oy, Espoo, Finland

bDepartment of Electronics and Nanoengineering, Aalto University, Espoo, Finland

Efficient surface passivation of black silicon using spatial atomic layer deposition

Contact Ismo T. S. Heikkinen ismo.heikkinen@beneq.com Tel. +358 9 7599 530 www.beneq.com

Main Office Beneq Oy P.0. Box 4 FI-02201 Espoo Finland

In this study we show that spatial ALD (SALD) can provide at least as efficient surface passivation of planar and nanostructured silicon (black silicon, b-Si) as temporal ALD. Results indicate that conformal coating of high surface area structures such as b-Si is feasible with SALD. Passivation of both planar and b-Si substrates was achieved even with a line speed of 9 m/min, which demonstrates excellent process scalability and suitability for industrial-scale applications.

Introduction

• Using b-Si (Fig. 1a) has gained an increasing amount of interest in photovoltaics

due to its low reflectance on a wide spectral range and light-trapping properties.

• The large surface area of b-Si leads to a high surface recombination velocity and,

therefore, efficient surface passivation is required.

• Atomic Layer Deposition (ALD) of Al2O3 has already been used in efficient b-Si

surface passivation [1].

• ALD-passivated b-Si has been demonstrated in record-breaking PV devices

reaching efficiencies above 22 % [2], and in close to ideal photodiodes [3].

• SALD, illustrated in Fig. 1b, is a modification of ALD aimed to increase the

deposition rate of high-quality conformal coatings and to broaden the reach of

ALD [4].

• In these experiments we study the surface passivation of planar and

nanostructured Si using a prototype SALD reactor, Beneq SCS 1000.

Beneq SCS 1000 SALD prototype reactor [5]

• The reactor, presented in Figure 2a, consists of a vacuum chamber, substrate

carrier, and a precursor delivery system called the coating head.

• The coating head has 11 reconfigurable precursor zones, each 600 mm wide.

• The maximum effective coating area is at the moment 400 mm x 500 mm.

• Maximum substrate translation speed is 30 m/min.

• Example of coating on a large-area substrate is shown in Figure 2b.

• TMA and H2O were used as precursors at 150°C. Line speeds were 1.5, 4.5 and

9 m/min, and a deposition rate of 2.9 nm/min was reached.

• SALD concept has enormous, easily upscalable throughput potential.

Materials and Experiments

• Float Zone wafers (~1 Ωcm, 4 inch, 250 μm, p-type) were used as substrates. b-Si

surface was prepared on some of the wafers using cryogenic deep reactive ion

etching process i.e. ICP-RIE with parameters reported in [6]. Both sample types

were passivated with 20 nm of Al2O3.

• Charge carrier lifetime τ, total film charge Qtot and interface defect density Dit of

SALD-passivated samples were analyzed and compared to results obtained with

temporal ALD passivation.

• τ was characterized using photo conductance decay (PCD) method in the transient

mode (WTC-120 Sinton Instruments).

• Passivation layer Qtot and Dit were measured using contactless CV (COCOS) [7].

Acknowledgements

• The authors were supported by Finnish Funding Agency for Innovation under the

project “BLACK” (project No. 2956/31/2014), under the umbrella of SOLAR-

ERA.NET, by Finnish Funding Agency for Innovation. The provision of facilities by

Aalto University at OtaNano - Micronova Nanofabrication Centre is acknowledged.

SALD processing was conducted at the Beneq Oy facilities in Espoo, Finland.

SiliconPV 2017

Fig. 2. a) SALD prototype system SCS-1000, inset showing a 4’’ wafer adapter. b) Large-area deposition demonstration with ~70 nm of ZnO deposited onto 1540 x 670 mm stainless steel substrate.

a) b)

Fig. 1. a) SEM image of a typical freshly etched b-Si surface. b) The principle of Spatial ALD reactant delivery system in which precursors are isolated from each other by inert gas zones and exhaust lines. Adapted from [4].

a) b)

Excellent passivation with high line speeds

• The industrial feasibility of the SALD concept was inspected by passivating planar

and b-Si substrates with line speeds 1.5, 4.5 and 9 m/min.

• Samples were annealed in H2/N2 at 370°C, which yielded the highest τ for both

planar and b-Si substrates.

• For b-Si 1.5 m/min gave the best results, but for planar substrates 9 m/min

yielded the highest τ. With all conditions τ in the order of 1 ms was reached.

Comparison of SALD and temporal ALD

• τ, Qtot and Dit of SALD passivated samples (line speed 1.5 m/min for b-Si and 9

m/min for planar) were compared to temporal ALD passivated samples.

• Temporal ALD passivation was done with a Beneq TFS 500 using a TMA + H2O

process at 200°C. Annealing at 425°C in N2 was chosen for these samples [8].

• Similar τ for both sample types was obtained with SALD compared to temporal

ALD. Dit was also higher with SALD.

Conclusions

• SALD can provide efficient surface passivation on planar and nanostructured Si,

as shown by the high charge carrier lifetimes. Further tests are needed to verify

the exact passivation mechanisms.

• Conformal coating of high surface area structures such as nanostructured silicon

is possible with SALD.

• Efficient passivation of both planar and b-Si substrates was achieved with all

line speeds, which demonstrates excellent scalability and potential for industrial

processing.

• Further experiments with SALD include using ozone as oxidant, which has been

shown to reduce blistering compared to H2O [1] and plasma processing.

[1] Repo P et al. Energy Procedia 2016;92:381-385 [2] Savin H et al. Nat Nanotech 2015;10:624-629 [3] Juntunen MA et al. Nat Photon 2016;10:777-781 [4] Poodt P et al. J Vac Sci Technol. A 2012;30:010802 [5] Söderlund M et al. Large-area sheet-to-sheet spatial ALD system for high-throughput coating applications. Poster presentation, ALD2016, 2016 , Dublin, Ireland [6] Repo P et al. IEEE J Photovolt 2013;3:90-94. [7] Wilson M et al. COCOS (Corona Oxide Characterization Of Semiconductor) non-contact metrology for gate dielectrics. AIP Conference Proceedings 2001, 220-225. [8] von Gastrow G et al. Sol Energ Mat Sol Cells 2015;142:29-33

References

Fig. 3. a) Charge carrier lifetimes of planar and b-Si samples passivated with increasing line speed. b) Qtot and Dit as a function of line speed. Dit could be accurately determined only for planar samples [1].

Fig. 4. a) Charge carrier lifetimes of planar and b-Si samples passivated with temporal and spatial ALD. b) Qtot for both sample types and Dit for planar substrates passivated with temporal and spatial ALD.