efficient hardware dependant software (hds) generation using sw development platforms

Efficient Hardware dependant Software (HdS) Generation

using SW Development Platforms

Frédéric ROUSSEAU

CASTNESS‘07 Computer Architectures and Software Tools for

Numerical Embedded Scalable SystemsWorkshop & School

Roma January 15-17th 2007

2TIMA Laboratory - Frédéric ROUSSEAU -

CASTNESS’07Roma

January 17thSummary Context:

• Current multimedia applications require heterogeneous MPSoC DSP + µC + sophisticated communication infrastructure

• Multiple software (SW) stacks Multiple layers: Application SW code + HdS (Hardware dependent

Software) Specific architecture/application HdS to achieve efficiency

Problems: • Classic SW development platforms do not fit: High level

programming environment is not efficient to handle specific architecture capabilities

• HdS is Application/OS/architecture specific

Challenges:• Efficient HdS generation• Efficient and fast SW development platforms

Contribution:• Specific HdS generation for Diopsis • Specific SW development platforms for SW debug and validation


CASTNESS’07Roma

January 17thHdS generation

Hardware dependant Software (HdS) is composed of different layers• Operating System (OS)• Communication primitives• Hardware Abstraction Layer (HAL)• Application Programming Interface (API)

Why do we need HdS automatic generation ?• Application/OS/Platform specific HdS

Difficulties• Validation and debug (of each layer)• HdS is used as an abstraction of HW by the application code

Requires HW and SW knowledge

Task 1

HDS API

Comm OS

HAL API

HAL

Task 2

Task n

HdS

Tasks


CASTNESS’07Roma

January 17th

GAP

Classical HW/SW Interfaces Abstraction Models: The GAPS

Abstract CPU SS1

Abstract CPU SS2HW SS

Interconnect

T1

HDS API

T2

HDS API

T3

HDS API

Abstract CPU SS1


Interconnect

Abstract CPU SS1


Interconnect

T1

HDS APIHDS API

T2

HDS API

T3

HDS API

T2

HDS API

T3

HDS API

Hardware/Softwarediscontinuity

Virtual Prototype

Correction cycle

Functionalspecification

Partitionning

Software design

Hardware design

Integration ISA/RTL

High Level App. model

Early HW/SW integration

AbstractHW/SW Interface

Software development platform

T1 T2 T3T1 T2 T3

Fully implicitHW/SW Interface

CPU-SS1CPU1 ISS

PeriphInterface

Memory HW SS

CPU2ISS

PeriphInterface

Memory

CPU-SS2

Interconnect

T1

HDS API

Comm OS

HAL APIHAL

T2

HDS API

Comm OS

HAL API

T3

HAL

CPU-SS1CPU1 ISS

PeriphInterface

Memory HW SS

CPU2ISS

PeriphInterface

Memory

CPU-SS2

Interconnect

CPU-SS1CPU1 ISS

PeriphInterface

Memory HW SS

CPU2ISS

PeriphInterface

Memory

CPU-SS2

Interconnect

T1

HDS API

Comm OS

HAL APIHAL

T2

HDS API

Comm OS

HAL API

T3

HAL

T1

HDS API

Comm OS

HAL APIHAL

T1

HDS API

Comm OS

HAL APIHAL

T2

HDS API

Comm OS

HAL API

T3

HAL

T2

HDS API

Comm OS

HAL API

T3

HAL

Fully explicitHW/SW Interface


CASTNESS’07Roma

January 17th

SW Development Platforms & HdS

Virtual architecture

Transaction accurate architecture

High levelapplication model(tasks + mapping)

HdS

Library

Virtual prototype

HdS generation(TIMA)

Abstract CPU SS1


Interconnect

Abstract CPU SS1


Interconnect

T1

HDS API

T1

HDS API

T2 T3

HDS API

T2 T3

HDS API

CPU-SS2CPU-SS1Abstract

CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect


CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API

High level application model• System architecture(SA) model• Implicit communication

Virtual architecture (VA)• Final application code & HdS API• Explicit communication• Explicit mapping to execution

subsystems• Implicit execution models & task

control Transaction accurate architecture (TA)

• Explicit OS, specific I/O, HAL API• Explicit communication and peripherals• Abstract computation model of CPU

Virtual prototype• Explicit execution models (CPU,

communication)• HdS implements com. API & task

control over OS and architecture


CASTNESS’07Roma

January 17th

SW Development Platforms & HdS



HdS generation


HdS

Library

Virtual prototype

High level application model• System architecture(SA) model• Implicit communication

Virtual architecture (VA)• Final application code & HdS API• Explicit communication• Explicit mapping to execution

subsystems• Implicit execution models & task

control Transaction accurate architecture (TA)

• Explicit OS, specific I/O, HAL API• Explicit communication and peripherals• Abstract computation model of CPU

Virtual prototype• Explicit execution models (CPU,

communication)• HdS implements com. API & task

control over OS and architecture

D940 Diopsis tile

JTAGROM KB

Bridge

DXM Interface(AHB EBI)DXM Interface(AHB EBI)

SRAM KB

PDMA

DSP JTAG

DSPAHB

Master

4-addr/cycle

Multiple DSP AddrGen

10-float ops/cycle

16-port 256x40

Data Regs

DPM2-port

DDM6-access/

cycle

DSPAHB Slave

Slave

ICE

RISC

Instr Cache MMU Data CacheRDM IF BIUI D I D

Master

Multi-layerBus MATRIX

APBDNPAHB

Master

DNPAHB Slave

DNPAHB

Master

DNP

X+

DXM DXM

X-

Y+

Y-

Z+

Z-

C+

NoC(NI)

PERI PHERALS

Abstraction

T1

HDS API

T1

HDS API

T2 T3

HDS API

T2 T3

HDS API

SW developmentplatform generation

Abstract CPU SS1


Interconnect

Abstract CPU SS1


Interconnect


CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect


CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API


CASTNESS’07Roma

January 17th

Software design flow in SHAPES



HdS generation


HdS

Library


JTAGROM KB

Bridge


SRAM KB

PDMA

DSP JTAG

DSPAHB

Master

4-addr/cycle


10-float ops/cycle

16-port 256x40

Data Regs

DPM2-port

DDM6-access/

cycle

DSPAHB Slave

Slave

ICE

RISC


Master


APBDNPAHB

Master

DNPAHB Slave

DNPAHB

Master

DNP

X+

DXM DXM

X-

Y+

Y-

Z+

Z-

C+

NoC(NI)

PERI PHERALS

D940 Diopsis tile

AbstractionCPU-SS1CPU1 ISS

PeriphInterface

Memory HW SS

CPU2ISS

PeriphInterface

Memory

CPU-SS2

Interconnect

T1

HDS API

Comm OS

HAL APIHAL

T2

HDS API

Comm OS

HAL API

T3

HAL

CPU-SS1CPU1 ISS

PeriphInterface

Memory HW SS

CPU2ISS

PeriphInterface

Memory

CPU-SS2

Interconnect

CPU-SS1CPU1 ISS

PeriphInterface

Memory HW SS

CPU2ISS

PeriphInterface

Memory

CPU-SS2

Interconnect

T1

HDS API

Comm OS

HAL APIHAL

T2

HDS API

Comm OS

HAL API

T3

HAL

T1

HDS API

Comm OS

HAL APIHAL

T1

HDS API

Comm OS

HAL APIHAL

T2

HDS API

Comm OS

HAL API

T3

HAL

T2

HDS API

Comm OS

HAL API

T3

HAL

Virtual prototype (Aachen)

Application

Applicationmapping (ETH)

Architecture

Abstract CPU SS1


Interconnect

Abstract CPU SS1


Interconnect

T1

HDS API

T1

HDS API

T2 T3

HDS API

T2 T3

HDS API


CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect


CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API


CASTNESS’07Roma

January 17thDetailed contributions

Abstraction of the RDT Diopsis Tile• With the specific communication schemes• At different abstraction levels (Virtual and Transaction levels)

Software development Platforms generation• Debug and validation of the different SW stacks and layers• Different abstraction levels

HdS Generation• From a high level application model• Using the specific communication schemes of Diopsis


CASTNESS’07Roma

January 17thNext presentations




HdS

Library

Virtual prototype

D940 Diopsis tile

JTAGROM KB

Bridge


SRAM KB

PDMA

DSP JTAG

DSPAHB

Master

4-addr/cycle


10-float ops/cycle

16-port 256x40

Data Regs

DPM2-port

DDM6-access/

cycle

DSPAHB Slave

Slave

ICE

RISC


Master


APBDNPAHB

Master

DNPAHB Slave

DNPAHB

Master

DNP

X+

DXM DXM

X-

Y+

Y-

Z+

Z-

C+

NoC(NI)

PERI PHERALS

Abstraction


Abstract CPU SS1


Interconnect

Abstract CPU SS1


Interconnect


CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect


CPU1

PeriphInterface

Memory HW SS

Abstract CPU2

PeriphInterface

Memory

Interconnect

HdS generation

T1

HDS API

T1

HDS API

T2 T3

HDS API

T2 T3

HDS API

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API

T1 T2 T3

Comm OS

HAL API

HDS API

Comm OS

HAL API

HDS API

SW Development Platform generation• Efficient SW

Development Platform for Multimedia Applications by Katalin Popovici

HdS generation• Software Code

Generation from a Simulink Application Model by Xavier Guérin

Demo• Application of Software

Code Generation Flow from Simulink to Diopsis Platform by Katalin Popovici

efficient hardware dependant software (hds) generation using sw development platforms

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