effects of variation on emerging devices for use in sram
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Effects of Variation on Emerging Devices for Use in SRAM. Greg LaCaille and Lucas Calderin. SRAM Power Consumption. Minimum operating supply voltage ( Vmin ) determined by: Minimum acceptable Ion/ Ioff ratio Effects of performance variation on read and write margins - PowerPoint PPT PresentationTRANSCRIPT
Effects of Variation on Emerging Devices for Use in SRAMGreg LaCaille and Lucas Calderin
SRAM Power ConsumptionMinimum operating supply voltage (Vmin)
determined by:◦ Minimum acceptable Ion/Ioff ratio◦ Effects of performance variation on read and write
margins As CMOS is scaled down both these values
typically get worse. Reducing Vmin will lower power consumption SRAM assist techniques typically target
improving variation tolerance contribution. Device selection can affect the contribution from
leakage requirements.
Fully Depleted CMOSUTB-SOI or FinFETSimilar to Bulk CMOSGate control over
entire channel reduces sub-threshold swing
DIBL reduced relative to Bulk but still present
Carbon Nano-tube FETsBallistic transportSaturation determined
by contact resistance Intrinsic channel more
similar to BJT than MOSFET
Little-to-No DIBL
Tunneling FETsn-type
Band to Band tunneling current
Capable of sub-threshold swing < 60mV/dec
Low on current relative to MOS device of similar size
Little-to-No DIBL
SRAM LeakageFor a SRAM with
m rows
where A is the desired marginm=256; A=4There is a
minimum Vdd where this can be satisfied Device
Vmin (V) (leakage only)
FD CMOS 0.260CNFET 0.225TFET 0.070
Read/Write FailureScript written to
simulate DC sweeps while sweeping variation in each transistor
Automatic detection of read and write failures
Variation Limits
Each point represents a read or write failure X axis is the average Vth of all the devices in the point that failed Y axis is the rms sum of the difference in Vth for each device from
the average Vth for the point Area below the curve represents successful cells
Variation LimitsFor all devices the maximum allowable
variation increased with Vdd as expectedThe allowable deviation at the lowest Vth to
satisfy leakage requirements deviates among the devices substantially
ConclusionImproved Ion/Ioff for the TFET
doesn’t necessarily improve Vmin due to variation
CNFET is comparable to FD CMOSMinimum access time will also
play a key role in design of the SRAM
Any of these devices could be used with SRAM assist circuits to improve variability tolerance