effects of i/o routing through column interfaces in ... · gth, gty hd, hp gth, gty hd, hp gth, gty...

Effects of I/O Routing ThroughColumn Interfaces in Embedded

FPGA FabricsChristophe Huriaux ❖, Olivier Sentieys ❖, Russell Tessier ★

Inria, Rennes, FR ❖University of Massachusetts, Amherst, USA ★

26th International Conference on Field Programmable Logic and ApplicationsSeptember 1st, 2016

Overview

September 1st, 2016C. Huriaux, O. Sentieys, R. Tessier - 2

• Introduction• Motivational example: the FlexTiles platform

• Approach• Interface models

• Implementation methodology

• Experimental results• Placement and routing quality of results (QoR)

• Performance evaluation

• Conclusion

Introduction


• Field-Programmable Gate Arrays (FPGAs) are ubiquitous in the reconfigurable hardware market

• Many applications have high bandwidth requirements• Input and output (I/O) signals are usually handled

through simple I/O blocks or transceiver interfaces• I/Os arranged in an outer ring or in columns

Altera Cyclone III floorplan [Alt16]

UltraScale Architecture and Product Overview

DS890 (v2.8) June 3, 2016 www.xilinx.comPreliminary Product Specification 18

Device LayoutUltraScale devices are arranged in a column-and-grid layout. Columns of resources are combined in different ratios to provide the optimum capability for the device density, target market or application, and device cost. At the core of UltraScale+ MPSoCs is the processing system that displaces some of the full or partial columns of programmable logic resources. Figure 1 shows a device-level view with resources grouped together. For simplicity, certain resources such as the processing system, integrated blocks for PCIe, configuration logic, and System Monitor are not shown.

Resources within the device are divided into segmented clock regions. The height of a clock region is 60 CLBs. A bank of 52 I/Os, 24 DSP slices, 12 block RAMs, or 4 transceiver channels also matches the height of a clock region. The width of a clock region is essentially the same in all cases, regardless of device size or the mix of resources in the region, enabling repeatable timing results. Each segmented clock region contains vertical and horizontal clock routing that span its full height and width. These horizontal and

Table 16: Zynq UltraScale+ MPSoC: EV Device-Package Combinations and Maximum I/Os

Package(1)(2)(3)(4)

Package Dimensions

(mm)

ZU4EV ZU5EV ZU7EV

HD, HPGTH, GTY

HD, HPGTH, GTY

HD, HPGTH, GTY

SFVC784(5) 23x23 96, 1564, 0

96, 1564, 0

FBVB900 31x31 48, 15616, 0

48, 15616, 0

48, 15616, 0

FFVC1156 35x35 48, 31220, 0

FFVF1517 40x40 48, 41624, 0

Notes: 1. Go to Ordering Information for package designation details.2. FB/FF packages have 1.0mm ball pitch. SF packages have 0.8mm ball pitch.3. All device package combinations bond out 4 PS-GTR transceivers.4. GTH transceivers in the SFVC784 package support data rates up to 12.5Gb/s.

X-Ref Target - Figure 1

Figure 1: FPGA with Columnar ResourcesI/O

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I/O, C

lock

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Mem

ory

Inte

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CLB

, DS

P, B

lock

RA

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, DS

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iver

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DS890_01_101712Xilinx Ultrascale logic resourcesorganization [Xil16]

2.5D and 3D technologies


• 2.5D and 3D packaging technologies are increasinglyused in large circuits

• Higher yield (smaller ICs on an interposer)• Complex heterogeneous 3D-stacked systems with an FPGA layer, processor cores

• Communication between components in these FPGA-based systems often take place through dedicatedbus or Network-on-Chip (NoC) interfaces

Motivational example: FlexTiles platform


• FlexTiles architecture : 3D-stacked heterogeneous manycore[Lem12]• Manycore layer with General Purpose and Digital Signal Processors (GPP, DSP)• Hardware acceleratorsmapped on a reconfigurable FPGA layer• Network-on-Chip to interconnect the computingresources

Target applications


• Platform aimed at streaming applications• Kernels are partitioned to fit FPGA hardware modules and software GPP / DSP tasks

T1 T2

T4

T3

T5

GPP 1 DSP 1

FPGAMod. 1

FPGAMod. 2

DSP 2

Impact of dedicated interfaces


• Hardware tasks are logic modules placed on FPGA logic fabric

• Communications between e.g. processors and hard tasks take place through dedicated, coarse-grainedinterfaces

• What is the impact of such interfaces on the placement and routing QoR of FPGA modules ?

Model of the interfaces


• Generic interface model• Read and write FIFOs• Separate clock domains

• Variable data size• W input/output data bits

• Two FIFOs for bi-directional communications

RAM

read pointer

sync

sync

empty

full

data_in

data_out

read_enread_clk

write_clkwrite_en

read_rst

write_rst

write domain

read domain

Full and I/O-only models


• Two interface implementations• Full interface: only control and data signals exposed to the fabric• I/O-only interface: FIFO and control logic implemented withFPGA logic

Logic fabric

FIFO

F>S

FIFO

S>F

data_in

write_en

write_rst

full

data_out

read_en

read_rst

empty

data_out

read_en

read_rst

empty

data_in

write_en

write_rst

full

Interface + TSVs

TSV

Logic fabric

data_in

write_en

write_rst

full

data_out

read_en

read_rst

empty

data_out

read_en

read_rst

empty

data_in

write_en

write_rst

full

Interface + TSVs

TSV

Interface modeling in Quartus


• Architectural exploration using Verilog-To-Routing(VTR) [Luu14]

• Quartus yields more accurate performance results• Not feasible to define custom hardware blocks• Interfaces were modeled with dummy logic• Dummy logic resource count depends on the interface size

W = 32

Full-interface area

5,565 µm2

TSV area(for each interface signal)

76 x 196 µm2

…+Equivalent Stratix IV LAB area

(~ 5,088 µm2)x 4

20,461 µm2

Interface modeling in Quartus (2)


• Dummy LABs arrangedcontiguously in columns

• Interface columns reservedevery R columns in StratixIV

I/O pads I/O interface columns RAM columnDSP column

Experimental methodology


• Impact of migrating FPGA I/Os to interface blocks• Routability (minimum channel width)• Design delay

• Placement and routing QoR using VTR• Performance results using Quartus

Channel width(# of wires/routing channel)

Interface-based architecture exploration


• Evolution of an Altera Stratix IV architectural model• Clusters of 10 fracturable 6-LUTs• 32 Kb single or dual port memories• Fracturable 36x36 multipliers

• Custom interface hard block added to the architecture• Number of interface columns parameterized by a repeatparameter R• Variable interface data width W

• Exploration of varying R, W against a standard, outerI/O-ring Stratix IV architecture

Benchmark set


• 19 benchmarks from the VTR benchmark set• I/O count ranging from 40 to 779• Design size up to ~100k 6-LUTs• Heterogeneous logic resources including memories, multipliers

• Versatile Place-and-Route (VPR) used to place and route the designs on the smallest possible logic fabric

• Min. channel width on a standard architecture ranges from 34 wires to 170 wires• Critical path delay ranges from 2.77 ns to 115.5 ns

QoR : full interface


• Max ~10% variation of channel width, ~2% of delay• Larger channel widths with wide interfaces

• Congestion problems to route signals to/from the interfaces• Smaller interfaces min. channel width brought down by smallbenchmarks with high number of I/Os

RW

15 20 25 30

32 1.002 1.008 1.003 1.00064 1.002 0.991 0.987 0.997128 0.999 0.992 0.982 0.995

Average normalized crit. path delay(w.r.t. standard architecture)

RW

15 20 25 30

32 0.923 0.911 0.908 0.91164 0.954 0.939 0.940 0.940128 1.065 1.100 1.104 1.093

Average normalized channel width(w.r.t. standard architecture)

QoR : I/O-only interface


• Max ~3% variation of channel width, ~2% of delay• More routing stress in comparison to full interfaces

• Additional logic/memory resources induce overall higher wire-length for the router

RW

15 20 25 30

32 0.979 1.003 0.986 0.98364 1.019 1.005 1.025 1.021128 1.004 0.998 1.025 1.034Average normalized channel width

(w.r.t. standard architecture)

RW

15 20 25 30

32 1.019 1.011 0.995 0.99464 1.010 1.013 0.998 1.012128 1.014 1.024 1.010 1.010

Average normalized crit. path delay(w.r.t. standard architecture)

Additional resources with I/O-only interfaces


W Memories LABs

32 11.87 33.3364 12.80 25.67128 15.47 26.07

• Higher W leads to fewer interfaces• Fewer control logic required• More memory blocks required to cope with larger data width

Average amount of additional resourcesrequired for the IO-only architecture

Performance evaluation with Quartus


• 5 largest circuits used in Quartus with W = 64, R = 25• Max. ±10% variation on Fmax• Additional LABs required to handle the data to/from

the FIFOs

Circuit Std. arch.Fmax (MHz)

Full interface arch.Fmax (MHz)

bgm 81.17 76.48blob_merge 103.75 108.71

mcml 35.73 35.78stereovision1 136.93 130.36stereovision2 113.95 125.08

Performance comparison of the full-interfacearchitecture w.r.t. the standard architecture

Conclusion


• Traditional outer I/O ring has limited value for fabricembedded in 2.5D and 3D architectures

• Common FPGA architectures already move towards columnI/Os

• Two generic interface models studied• Both are implementable with little impact on the placement and routing QoR• Up to 10% min. channel width and 3% delay variations on average in comparison to a standard architecture

• More experiments to be performed• Comparison with commercial FPGA I/O count• TSV design constraints

Thank you foryour attention


References


[Alt16] https://www.altera.com/products/fpga/cyclone-series/cyclone-iii/features.html (July 2016)

[Lem12] F. Lemonnier, P. Millet, G. M. Almeida, M. Hubner, J. Becker, S. Pille- ment, O. Sentieys, M. Koedam, S. Sinha, K. Goossens, C. Piguet, M. N. Morgan, and R. Lemaire, “Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures,” in International Conference on Embedded Computers, 2012, pp. 228–235.

[Luu14] J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. B. Kent, J. Anderson, J. Rose, and V. Betz, “VTR 7.0: Next Generation Architecture and CAD System for FPGAs,” ACM Trans. Reconfigurable Technol. Syst., vol. 7, no. 2, pp. 6:1–6:30, June 2014.

[Xil16] Xilinx, DS890, UltraScale Architecture and Product Overview, v2.8

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