effect of device layout on the stability of rf mosfets

9
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 5, MAY 2013 1861 Effect of Device Layout on the Stability of RF MOSFETs Yongho Oh and Jae-Sung Rieh, Senior Member, IEEE Abstract—In this paper, the stability of RF MOSFETs is investi- gated in terms of the stability-factor ( -factor) for various layout schemes and device dimensions based on two different RFCMOS technologies. To systematically analyze the effect of small-signal device model parameters on RF MOSFET stability, the expression for -factor is derived as a function of the small-signal model pa- rameters of RF MOSFETs. Based on the expression, the effect of small-signal model parameters on the stability of RF MOSFETs is explored along with its bias dependence. In addition, the effect of wiring schemes, number of gate ngers, gate nger pitch, and gate length is examined based on various device structures. It is shown that the transconductance and capacitances are the dominant de- vice parameters to determine the stability of RF MOSFETs. The result also indicates that the stability of RF MOSFETs is strongly affected by the details of layout scheme and lateral dimension. Ad- ditionally, it was found that there is a tradeoff between device sta- bility and speed. This study is expected to serve a guideline for the device design and optimization for stable operation of RF MOS- FETs and circuits based on them. Index Terms—RF MOSFETs, small-signal model, stability. I. INTRODUCTION T HE rapid development of CMOS technology in the past decades has drastically enhanced the RF performance of MOSFETs, leading to devices now operating up to the range of a few hundred gigahertz [1], [2]. Such development has enabled the application based on CMOS technology up to the millimeter-wave band and even higher [3]. Typically, the device performance for circuit design is mostly determined by the technology provided to the designers. However, further performance enhancement is still available if device layout optimization is performed with the given process design kit. There have been a number of reports that investigated the effect of device dimension and layout scheme on and of MOSFETs [4]–[7]. Some studies focused on the optimization of unit nger width and number of ngers for higher [4], [5], while others discussed the impact of metal wiring schemes on and of MOSFETs [6], [7]. There have also been reports on the optimization of layout schemes to enhance the noise performance of MOSFETs [8]. Manuscript received November 29, 2012; revised February 25, 2013; ac- cepted February 26, 2013. Date of publication April 04, 2013; date of current version May 02, 2013. This work was supported by the National Research Foun- dation of Korea (NRF) funded by the Korea government (MEST) under Grant 2012R1A2A1A01005584. Y. Oh was with the School of Electrical Engineering, Korea University, Seoul, Korea. He is now with the System LSI Business, Samsung Electronics, Yongin City, Korea (e-mail: [email protected]). J.-S. Rieh is with the School of Electrical Engineering, Korea University, Seoul, Korea (e-mail: [email protected]). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TMTT.2013.2252918 However, another important aspect of RF performance, the device stability, has rarely been studied in a systematic manner for MOSFETs. The device stability limits the exibility in the design of most RF circuits, acting as a constraint for circuit optimization. It is not uncommon that fabricated ampliers, for example, end up getting unstable and oscillating, thus failing the system, which may have resulted from limited analysis on the device stability. Hence, the information on the stability of devices is critical, which is affected by the details in the layout scheme of the device as for other performance parameters. The limited number of papers reported for device stability in- clude studies on the stability of GaAs MESFET based on simple small-signal equivalent circuit [9] and on the stability of GaAs HBT [10] and SiGe HBTs [11]. There was a study on the sta- bility of MOSFETs [12], in which the impact of bias condi- tion and scaling on stability were investigated. However, it was based on rather relaxed 0.35- m CMOS technology, and only with a limited layout scheme and device parameters were in- volved. In this paper, a comprehensive study on the stability of RF MOSFET is performed based on three different layout schemes with two different CMOS technologies, in terms of var- ious small-signal model parameters, such as series resistances ( , , and ) and capacitances ( , , and ) that in- uence the stability factor ( -factor). The effect of device layout parameters, such as the number of gate ngers, gate pitch, and gate length, as well as wiring scheme on the stability of RF MOSFETs is discussed along with its bias dependence. II. STABILITY FACTOR OF MOSFETS It is well known that the criterion for unconditional stability for a linear two-port network is given in terms of -factor as follows [13]: (1) provided (2) To investigate the stability of MOSFETs, it is desired to ex- press the -factor in terms of small-signal model parameters of MOSFETs. Here, the condition for a two-port network and the expression of -factor for MOSFETs are derived based on a sim- plied small-signal equivalent circuit as shown in Fig. 1. The equivalent circuit includes the series resistances, such as , , and , and a core, which is composed of capacitances , , and as well as output conductance and a de- pendent current source. The bulk is assumed to be connected to grounded source, and, thus, the bulk capacitances are not shown 0018-9480/$31.00 © 2013 IEEE

Upload: jae-sung

Post on 10-Dec-2016

215 views

Category:

Documents


2 download

TRANSCRIPT

Page 1: Effect of Device Layout on the Stability of RF MOSFETs

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 5, MAY 2013 1861

Effect of Device Layout on the Stabilityof RF MOSFETs

Yongho Oh and Jae-Sung Rieh, Senior Member, IEEE

Abstract—In this paper, the stability of RF MOSFETs is investi-gated in terms of the stability-factor ( -factor) for various layoutschemes and device dimensions based on two different RFCMOStechnologies. To systematically analyze the effect of small-signaldevice model parameters on RFMOSFET stability, the expressionfor -factor is derived as a function of the small-signal model pa-rameters of RF MOSFETs. Based on the expression, the effect ofsmall-signal model parameters on the stability of RF MOSFETs isexplored along with its bias dependence. In addition, the effect ofwiring schemes, number of gate fingers, gate finger pitch, and gatelength is examined based on various device structures. It is shownthat the transconductance and capacitances are the dominant de-vice parameters to determine the stability of RF MOSFETs. Theresult also indicates that the stability of RF MOSFETs is stronglyaffected by the details of layout scheme and lateral dimension. Ad-ditionally, it was found that there is a tradeoff between device sta-bility and speed. This study is expected to serve a guideline for thedevice design and optimization for stable operation of RF MOS-FETs and circuits based on them.

Index Terms—RF MOSFETs, small-signal model, stability.

I. INTRODUCTION

T HE rapid development of CMOS technology in the pastdecades has drastically enhanced the RF performance of

MOSFETs, leading to devices now operating up to the rangeof a few hundred gigahertz [1], [2]. Such development hasenabled the application based on CMOS technology up tothe millimeter-wave band and even higher [3]. Typically, thedevice performance for circuit design is mostly determined bythe technology provided to the designers. However, furtherperformance enhancement is still available if device layoutoptimization is performed with the given process design kit.There have been a number of reports that investigated the effectof device dimension and layout scheme on and ofMOSFETs [4]–[7]. Some studies focused on the optimizationof unit finger width and number of fingers forhigher [4], [5], while others discussed the impact ofmetal wiring schemes on and of MOSFETs [6], [7].There have also been reports on the optimization of layoutschemes to enhance the noise performance of MOSFETs [8].

Manuscript received November 29, 2012; revised February 25, 2013; ac-cepted February 26, 2013. Date of publication April 04, 2013; date of currentversionMay 02, 2013. This work was supported by the National Research Foun-dation of Korea (NRF) funded by the Korea government (MEST) under Grant2012R1A2A1A01005584.Y. Oh was with the School of Electrical Engineering, Korea University,

Seoul, Korea. He is now with the System LSI Business, Samsung Electronics,Yongin City, Korea (e-mail: [email protected]).J.-S. Rieh is with the School of Electrical Engineering, Korea University,

Seoul, Korea (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TMTT.2013.2252918

However, another important aspect of RF performance, thedevice stability, has rarely been studied in a systematic mannerfor MOSFETs. The device stability limits the flexibility in thedesign of most RF circuits, acting as a constraint for circuitoptimization. It is not uncommon that fabricated amplifiers, forexample, end up getting unstable and oscillating, thus failingthe system, which may have resulted from limited analysis onthe device stability. Hence, the information on the stability ofdevices is critical, which is affected by the details in the layoutscheme of the device as for other performance parameters.The limited number of papers reported for device stability in-

clude studies on the stability of GaAsMESFET based on simplesmall-signal equivalent circuit [9] and on the stability of GaAsHBT [10] and SiGe HBTs [11]. There was a study on the sta-bility of MOSFETs [12], in which the impact of bias condi-tion and scaling on stability were investigated. However, it wasbased on rather relaxed 0.35- m CMOS technology, and onlywith a limited layout scheme and device parameters were in-volved. In this paper, a comprehensive study on the stabilityof RF MOSFET is performed based on three different layoutschemeswith two different CMOS technologies, in terms of var-ious small-signal model parameters, such as series resistances( , , and ) and capacitances ( , , and ) that in-fluence the stability factor ( -factor). The effect of device layoutparameters, such as the number of gate fingers, gate pitch, andgate length, as well as wiring scheme on the stability of RFMOSFETs is discussed along with its bias dependence.

II. STABILITY FACTOR OF MOSFETS

It is well known that the criterion for unconditional stabilityfor a linear two-port network is given in terms of -factor asfollows [13]:

(1)

provided

(2)

To investigate the stability of MOSFETs, it is desired to ex-press the -factor in terms of small-signal model parameters ofMOSFETs. Here, the condition for a two-port network and theexpression of -factor forMOSFETs are derived based on a sim-plified small-signal equivalent circuit as shown in Fig. 1.The equivalent circuit includes the series resistances, such as, , and , and a core, which is composed of capacitances, , and as well as output conductance and a de-

pendent current source. The bulk is assumed to be connected togrounded source, and, thus, the bulk capacitances are not shown

0018-9480/$31.00 © 2013 IEEE

Page 2: Effect of Device Layout on the Stability of RF MOSFETs

1862 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 5, MAY 2013

Fig. 1. Simplified small-signal equivalent circuit of MOSFET employed in thiswork.

separately. For the sake of analysis, the equivalent circuit is di-vided into the intrinsic part, as indicated in Fig. 1 with the grayline, and the remaining extrinsic part. The intrinsic part can becharacterized by the admittance matrix , which relates theintrinsic voltages , and and as follows:

(3)

It can be easily shown that is expressed in terms of small-signal model parameters as

(4)

where and . Then, thesmall-signal voltages of the entire network, and , can berelated to and by the following matrix expression:

(5)

where is the impedance matrix of the entire circuit. Afterrearrangement, can be given as follows:

(6)

where is the determinant of that can be expressed as

(7)

Assuming, which is valid up to a few tens of gigahertz with the actual

values estimated for MOSFETs used in this study, can beapproximated as

(8)

where . At 40 GHz, the error due tothis approximation is less than 5% for the devices studied in thiswork.With the -parameters derived in (6), we can easily show

that the condition given (2) is always satisfied for a MOSFETbecause and are always positive as they areexpressed as follows:

(9)

(10)

This provided, the criterion given in (1) in terms of -factorremains as the only condition we need to concern in the analysis.Hence, the stability of MOSFETs in this study will be discussedin terms of -factor only.

-factor of MOSFETs can be expressed in terms of small-signal model parameters when the -parameters are given as (6)by (11), shown at the bottom of the page. From (11), it can beseen that the -factor ofMOSFETs increases with increasing se-ries resistances, indicating that MOSFETs become more stablewith large series resistances as expected. It can be also noted thatthe -factor of MOSFETs is dependent on bias condition, sinceand as well as the capacitances are affected by the bias

condition. -factor in (11) can be further approximated and re-arranged as given by (12), shown at the bottom of the followingpage, where following assumptions are made:

(13)

For the devices investigated in this work, approximated -factorobtained from (11) was within 10% error from the -factorbased on (12) when calculated at 40 GHz. As -factor is adimensionless parameter, it can be shown as a product offrequency and a time constant as follows:

(14)

(11)

Page 3: Effect of Device Layout on the Stability of RF MOSFETs

OH AND RIEH: EFFECT OF DEVICE LAYOUT ON THE STABILITY OF RF MOSFETS 1863

where is divided into two time constants and , whichare given as follows:

(15)

(16)

For , the intrinsic voltage gain is much larger thanthe capacitance ratio , resulting in the first factor in (15)being close to unity. This indicates that mostly representsthe time constant arising from the series resistances , ,and . On the other hand, represents an intrinsic time con-stant as it is driven by the inverse of and the capacitances.The expression of -factor obtained above is more comprehen-sive than the one introduced in [12], as it additionally includes, , and .In the following sections, the effect of small-signal model

parameters on the stability of RF MOSFETs is studied in termsof -factor and .

III. DEVICE STRUCTURE AND MEASUREMENT

To investigate the stability of RFMOSFETs, test devices withvarious wiring schemes and layout details were designed andfabricated based on two different technology nodes. Fig. 2 de-scribes the simplified schematics of MOSFETs designated asGM2, GPO, and GM1. GM2 (Gate wiring on M2) and GPO(Gate wiring on POly) were fabricated based on Dongbu HiTek

m RFCMOS technology. The gate length and unitgate width are fixed as 0.13 and 2.5 m, respectively. ForGM2, poly gate fingers are connected with a rectangular-shapedloop on M2 metal level, while for GPO gate fingers are con-nected on poly level as the names indicate. The details other thanthe gate metal wiring scheme are identical for the two schemes,as detailed in [14]. In order to explore the effect of lateral di-mension on the stability of RFMOSFETs, various were em-ployed for the two schemes. GPO additionally includes the vari-ation in the gate finger pitch . GM1 (Gate wiring on M1)was fabricated in IBM 90-nm RFCMOS technology, which islargely similar to GM2 except for the details of metal level forwiring, most importantly the gate wiring made on M1 insteadof M2 level. Source contacts are connected on M4 level and thedrain contacts are connected on M2 level. is fixed at 1.5 mand various of 0.10, 0.13, and 0.18 m are included to studythe effect of scaling on stability.All of the fabricated test devices were characterized with-parameters measurement with a network analyzer, for whicha two-step de-embedding based on “open” and “short” was

carried out. -factor of the devices was calculated as a functionof frequency based on (1) with the -parameters convertedfrom the measured -parameters. Additionally, small-signalmodel parameters, including series resistances and capacitancesas well as and , were extracted from the converted -and -parameters [15], [16] in order to study the dependenceof -factor on the device parameters.

IV. EFFECT OF DEVICE PARAMETERS AND BIAS ON STABILITY

Here, the effect of small-signal model parameters on -factoris investigated in order to identify the dominant device param-eters that affect the device stability. The bias dependence of thestability is also discussed. A test device based on GM2 schemewith is used throughout the analysis here as a typicalexample.

A. Effect of Device Parameters on Stability

Fig. 3 shows the measured -factor as a function of attwo different frequencies of 20 and 40 GHz. As shown in theplot, -factor does not show a strong dependence on , whileit tends to increase with at a higher current regime. Theobserved frequency dependence is consistent with (14), whichpredicts a linear relation. As a first step to investigate the ef-fect of device parameters, is divided into and andplotted as a function of the bias current as shown in Fig. 4(a). Itis noted that the time constants shown in Fig. 4 are based on thesmall-signalmodel parameters extracted from themeasurement,and the trend may slightly differ from -factor directly calcu-lated from the -parameters, as shown in Fig. 3. However, suchdiscrepancy, which was estimated to be , will not affectthe analysis significantly as the relative effect of each parameterwill be retained. From Fig. 4(a), it is clear that is dominatedby , which is an indication that the stability is determinedmostly by the intrinsic component for the given device. As theentire factor of is multiplied by , it becomes obviousthat is a critical parameter that determines the level of thedevice stability. To further detail the capacitance dependence,

is subdivided into two time constant components andas follows:

(17)

(18)

Fig. 4(b) compares the relative contribution from each timeconstant, which reveals that makes up a larger portion than

in for the entire range of measured . This can be ex-plained from Fig. 5, which presents the values of extracted pa-rameters that affect the time constants. According to the plots,

is larger than other capacitances while is about

(12)

Page 4: Effect of Device Layout on the Stability of RF MOSFETs

1864 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 5, MAY 2013

Fig. 2. Three different wiring schemes employed in this study. (a) GM2. (b) GPO. (c) GM1. Note that GM2 and GPO structures are based on Dongbu Hitek0.13- m process, and the GM1 structure is based on the IBM 90-nm process.

0.4 for the entire range of . This makesmuch larger than and thus becomes largerthan . A closer look into the plot reveals that grad-ually decreases with increasing , which is due to in-creasing with . However, it does not significantly affect theoverall trend of and thatremain roughly insensitive to variation. Fig. 5(c) shows thetrend of , which is similar to that of , another indicationthat and thus are strongly affected by .While it turnedout that is not a driving factor for the stability for the givendevice, a couple of related observations can be mentioned.

shows a gradual increase with increasing , which is mainlybecause the intrinsic voltage gain gradually decreaseswith increasing . It is also noted that is much larger thanand , leading to term dominating .

B. Effect of on Stability

Up to this point, bias dependence has been described in termsof only , which was controlled by . To further investigatethe behavior of -factor, its dependence is now discussed.Fig. 6 shows the measured -factor for three different values of

Page 5: Effect of Device Layout on the Stability of RF MOSFETs

OH AND RIEH: EFFECT OF DEVICE LAYOUT ON THE STABILITY OF RF MOSFETS 1865

Fig. 3. Measured -factor of GM2 as a function of for two given frequen-cies with 1.0 V.

Fig. 4. (a) Extracted , and of GM2. (b) Extracted , andof GM2 as a function of JD with 1.0 V.

as a function of at a fixed frequency of 20 GHz. As pre-sented in the plot, -factor shows a similar trend for 1.0and 1.5 V, but it sharply increases for 0.5 V, especiallyat large drain current level. The observed larger -factor forsmall can be explained by the fact that the device entersthe linear region when is reduced, more rapidly when thecurrent level is high. Once in the linear region, becomesvery large leading to a drastic increase in , which results inan increase in -factor. Additional effects include the increasesin capacitances and reduction in , which also helps the in-crease in -factor and stability with reduced . However, theoperation of MOSFETs in the linear region is rarely practicedand the increased stability with smaller does not bear a sig-nificance from a practical point of view. Fig. 7 shows -factoras a function of frequency for the three points at fixed .It exhibits a linear relation with frequency as is expected from(14), supporting the validity of approximations made for (14).

Fig. 5. (a) Extracted , and . (b) Extracted ,and as a function of . (c) Extracted as a function

of , is 1.0 V.

The analysis in this section indicates that, for the given devicein the practical region of operation, is the dominant deviceparameters affecting device stability, while the capacitancesin particular also modulate the stability.

V. EFFECT OF DEVICE LAYOUT ON STABILITY

Here, the effect of device layout on the stability of MOSFETis described. First, the effect of the wiring scheme is presentedby comparing devices based on GM2 and GPO structures.Next, the effect of gate finger layout is discussed in terms ofthe number of gate fingers , gate finger pitch , andgate length .

A. Effect of Wiring Scheme on Stability

To study the effect of gate metal wiring scheme on the sta-bility, -factor is compared for the devices based on GM2 andGPO structures. In Fig. 8, -factors of each device, both withten gate fingers, are shown as a function of frequency for twodifferent levels at a fixed of 1.0 V. As shown in theplot, -factor for GPO is larger than that for GM2 for the entirerange of the measured frequency range. To examine the cause ofthe difference, and its components and are comparedfor GM2 and GPO in Fig. 9(a). As is obvious in the plot,of GPO is significantly larger than that of GM2, explaining thelarger and thus -factor for GPO. There is little difference in

Page 6: Effect of Device Layout on the Stability of RF MOSFETs

1866 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 5, MAY 2013

Fig. 6. (a) Measured -factor of GM2 as a function of at a given frequencyof 20 GHz with various . (b) Extracted , as a function of withvarious .

Fig. 7. Measured -factor of GM2 as a function of frequency with variousfor a given of 280 A m.

for the two structures. It turns out that the large is dueto the significantly larger for GPO as shown in Fig. 9(b),which arises from the fact that the gate fingers are connected onthe poly level for GPO, which is much more resistive than M2level used for gate connection for GM2. Other device model pa-rameters did not show significant difference between GM2 andGPO structures. The result implies that the larger for GPOmakes the device more stable than GM2, but apparently at thecost of device operation speed. The -parameter measurementof the devices shows that of GPO is around 65 GHz, sig-nificantly lower than that of GM2 that was around 100 GHz.

Fig. 8. Measured -factor for GPO and GM2 as a function of frequency fortwo different levels of 280 and 490 A m with 1.0 V.

Fig. 9. (a) Extracted , , and for both schemes as a function ofand (b) extracted for the two schemes as a function of . is 1.0 V.

This indicates that there is a tradeoff between device stabilityand speed in device design and optimization. It is noted thatfor GM2, 65 GHz, is slightly lower than 75 GHz for GPOmainly due to larger parasitic capacitances [14].

B. Effect of Number of Gate Fingers on Stability

The number of gate fingers affects the power driving capa-bility of the devices, but it may affect the stability as well. Toexplore the effect of on device stability, the -factor is com-pared and presented in Fig. 10 with different numbers of gatefingers ( 5, 10, and 20) for both GM2 and GPO. Unitfinger width is fixed at 2.5 m. It is interesting to observethat -factor for GPO increases with increasing while an op-posite trend was exhibited by GM2. The observed differentdependence of stability for the two structures can be explained

Page 7: Effect of Device Layout on the Stability of RF MOSFETs

OH AND RIEH: EFFECT OF DEVICE LAYOUT ON THE STABILITY OF RF MOSFETS 1867

Fig. 10. Measured -factor for GPO and GM2 as a function of frequency withvarious for a given of 280 A m with 1.0 V.

Fig. 11. (a) Extracted , , and for both GM2 and GPO as a functionof . (b) Extracted and for both structures. (c) Extractedfor both structures. is 280 A m with a fixed 1.0 V.

by the trend of the time constants and key device model param-eters over variation, as presented in Fig. 11. As shown inFig. 11(a), is mostly insensitive to variation for bothstructures. However, a pronounced and opposite trend is ob-served in for GPO and GM2: it increases with for GPObut decreases for GM2. This results in overall increasing (de-creasing) trend of and thus -factor for GPO (GM2).

Fig. 12. Measured -factor as a function of frequency for various with agiven of 280 A m. is 1.0 V.

The difference in the trend for the two structures is nowdiscussed. The dominant term in is the productsince and are much larger than other resistance and ca-pacitance components, respectively. Hence, the trend ofdominates the trend of . It is noted that the term

, which is a common factor for as shown in (16), israther insensitive to variation in this work. Fig. 11(b) showsthe trend of and over . For both GM2 and GPO,

has a monotonic increase with while decreases withincreasing . However, the rate of decrease in with in-creasing is more rapid for GM2, since the total of GM2is mostly determined by the parallel combination of from in-dividual gate fingers. On the other hand, the total of GPO isadditionally affected by the series resistance between gate fin-gers due to the relatively high resistivity of the poly layer thatconnects the gate fingers. Hence, reduction for GM2 dom-inates over the increase for larger while increasedominates over for GPO. Thus, it results in differentdependence of the as shown Fig. 11(c), leading to op-posite dependence of stability for the two structures. It isinteresting to note that increases with increasing forGM2, while an opposite trend is observed for GPO. Again atradeoff between stability and speed is observed.

C. Effect of Gate Pitch on Stability

The pitch between gate fingers, or the gate pitch , wasvaried for GPO structure from 0.78 m to 1.18 m. The de-pendence of -factor on is shown as a function of frequencyin Fig. 12. As observed in the plot, larger leads to larger-factor for the entire measured frequency range. Such de-pendence of -factor can be explained by the increasing trend oftime constants shown in Fig. 13(a), which is determined by thetrend of series resistances and capacitances. As increases,resistance along gate metal wiring increases, which leads toincreasing as presented in Fig. 13(b). In addition, andalso slightly increase with as the current path along the

source/drain metal wiring and diffusion region increase [14]. Inaddition to series resistances, capacitances also increase withas shown in Fig. 13(b), since the vertical capacitance componentincreases as the lateral dimension of the wiring is expanded. Al-though lateral capacitance component may partly increase withthe increased pitch, the effect is apparently not dominating. The

Page 8: Effect of Device Layout on the Stability of RF MOSFETs

1868 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 5, MAY 2013

Fig. 13. (a) Extracted , , and as a function of . (b) Extractedand capacitances as a function of . is 280 A m with 1.0 V.

Fig. 14. Measured -factor of GM1 as a function of frequency for variousfor two different levels of 200 and 480 A m with 1.0 V.

increase in resistance and capacitance with increasing resultsin larger time constants, leading to stability improvement. It isnoted that the increase in with increasing will be less pro-nounced for GM1 or GM2 structures as the sheet resistance ofmetal layers are significantly smaller than that of a poly layer.Extracted shows degradation with increased a result ofincreased resistance and capacitance.

D. Effect of Gate Length on Stability

GM1 is based on amore scaled technology than used for GM2and GPO, and devices with various were implemented tostudy the impact of scaling on the stability. The measured-factor of GM1 with various are compared in Fig. 14 as afunction of frequency with two different levels. As shown

Fig. 15. Extracted and for various as a function of for a givenof 1.0 V.

Fig. 16. (a) Extracted capacitances for various as a function of .(b) Extracted and for various as a function of . is 1.0 V.

in the plot, there is a clear trend of increasing -factor with in-creasing , an indication of a better stability with larger .As a routine step in this study to search for the dominant fac-tors, the time constants are plotted as a function of for thedifferent gate lengths in Fig. 15. As can be found in the plot,

variation with is responsible for the observed trend of-factor. Although shows an opposite trend, it is dominatedby the wide variation of . The extracted device parametersfor various , including capacitance as well as and areshown as a function of in Fig. 16. As shown in Fig. 16(a),capacitances increase with increasing since the gate area,given by , increases with . Especially, the variation of

with is larger than those of other capacitances as ismore sensitive to the gate area variation. Additionally, alsoincreases with as shown in Fig. 16(b) as is expected fromthe well-known dependence of , adding to the increasingtrend of with . Fig. 16(b) shows that decreases with

Page 9: Effect of Device Layout on the Stability of RF MOSFETs

OH AND RIEH: EFFECT OF DEVICE LAYOUT ON THE STABILITY OF RF MOSFETS 1869

TABLE IEFFECT OF LAYOUT VARIATIONS

since is inversely proportional to , explaining the de-creasing trend of with . It can be commented that themea-sured and improve over scaling as expected, againreinforcing the trade-off between stability and speed.

VI. CONCLUSION

In this paper, a comprehensive study on the stability of RFMOSFETs has been carried out in terms of -factor obtainedfrom various devices. The effect of small-signal device modelparameters and bias on the stability was explored, and the ef-fect of various layout options such as external wiring schemes,number of gate finger, gate finger pitch, and gate length was dis-cussed with measured data. The overall results indicate that thetransconductance and capacitances, in particular , are themost dominating device model parameters that determine thestability of RF MOSFETs while other capacitances and seriesresistances also affect the stability. Also, various layout optionsresulted in different stability levels of RF MOSFETs, and it wasnotable that the options improving the stability tend to degradethe device operation speed. The effects of the layout variationson the stability and device speed explored in this work are sum-marized in Table I. The observation made in this work is ex-pected to serve as a useful and practical guideline for the designand optimization of RF MOSFETs aiming at high performanceyet stable operation of the devices.

ACKNOWLEDGMENT

The authors would like to thank Dongbu Hitek and IBM fortheir kind fabrication support of the devices used in this work.

REFERENCES

[1] S. Lee, B. Jaganathan, S. Narasimha, A. Chou, N. Zamdmer, J.Johnson, R. Williams, L. Wagner, J. Kim, O. Plouchart, J. Pekarik, S.Springer, and G. Freeman, “Record RF performance of 45-nm SOICMOS technology,” in Proc. IEEE Int. Electron Device Meet., 2007,pp. 255–258.

[2] C. H. Jan, M. Agostinelli, H. Deshpande, M. A. El-Tanani, W. U. J.Hafez, L. Janbay, M. Kang, H. Lakdawala, J. Lin, Y.-L. Lu, S. Mun-danai, J. Park, A. Rahman, J. Rizk, W. K. Shin, K. Soumyanath, H.Tashiro, C. Tsai, P. VanDerVoorn, J.-Y. Yeh, and P. Bai, “RF CMOStechnology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications,” in Proc. IEEE Int. Electron Device Meet., 2010,pp. 27.2.1–27.2.4.

[3] O.Momeni and E. Afshari, “High power terahertz andmillimeter-waveoscillator design: a systematic approach,” IEEE J. Solid-State Circuits,vol. 46, no. 3, pp. 583–597, Mar. 2011.

[4] T. Tatsumi, “Geometry optimization of sub-100 nm node RF CMOSutilizing three dimensional TCAD simulation,” in Proc. 36th Eur.Solid-State Device Res. Conf., 2006, pp. 319–322.

[5] A. F. Tong, W. M. Lim, C. B. Sia, K. S. Yoo, Z. L. Teng, and P. F. Ng,“RFCMOS unit width optimization technique,” IEEE Trans. Microw.Theory Tech., vol. 55, no. 9, pp. 1844–1852, Sep. 2007.

[6] H.-S. Jhon, J.-H. Lee, J. Lee, B. Oh, I. Song, Y. Yun, B. -G. Park, J.-D.Lee, and H. Shin, “ improvement by controlling extrinsic parasiticin circuit-level MOS transistor,” IEEE Electron Device Lett., vol. 30,no. 12, pp. 1323–1325, Dec. 2009.

[7] C.-Y. Chan, S.-C. Chen, M.-H. Tsai, and S. S. H. Hsu, “Wiring effectoptimization in 65-nm low-power nmos,” IEEE Electron Device Lett.,vol. 29, no. 11, pp. 1245–1248, Nov. 2008.

[8] W. Wu, S. Lam, and M. Chan, “Effect of layout methods of RF CMOSon noise performance,” IEEE Trans. Electron Devices, vol. 52, no. 12,pp. 2753–2759, Dec. 2005.

[9] G. D. Vendelin andM.Omori, “Circuit model for the gaasM.E.S.F.E.T.valid to 12 GHz,” Electron. Lett., vol. 11, no. 3, pp. 60–61, Feb. 1975.

[10] S. Tanaka, Y. Amamiya, S. Murakami, H. Shimawaki, N. Goto, Y.Takayama, and K. Honjo, “Design considerations for millimeter-wavepower HBT’s based on gain performance analysis,” IEEE Trans. Elec-tron Devices, vol. 45, no. 1, pp. 36–44, Jan. 1998.

[11] Z. Ma and N. Jiang, “On the operation configuration of SiGe HBTsbased on power gain analysis,” IEEE Trans. Electron Devices, vol. 52,no. 2, pp. 248–255, Feb. 2005.

[12] J. -G. Su, S. -C. Wong, and C. Y. Chang, “An investigation on RFCMOS stability related to bias and scaling,” Solid-State Electron., vol.46, no. 4, pp. 451–458, Apr. 2002.

[13] J. M. Rollett, “Stability and Power-Gain Invariants of LinearTwoports,” IRE Circuit Theory, vol. 9, no. 1, pp. 29–32, Mar. 1962.

[14] Y. Oh and J.-S. Rieh, “The effect of device layout schemes on RFperformance of multi-finger MOSFETs,” IEICE Trans. Electron., vol.E95-C, no. 5, pp. 785–791, May 2012.

[15] W. Choi, G. Jung, J. Kim, and Y. Kwon, “Scalable small-signal mod-eling of RF CMOS FET based on 3-D em-based extraction of para-sitic effects and its application to millimeter-wave amplifier design,”IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3345–3352,Dec. 2009.

[16] I. Kwon, M. Je, K. Lee, and H. Shin, “A simple and analytical param-eter-extraction method of a microwave MOSFET,” IEEE Trans. Mi-crow. Theory Tech., vol. 50, no. 6, pp. 1503–1509, Jun. 2002.

Yongho Oh received the B.S. and M.S degreesin electrical engineering from Hongik University,Seoul, Korea, in 2004 and 2006, respectively, andthe Ph.D. degree in electrical engineering fromKorea University, Seoul, Korea, in 2013.From 2006 to 2007, he was with Dongbu HiTek

Semiconductor Business, where he worked onadvanced CMOS process integration and deviceengineering. Since 2013, he has been with SystemLSI Business, Samsung Electronics, where heworks on device characterization and modeling for

RF/mm-wave applications.

Jae-Sung Rieh (S’89–M’91–SM’05) received theB.S. and M.S. degrees in electronics engineeringfrom Seoul National University, Seoul, Korea, in1991 and 1995, respectively, and the Ph.D. degreein electrical engineering from the University ofMichigan, Ann Arbor, MI, USA, in 1999.In 1999, he joined the IBM Semiconductor R&D

Center, where he was responsible for the research anddevelopment activities for 200-GHz and 350-GHzSiGe HBT technologies. Since 2004, he has beenwith the School of Electrical Engineering, Korea

University, Seoul, Korea, where he is currently a Professor. His major interestlies in the Si-based RF devices and their application to millimeter-wave andterahertz circuits.Dr. Rieh was a recipient of the 2004 IBM Faculty Award and a corecipient

of the 2002 and 2006 IEEE Electron Device Society George E. Smith Award.He has served as an associate editor of the IEEE MICROWAVE AND WIRELESSCOMPONENTS LETTERS and is currently serving as an associate editor of theIEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.