ees11 - power management

7/27/2019 EES11 - Power Management

1/40

Embedded Electronic Systems

draNolte,

GesineMarwedel,2003

Graphics:

Alexan

Power Issues

Battery Management

Processing units

Need for efficiency (power + energy):

Wh worr about

Power is considered as the most important constraint in

embedded systems[in: L. Eggermont (ed): Embedded Systems Roadmap 2002, STW]

energy and power?

Energy consumption by IT is the key concern of

green computing initiatives

(embedded computing leading the way)http://www.esa.int/images/earth,4.jpg


2/40

Low Power vs. Low Energy Consumption

Minimizing the power consumption is important for

the design of the power supply

the design of voltage regulators

the dimensioning of interconnect

short term cooling

Minimizing the energy consumption is important due to

restricted availability of energy (mobile systems) limited battery capacities (only slowly improving)

ver hi h costs of ener solar anels, in s ace

cooling high costs

limited space

dependability

long lifetimes, low temperatures

Power Consumption in CMOS Digital Logic

Dynamic power consumption

charging and discharging capacitors

Short circuit currents

short circuit path between supply rails duringswitching

Leakage

leaking diodes and transistors

problem even when in standby!


3/40

Power Consumption in CMOS Digital logic

Dynamic power Power due to

short-circuit Power due to

P = ACV2 f + AIsw Vf + Ileak V

where

current duringtransition

leakage current

A = activity factor (probability of 0 1 transition)C = total chip capacitanceV = total voltage swing, usually near the power supply voltage

f = clock frequency

Isw = short circuit current when logic level changes

Ileak = leakage current in diodes and transistors

Dynamic Power Consumption

V Supply voltage

Trend: has been dropping

with each successive fab

C Total capacitance

seen by the gates output s

Function of wir e lengths,

fACV2

A - Act iv it y o f gates

How often on average do

wires switch?

f clock frequency

Trend: increasing ...

, ...

Reducing Dynamic Power

1) Reducing V has quadratic effect; Limits?

2) Lower C - shrink structures, shorten wires

3) Reduce switching activity - Turn off unused parts or

use design techniques to minimize number of transitions


4/40

Short-circuit Power Consumption

fAVI

Finite slope of the input signal

causes a direct current path

between VDD and GND for a

short period of time during

switching when both the

NMOS and PMOS transistors

Vin Vout

CL

Ishort

are conducting

Reducing Short-circuit

1) Lower the supply voltage V

2) Slope engineering match the rise/fall time of the input and output signals

Leakage Power

leakVI

Sub-threshold current grows exponentially with

increases in temperature and decreases in Vt

Sub-threshold

current


5/40

How can we reduce

power consumption?Dynamic power consumption Reduce the rate of charge/discharge of highly loaded nodes Reduce spurious switching (glitches) Reduce switching in idle states (clock gating) Decrease frequency Decrease voltage (and frequency)

Static power Consumption Smaller area (!) Reduce device leakage through power gating Use higher-threshold transistors when possible

Power performance tradeoffs!

Why not simply lower V?

Total P can be minimized by lower V

lower V are a natural result of smaller feature sizes

But transistor speeds decrease dramatically as V is

reduced to close to threshold voltage

performance goals may not be met

td = CV / k(V-Vt) where is between 1-2

Why not lower this threshold voltage?

makes noise margin and Ileak worse!

Need to do smarter voltage scaling!


6/40

Approaches to Energy Efficiency

P = C V2 f

Continuous Event-Driven

Latency is ImportantOnly Throughput is

Important

Reduce V

(Burst throughput)

Increase h/w andMake f low or 0

Shutdown when

e.g., Speech CodingVideo Compression

e.g., X Display Servera gor m c concurrency

Disk I/OReduce CEnergy efficient s /w CommunicationSystem partition ing

nac ve

Efficient Circuits & Layouts

Speed vs. Voltage

7.0

3.0

5.0Normalized

Delay

1.0 1.5 2.0 2.5 3.0

Supply Voltage, V

1.0


7/40

Reducing the Supply Voltage: an Architectural

Approach

Operate at reduced voltage at lower speed

Use architecture optimization to compensate for slower

e.g. concurrency, pipelining via compiler techniques

Architecture bottlenecks limit voltage reduction

degradation of speed-up

interconnect overheads

Trade-off AREA for lower POWER

Fundamentals of dynamic voltage scaling (DVS)

Power consumption of CMOS

circuits (ignoring leakage):

2

Delay for CMOS circuits:

fre uencclock:

voltagesupply:

ecapacitancload:

activityswitching:

f

V

C

dd

L

ddL

)than(

voltagethreshhold:

with2

ddt

t

tdd

ddL

VV

V

VVCk

Decreasing Vdd reduces P quadratically,

while the run-time of algorithms is only linearly increased

E=P x t decreases linearly

(ignoring the effects of the memory system and Vt)


8/40

Voltage scaling: Example

Vdd[Courtesy, Yasuura, 2000]

Tframe Tframe

Fixed Supply Variable Supply

Varying the Supply Voltage

Active Idle

Efixed = 1/2 CVdd2

Active

Evar = 1/2 C(Vdd/2)2 = 1/4Efixed

0.6

0.8

1.0

Normalized Fixed Supply

0 0.2 0.4 0.6 0.8 1.00

0.2

0.4

Normalized Workload

Variable Supply

from [Gutnik96](VLSI Symposium)


9/40

Low-power Software

Wireless industry Constantly evolving standards

Systems have to be flexible and adaptable

Significant portion of system functionality is implemented as

software running on a programmable processor

Software drives the underlying hardware Hence, it can significantly impact system power consumption

software design.

Low-power Software Strategies

Code running on CPU

Code o timizations for low ower

Code accessing memory objects

SW optimizations for memory

Data flowing on the buses

I/O coding for low power

CPU

Cache

Compiler controlled power management

Memory


10/40

Dynamic Power Optimization

Two main steps:

Workload allocation to processing elements: task mapping and

schedulin

Af ter workload allocation, resource of p rocessing elements

should be adapted to the required performance to minimize

energy consumption

shut-down voltage scaling

Shut-Down

When the system is idle the processor can be placed into a

-

reactivity power level-core clock gating (waked-up by timer interrupt)

- core power gating (waked-up by on-chip peripherals)

no need for context restore

-chip power gating (waked-up by external, on board

interrupts)

nee or con ex res ore


11/40

Shutdown for Energy Saving

Blocked

Active

Subsystems may have small duty factors

CPU, disk, wireless interface are often idle

Tblock Tactive ideal improvement = 1 + Tblock/Tactive

uge erence e ween on o power Some Low-Power CPUs: StrongARM 400mW (active)/ 50 mW (idle) / 0.16 mW (sleep)

2.5 Hard Disk: 1.35W (idle spinning) / 0.4W (standby) / 0.2W (sleep) / 4.7W (start-up)

Example: SA-1100 CPU

400 mW

IDLE

CPU stopped when not inuse

Monitoring for interrupts

RUN

10 s 10 s

90 s

160 ms

SLEEP

Shutdown on-chip activity IDLE SLEEP

50 mW 0.16 mW

90 s


12/40

When is DPM useful?

Ptr Ttr

If Ttr=0, Ptr=0 then DPM policy is trivial Stop a component when it is not needed

Off On

Ptr Ttr

If, as is usual, Ttr!=0, Ptr!=0 shutdown only when idleness is going to be long enough to

make it worthwhile

Complex decision if the time spent in state is not deterministic

Breakeven Point

Breakeven point: minimum idle time that would make it

worthwhile to shutdown

DPM worthwhile when TBE < Average Tidle


13/40

Problems in Shutdown

Cost of restarting: latency vs. power trade-off

increase in latency (response time) e. . time to save restore CPU state, s in u disk

increase in power consumption e.g. higher start-up current in disks

When to Shutdown

Optimal vs. Idle Time Threshold vs. Predictive

When to Wakeup

Optimal vs. On-demand vs. Predictive

Cross-over point for shutdown to be effective

Frequency/Voltage Scaling

DFVS:

Frequency must be scaled with voltage to keep circuit

functionality

Dynamic power goes with the square of Vdd andlinearly with clock speed

Scaling V and F by a factor of s -> power scales as s3

fVCP ddeff 2


14/40

Shutdown vs. Variable Voltage

Example: task with 100ms deadline, requires 50ms CPU

time at full s eed

When Voltage Reduction is Better

normal system gives 50ms computation, 50ms idle/stopped

time

half speed/voltage system gives 100ms computation, 0ms

idle

same number of CPU cycles but 1/4 energy reduction

T1 T2 T1 T2

Speed

Time

Idle

Same work,

lower energyTask

Task

Problem with Voltage Reduction

Voltage gets dictated by the tightest (critical) timing constraint

not a problem if latency not important ,

parallelism etc.

but, real systems have bursty throughput and latencycritical tasks

Solution: dynamically vary the voltage!


15/40

Barriers to Future Voltage Scaling

Voltage scaling requires threshold voltage Vt to be scaled as well (15%

per generation)

this increases sub-threshold leakage current

impact on power consumption and circuit robustness

scaling V and Vt poses serious challenges to special circuits such as

domino logic, sense amplifiers

Leakage power

total leakage current goes up 7.5x per generation

leakage power power by 5x

active power remains constant for constant die size

leakage power, and therefore total power, can be substantially

reduced by cooling Essential to control die temperature

power density (W/cm2): 0.6 micron chips surpassed a hot plate!

Energy Use scaling while it

Scaling vs. Shutdown

Region of

scaling

Region of

shutdown

Emin

If more time is

allowed, scale

down to the

minimum energy

point and

subsequently use

shutdown

Power

time

allowed time

Execution time = t*

Power

time

allowed time

Execution time = t*

Power

time

allowed timeExecution time

t


16/40

Energy in Radio

x: ece ver

ChannelIncoming

informationOutgoing

information

Tx

elecE Rx

elecERFE

Transmit ReceivePower

Wireless communication subsystem consists of threecomponents with substantially different characteristics

Their relative importance depends on the transmissionpowerof the radio

Tx Electronics Rx Electronics

txElecstarttx PEP rxElecstartrx PEP

Path Loss

Prcvd P1m dn

Communication Energy Model

P P 2Digital Processing

ProtocolMAC

Link

Radio

Tx

ProtocolMAC

Link

Radio

Rx

Power Amp Efficiency

amp amp amp out bit bit DD

VDDIleak(VDD,VTH) Tbit(VDD,VTH)

CbitIleakTbitVDDVTH

Estartn

P1mPoutPrxElecPtxElec

Switched capacitance per bit

Leakage current

Processing time per bit

Supply Voltage

Transistor Threshold Voltage

Startup (turn-on) energy

Path loss exponent

Attenuation over one meter

Output power from power amp

Receiver static power

Transmitter static power

Min et. al., Mobicom 2002 (Poster)


17/40

Energy Consumption of Transmit ting a Packet

overheadbitselectronictransmitpacket EHLTPPE

Power consumed by the power amplifier, depends on the required

performance and the wireless channel (distance, fading, etc.)P

transmit

Power consumed by the electronic circuitry for filtering,

upconverting, modulation, frequency synthesis, etc.P

electronics

Energy consumption that is independent of the packet size andE

modulation scheme (startup cost, fixed encoded header, etc.)over ea

Time to transmit one bit (depends on modulation and symbol rate Rs)Tbit

Size of packet payloadL

Size of packet headerH

Energy Consumption of Transmitting a Bit

Minimize header

size

Minimize

overhead

: Optimize

modulation

Independent of

bitE

LL

TPPL

overheadbitselectronictransmit

packet 1

modulationModulation

Scaling


18/40

Energy per Bit

JEbit

Region of modulation scalingPtransmit

4-QAM 9 mW

electronics

Rs 1 Mbaud

Beyond Energy Efficiency: Battery-aware Design

Theoretical capacity of battery is decided by the amount of the activematerial in the cell

batteries often modeled as buckets of constant energye.g. halving the power by halving the clock frequency is assumedto double the computation time while maintaining constant

computation per battery life

In reality, delivered or nominal capacity depends on how the battery isdischarged

sc arge ra e oa curren

discharge profile and duty cycle

operating voltage and power level drained


19/40

Problem Formulation

Due to battery properties, the waysat which the batteries are

time

Total Service, S

U discharged have impact on theactual lifetime

Static Approach: Fix U(t), find theoptimal U that maximize S

T

t

APP dttUS0

)(

Dynamic Approach: Heuristicapproach to find optimal U(t)

Power and energy are related to each other

dtPE

EE'

t

In many cases, faster execution also means less energy, but

the opposite may be true if power has to be increased to allow

faster execution.


20/40

Battery Characteristics

Important characteristics: energy density (Wh/liter) and specific energy (Wh/kg)

ower densit W/liter and s ecific ower W/k

open-circuit voltage, operating voltage

cut-off voltage (at which considered discharged)

shelf life (leakage)

cycle life

The above are decided by system chemistry

significant changes in older systems carbon-zinc, alkaline manganese, NiCd, lead-acid

new systems primary and secondary (rechargeable) Li

secondary zinc-air, Ni-metal hydride

Modeling the Battery Behavior

Theoretical capacity of battery is decided by the amount of the

active material in the cell

e.g. halving the power by halving the clock frequency is

assumed to double the computation time while maintaining

constant computation per battery life

In reality, delivered or nominal capacity depends on how the

battery is discharged

sc arge ra e oa curren

discharge profile and duty cycle

operating voltage and power level drained


21/40

Battery Model: Physical Picture

Battery Capacity

100

Current in C rating:

load current normalized to batterys capacity

e.g. a discharge current of 1C for a capacity of 500 mAh is 500 mA


22/40

Battery Capacity vs. Discharge Current

Amount of energy delivered is decreased as the current (rate

at which power is drawn) is increased

at a specific rate to a specific cut-off voltage primary cells rated at a current which is 1/100th of the

capacity in ampere hours (C/100)

secondary cells are rated at C/20 or C/10

At high currents, the diffusion process that moves new active

concentration of active material at cathode drops to

zero, and cell voltage goes down below cut-off

even though active material in cell is not exhausted!

Battery Capacity vs. Discharge Current

Peukerts Formula

Peukerts Law expresses the capacity of a battery

in terms of it discharge.

CP = Ikt

CP is the capacity according to Peukert (A.h).I discharge current.

k Peukert constant .

t time of discharge.


23/40

Ragone Plots (log-log plot )

Specific Power

W/kg

Specific Energy

Wh/kg

Al ternate Equivalent View of the Battery

Manufacturers often give battery efficiency (%) vs. discharge rate

(or discharge current ratio)

dischar e rate = I /I

Battery cannot respond to instantaneous changes in current so, a

time constant used to calculate Iave

Given actual energy drawn by the circuit, one can use the battery

efficiency to calculate the actual depletion in the stored energy in

Example:

battery efficiency is 60% and its rated capacity is 100 mAh @ 1V

computed average DC-DC current of 300 mA would drain the

battery in 12 min, while at 100% efficiency it would last 1 hr


24/40

Modeling Battery Efficiency

rated

aveI

I

IR

cycle

batT

N

batN

c cleII1

cyclebatN 0

cyclebatavebatbat TVIE )1(

from [Simunic01]

Capacity & Variable Discharge Current

Constant vs. Pulsed

Capacity can be extended by draining power in short discharge

also works with constant background current

Battery relaxes and partially recovers the active material lost

during the current impulse

longer the rest period, the better is the recovery

longer rest period needed as the discharge depth becomes greater

battery voltage also goes back up


25/40

Benefits of Pulsed Discharge

Higher specific power for a given specific energy

impulses of several times the limiting current value

rest periods

Higher specific energy for a given specific power

ideally, want specific energy = theoretical capacity

depends on pulse and rest periods

Exploiting Pulse Discharge

Gain in battery life if system shutdown is done taking into

account the pulse discharge

Examples:

protocols in case of radios where power during

transmission is a lot higher than during receive andidle periods

shutdown of CPUs and variable speed CPUs

shutdown of disks


26/40

Rate Capacity Effect

Capacity depends on the discharge rate

Summary of Battery

Non-Idealities

Relaxation Effect

When discharge current is either cutoff or reduced, the batterys

capacity is recovered

2.66

2.68

2.7

2.72

V)

0 100 200 300 400 500 600

time (sec)

2.56

2.58

2.6

2.62

2.64

Voltag

e( .

1.9 mA

Battery Modeling

Predict battery lifetime given a load profile

Model electrochemical processes in the battery Solve system of PDEs, e.g. Berkeleys DUALFOIL Accurate but long simulation times and large number of

parameters (e.g. > 50 with DUALFOIL) Not easy to use in an optimization tool

Abstract representation of batteries E.g. Markov chain

Not easy to use in an optimization tool

Analytical models Capture key factors of battery performance E.g model by Rakhmatov & Vrudhula @ U. Arizona


27/40

Lithium Battery Charging

Example of Rechargeable Battery management


28/40

Example of Rechargeable Battery management

Example of Non-Rechargeable Battery management


29/40

Battery Charging Method

Trickle Charging -dT/dt cutoff

-V cutoff Time controlled charging

Al ternatives to Bat teries?

Small batteries are the only choice for consumer productsup to 20W

But heavy expensive

expire without warning require replacement (disposal problem) or recharging

(time problem)

Are there alternatives?

YES, we canharvest the energy!!!!


30/40

How to Select and Use Power

Supplies and dc/dc Converters for

Your Applications

Introduction to Power Supplies and dc/dc

Converters

Available/Raw Power Sources

Un-regulated (changes with load, prime source, etc.)

Voltage (different level, polarity, isolation)

Non-protected (against over load, fault, temp., etc.)

Load Demand

Regulated (against load, prime source, etc.)

Voltage (different level, polarity, isolation)

Protected (against over load, fault, temp., etc.)


31/40

Desired power out

Introduction to Power Supplies and dc/dc

Converters

Power & Electronic

Circuits

Raw power in(V, I, P, F)

To loads:

Electronic ckts

Motor

Computer

Battery

Fuel Cell

AC Out let

Solar

Power Supply qu pmen

Control

Power Suppl ies and dc/dc Converters

Types & Technologies

AC-DC Power Supply (or AC Adapter)

Change ac power into regulated dc power, e.g., a typical AC Adapter takes 120

V ac input and converter it to regulated 5 Vdc.

DC-DC Converters

Change dc at one voltage potential to a dc at a different voltage potential

DC-AC Power Supply (for example, UPS, 12Vdc-

120Vac ada ter

AC-AC Power Supply/Regulator (for example, line

regulator)


32/40

Linear Regulators

+ Simple, inexpensive

- Vout < Vin

- Poor Efficiencye.g., if Vin = 6V, Vout = 3V, Efficiency = %?

- Can be physically large

Switching Regulators

Also known as DC-DC Converters or

Switchmode Regulators

+ Wide range of input voltages

+ Multiple output voltages possible+ High Efficiency (sometimes >90%!)

+ Compact

- ,

- Electrically noisy (not pure DC)


33/40


A few types

Buck (step-down)

oost step-up

Flyback (supports multiple outputs; transformer needed)

Buck-boost (step-up or down)

SEPIC, Zeta, Cuk (specialized buck-boost)

Charge Pump (no inductor)


Buck Converter

Continuos mode Discontinuos Mode

D = Duty Cycle


34/40


Boost Converter

on nuos mo e scon nuos o e

D = Duty Cycle


Buck Boost Converter

D = Duty Cycle

Continuos mode Discontinuos Mode


35/40

A.K.A. charge pump or flying capacitor


Switched Capacitor

n uc or ess ow cos

Work well for loads up to ~100mA

Produce output voltage equal to Vin or 2 x Vin

Output noisy and poorly regulated,

but OK for certain applications

AC-DC Power Suppl ies

Circuit Selection and Design

Using Linear Regulators

Step-downXfmer

Regulator120 VAC

For low power (some watts or below) applications.

Low effic iency, large size and weight

(bulky step-down line transformer)

Low cost


36/40

AC-DC Power Suppl ies

Circuit Selection and Design

Using Switching-Mode

High efficiency

Small size and light weight

For high power (density) applications

Selecting the Right dc/dc Converter

The Need for dc/dc Converters

E.g., a single AA alkaline battery produces 1.5 V when fully charged and its voltage

drops to as low as 0.9 V when becoming depleted.

Dc/dc Converter Types

Buck

Boost

Buck-Boost

Dc/dc Converter Technologies

Linear Regulators


Charge Pumps


37/40

Selecting the Right dc/dc Converter

Dc/dc converter technology comparison

Linear Switchingregulator regulator

Efficiency Low High Medium

EMI Noise Low High Medium

Output current Low to medium Low to High Low

Boost (step-up) No Yes Yes

Buck (step-down)

Yes Yes Yes

Solution size small Large Medium

Selecting the Right dc/dc Converter(example mobile phone)

VBAT = 3.7 V nom, Vcircuit= 1.2 V

Load Current = 600 mA

Power delivered to load = 600 mA * 1.2 V = 720 mW

Power converted to heat =

Linear regulators:

Inexpensive

m . . - = , mTotal power consumed =

720 mW + 1,500 mW = 2,200 mW

32% goes to work , 68% goes to heating user hand and earwhen using a Linear Regulator for a mobi le device

VBAT = 3.7 V nom; Vci rcui t = 1.2 V

Load Current = 600 mA

low part count

low noise

high ripple rejection

Switching regulators:Converter efficiency = 90%

Power delivered to load = 600 mA * 1.2 V = 720 mW

Power conver ted to heat =720 mW * ((1/0.9)-1)=80 mW

Total power consumed = 720 mW + 80 mW = 800 mW

90% goes to work , 10% goes to heating user hand and ear

When using a Switch-mode regulator for a mobile device.

a bigger footprint

higher part count,

more cost

prone to conducted and

radiated EMI.


38/40

Specs, Performance and Protection

Voltage ripple (+-50 mV, or 5%)

Isolation e. . 1 500 V ac for 1 min.

Load regulation (e.g., 3%)

Dynamic response (transients, wake-up time, etc.)

Short circuit protection

OC protection (Overcharge)

OV protection (Overvoltage)

OT protection (Overtemperature)

Power Losses and Thermal Design

For example, a 7815 linear regulator with input voltage of 20 V and

output current of 1 A.

The power loss is (20-15)Vx(1 A)=5 W.

From the chip to the ambient, Ti can be calculated according to thethermal circuit using Ohms law (R=V/I), where R is the thermal

resistance, V is the temperature and I is the power dissipation.

case ambientThcase ambient

T TR

Where:

Tcase is case Temp.Tambient is ambient Temp.

issipation

outdissipation in out out

op

PP P P P

Pdissipation is power loss

Pin is input power

Pout is output powerop is efficiency undergiven operating conditi ons


39/40


A more detailed thermal circuit

W : Device power loss

Tj : Junction temperature of device

Tc : Device case temperature

Tf : Temperature of heatsink

Ta : Ambient temperature

Rth(j-c) : Thermal resistance between junction and case,

specified in datasheet

Rth(c-f) : Contact thermal resistance between case and

ea s n , spec e n a as ee

Rth(f-a) : Thermal resistance between heatsink and

ambient air, specified by the heatsink manufacturer


= - +

Tc=W{Rth(c-f) + Rth(f-a)}+Ta


40/40

Examples

Device : 7815 (Linear regulator)

Vin=20V, Vo=15V, Io=1A

- Rth(j-c) : 5 C/W

Rth(c-f) : 0.5 C/W, Greased surface

Rth(f-a) :20 C/W

Ta=25 CAn assortment of 78XX ser ies

Tc=5(0.5 + 20)+25=127.5 C

Tj=51+127.5=132.5 C

Tj=82.5-25=107.5CAn assortment of heatsinks

ees11 - power management

Documents