eel 4783: hdl in digital system designmingjie/eel4783/lect.11a.pdfbus invert coding against...
TRANSCRIPT
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EEL 4783: HDL in Digital System Design
Lecture 5a: Architeching Power
Prof. Mingjie Lin
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Power Dissipation
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Dynamic Power
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Static Power
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Static Power
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Low Power Design Methodologies
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Low Power Design Methodologies
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Low Power Design Methodologies
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Low Power Design Methodologies
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Low Power Design Methodologies
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Minimize Data Transition on Bus
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Bus Coding
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Bus Invert Coding
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Low Power Design Methodologies
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Low Power Design Methodologies
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How Effective is Clock-Gating?
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Low Power Design Methodologies
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Low Power Design Methodologies
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Resource Sharing
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Design Flow Integration
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Power Characterization and Modeling
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Generalized Low-Power Design Flow
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Design-Phase Low Power Design
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Clock Gating
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Clock Gating Insertion
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Clock Gating Verilog Code
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Clock Gating: Glitch Free Verilog
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Data Gating
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Data Gating Insertion
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Data Gating Verilog Code: Operand Isolation
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Memory System Design
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Split Memory Access
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Implementation Phase Low Power Design
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Power Gating
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Final issues
• Come by my office hours (right after class)
• Any questions or concerns?