eee digital question bank

8/3/2019 Eee Digital Question Bank

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UNIT-I

2 Marks

1) Given the two binary numbers X = 1010100 and Y = 1000011,perform the

subtraction (a) X -Y and (b) Y - X using 2s complements.X = 10101002s complement of Y = + 0111101-------------Sum = 10010001Discard end carryAnswer: X - Y = 0010001b) Y = 10000112s complement of X = + 0101100---------------

Sum = 1101111There is no end carry,Therefore the answer is Y-X = -(2s complement of 1101111) =-00100012). Given the two binary numbers X = 1010100 and Y = 1000011,perform thesubtraction (a)X -Y and (b) Y - X using 1s complements.a). X - Y = 1010100 - 1000011X = 1010100

1s complement of Y = + 0111100--------------Sum = 10010000End -around carry = + 1--------------Answer: X - Y = 0010001

b). Y - X = 1000011 - 1010100Y = 10000111s complement of X = + 0101011

-----------Sum = + 1101110There is no end carry.Therefore the answer is Y - X = -(1s complement of 1101110) =-0010001

3). What is meant by parity bit?A parity bit is an extra bit included with a message to make the totalnumber of


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1s either even or odd. Consider the following two characters and theireven and odd parity:With even parity With odd parity

ASCII A = 1000001 01000001 11000001

ASCII T = 1010100 11010100 01010100

In each case we add an extra bit in the left most position of the code toproducean even number of 1s in the character for even parity or an oddnumber of 1s in the character for odd parity. The parity bit is helpful indetecting errors during the transmission of information from onelocation to another.

4).What are registers?Register is a group of binary cells. A register with n cells can store any

discrete quantity of information that contains n bits. The state of aregister is an n-tuple number of 1s and 0s, with each bit designatingthe state of one cell in the register.

5). What is meant by register transfer?A register transfer operation is a basic operation in digital systems. Itconsists oftransfer of binary information from one set of registers into another setof registers. The transfer may be direct from one register to another, ormay pass through data processing circuits to perform an operation.

6). Define binary logic?Binary logic consists of binary variables and logical operations. Thevariables are designated by the alphabets such as A, B, C, x, y, z, etc.,with each variablehaving only two distinct values: 1 and 0. There are three basic logicoperations: AND, OR, and NOT.

7). Define logic gates?Logic gates are electronic circuits that operate on one or more input

signals toproduce an output signal. Electrical signals such as voltages orcurrents exist throughout a digital system in either of two recognizablevalues. Voltage- operated circuits respond to two separate voltagelevels that represent a binary variable equal to logic 1 or logic 0.

8).Define duality property.Duality property states that every algebraic expression deducible fromthe


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postulates of Boolean algebra remains valid if the operators andidentity elements are interchanged. If the dual of an algebraicexpression is desired, we simply interchange OR and AND operatorsand replace 1s by 0s and 0s by 1s.

9).Find the complement of the functions F1 = xyz + xyz and F2 =x(yz + yz).

By applying De Morgans theorem as many times as necessary.F1 = (xyz + xyz) = (xyz)(xyz) = (x + y + z)(x + y +z)F2 = [x(yz + yz)] = x + (yz + yz)= x + (yz)(yz)= x + (y + z)(y + z)

10).Find the complements of the functions F1 = xyz + xyz and F2 =x(yz + yz). by taking their duals and complementing each literal.F1 = xyz + xyz

The dual of F1 is (x + y + z)(x + y + z)

Complementing each literal: (x + y + z)(x + y + z)F2 = x(yz + yz).

The dual of F2 is x + (y + z)(y + z).Complement of each literal: x + (y + z)(y + z)

11).State De Morgans theorem.De Morgan suggested two theorems that form important part ofBoolean algebra.

They are,1) The complement of a product is equal to the sum of the

complements.(AB) = A + B2) The complement of a sum term is equal to the product of thecomplements.(A + B) = AB

12).Reduce A.ACA.AC = 0.c [A.A = 1] = 0

13). Reduce A(A + B)

A(A + B) = AA + AB= A(1 + B) [1 + B = 1]= A.

14. Reduce ABC + ABC + ABCABC + ABC + ABC = AC(B + B) + ABC= AC + ABC [A + A = 1]= A(C + BC) = A(C + B) [A + AB = A + B]


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15.) Reduce AB + (AC) + ABC(AB + C)AB + (AC) + ABC(AB + C) = AB + (AC) + AABBC + ABCC= AB + (AC) + ABCC [A.A = 0]= AB + (AC) + ABC [A.A = 1]= AB + A + C =ABC [(AB) = A + B]= A + B + C + ABC [A + AB = A + B]= A + BC + B + C [A + AB = A + B]

= A + B + C + BC=A + B + C + B=A + C + 1= 1 [A + 1 =1]

16. Simplify the following expression Y = (A + B)(A + C )(B + C )Y = (A + B)(A + C )(B + C )= (AA + AC +AB +BC )(B + C) [A.A = 0]

= (AC + AB + BC)(B + C )= ABC + ACC + ABB + ABC + BBC + BCC= ABC + ABC

17).Simplify the following using De Morgans theorem [((AB)C) D][((AB)C) D] = ((AB)C) + D [(AB) = A + B]= (AB) C + D= (A + B)C + D

18.Show that (X + Y + XY)( X + Y)(XY) = 0

(X + Y + XY)( X + Y)(XY) = (X + Y + X)(X + Y )(X + Y) [A + AB = A+ B]= (X + Y )(X + Y )(XY) [A + A = 1]= (X + Y )(XY) [A.A = 1]= X.X + Y.X.Y= 0 [A.A = 0]

19).Prove that ABC + ABC + ABC + ABC = AB + AC + BCABC + ABC + ABC + ABC =AB(C + C) + ABC + ABC=AB + ABC + ABC

=A(B + BC) + ABC=A(B + C) + ABC=AB + AC + ABC=B(A + C) + AC=AB + BC + AC=AB + AC +BC ...Proved

20).Convert the given expression in canonical SOP form Y = AC + AB +BC


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Y = AC + AB + BC=AC(B + B ) + AB(C + C ) + (A + A)BC=ABC + ABC + ABC + ABC + ABC + ABC + ABC=ABC + ABC +ABC + ABC [A + A =1]

21).Convert the given expression in canonical POS form Y = ( A + B)(B+

C)(A + C)Y = ( A + B)(B + C)(A + C)= (A + B + C.C )(B + C + A.A )(A + B.B + C)= (A + B + C)(A + B + C )(A + B +C)(A + B +C)(A + B + C)(A + B +C) [A + BC= (A + B)(A + C) Distributive law]

= (A + B + C)(A + B + C)(A + B + C)(A + B + C)(A + B + C)

22). Find the minterms of the logical expression Y = ABC + ABC +

ABC+ ABC

Y = ABC + ABC + ABC + ABC=m0 + m1 +m3 +m6=p

____________

23).Write the maxterms corresponding to the logical expression Y = (A+ B + C )(A + B +C)(A + B + C)

Y = (A + B + C )(A + B + C)(A + B + C)

=M1.M3.M6

24).Convert (4021.2)5 to its equivalent decimal.(4021.2)5 = 4 x 53 + 0 x 52 + 2 x 51 + 1 x 50 + 2 x 5-1= (511.4)10

25) Using 10s complement subtract 72532 - 3250M = 7253210s complement of N = + 96750

-----------Sum = 169282Discard end carryAnswer = 69282

26) What are called dont care conditions?In some logic circuits certain input conditions never occur, thereforethe


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corresponding output never appears. In such cases the output level isnot defined, it can be either high or low. These output levels areindicated by X ord in the truth tables and are called dont careconditions or incompletely specified functions.

27) Write down the steps in implementing a Boolean function withlevels of

NAND Gates?Simplify the function and express it in sum of products.Draw a NAND gate for each product term of the expression that has atleast twoliterals. The inputs to each NAND gate are the literals of the term. Thisconstitutes agroup of first level gates. Draw a single gate using the AND-invert orthe invert-OR graphic symbol in the second level, with inputs comingfrom outputs of first level gates. A term with a single literal requires aninverter in the first level. How ever if the single literal is

complemented, it can be connected directly to an input of the secondlevel NAND gate.

28) Give the general procedure for converting a Boolean expression intomultilevel NAND diagram?Draw the AND-OR diagram of the Boolean expression.Convert all AND gates to NAND gates with AND-invert graphic symbols.Convert all OR gates to NAND gates with invert-OR graphic symbols.Check all the bubbles in the same diagram. For every bubble that is

not compensated by another circle along the same line, insert aninverter or complement the input literal.

29) What are combinational circuits?A combinational circuit consists of logic gates whose outputs at anytime are Determined from the present combination of inputs. Acombinational circuit performs an operation that can be specifiedlogically by a set of Boolean functions. It consists of input variables,logic gates, and output variables.

30) Give the design procedures for the designing of a combinationalcircuit.The procedure involves the following steps,

From the specification of the circuit, determine the required number of inputs and outputs and assign a symbol to each.

Derive the truth table that defines the required relationships between inputs and outputs.

Obtain the simplified Boolean functions for each output as a function of the input variables.


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Draw the logic diagram and verify the correctness of the design.

31) Define half adder.A combinational circuit that performs the addition of two bits is called ahalf adder. A half adder needs two binary inputs and two binaryoutputs. The input variables designate the augend and addend bits;the output variables produce the sum and carry

32) Define full adder?A combinational circuit that performs the addition of three bits is a fulladder. It consists of three inputs and two outputs.

33) Define binary adder.A binary adder is a digital circuit that produces the arithmetic sum oftwo binarynumbers. It can be constructed with full adders constructed in cascade,with the output carry from each full adder connected to the input carry

of the next full adder in the chain.

34) What is overflow?Over flow is a problem in digital computers because the number of bitsthat hold

The number is finite and a result that contains n + 1 bits cannot beaccommodated.

For this reason many computers detect the occurrence of an overflow,and when it occurs a corresponding flip flop is set that can be checked

by the user. An overflow condition can be detected by observing thecarry into sign bit position and the carry out of the sign bit position. Ifthese two carries are not equal, an overflow has occurred.

35) Define magnitude comparator?A magnitude comparator is a combinational circuit that compares twonumbers, Aand B, and determines their relative magnitudes. The outcome of thecomparison isspecified by three binary variables that indicate whether a>b, A = b, or

A < B.

36) What are decoders?A decoder is a combinational circuit that converts binary informationfrom n inputlines to a maximum of 2n unique output lines. If the n bit codedinformation has unused combinations, The decoder may have fewerthan 2n outputs.


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37) What are encoders?An encoder is a digital circuit that performs the inverse operation of adecoder.An encoder has 2n and n output lines. The output lines generate thebinary codecorresponding to the input value.

38) Define priority encoder?A priority encoder is an encoder circuit that includes the priorityfunction. Theoperation of priority encoder is such that if two or more inputs areequal to 1 at the same time, the input having the highest priority willtake precedence.

39) Define multiplexer?A multiplexer is combinational circuit that selects binary informationfrom one of many input lines and directs it to a single output line. The

selection of a particular input line is controlled by a set of selectionlines. Normally there are 2n input lines and n selection lines whose bitcombinations determine which input is selected.

40) Define binary decoder?A decoder which has an n- bit binary input code and a one activatedoutput out-of -2N output code is called binary decoder. A binarydecoder is used when it is necessary to activate exactly one of 2Noutputs based on an n-bit input value.

16 Marks

1. Obtain the minimum sop using QUINE- McCLUSKY method and verifyusing K-map F=m0+m2+m4+m8+m9+m10+m11+m12+m13. (16)

2. Reduce the following using tabulation method.F=m2+m3+m4+m6+m7+m9+m11+m13. (16)

3. Reduce the Boolean function using k-map technique and implementusing gates f (w, x, y, z)= _m (0,1,4,8,9,10) which has the dont carescondition d (w, x, y, z)= _m (2,11). (16)

4. Find the minimum SOP expression using K-map for the function f=_m (7, 9, 10, 11, 12, 13, 14, 15) and realize the minimized functionusing only NAND gates. (16)


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5. a) Expand the following Boolean expression to minterms andmaxterms (8)F= A+BC+ABD+ABCDb).Prove the following (A+B) ((AC)+C) (B+AC)=AB. (8)

6. a) Design a 2-bit magnitude comparator? (8)

b). Using 8 to 1mux, realize the Boolean function (8)T=F (w, x, y, z)= _m (0,1,2,4,5,7,8,9,12,13)

7. a) Design an 8421 to gray code converter. (8)b).Implement the Boolean function using 8:1 mux. (8)F (A, B, C, D) =ABD+ACD+BCD+ACD.8. a) Explain the operation of 4 to 10 decoder. (8)b). Implement the following multiple output combinational logic circuitusing a3-to8 decoder.

F1= _m (1, 2, 3, 5, 7)F2= _m (0, 3, 6)F3= _m (0, 2, 4, 6) (8)

4. Design a 4-bit adder /subtractor-using logic gates and explains itsoperation. (16)5. Construct a combinational circuit to convert BCD to EX-3 code. (16)6. Design A Full Adder And A Full Subtractor. (16)

UNIT-II

2 Marks

1. What are the classification of sequential circuits?The sequential circuits are classified on the basis of timing of theirsignals into two


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types. They are,1)Synchronous sequential circuit.2)Asynchronous sequential circuit.

2. Define Flip flop.The basic unit for storage is flip flop. A flip-flop maintains its outputstate either at 1

or 0 until directed by an input signal to change its state.

3.What are the different types of flip-flop?There are various types of flip flops. Some of them are mentionedbelow they are,1. RS flip-flop2. SR flip-flop3. D flip-flop4. JK flip-flop5. T flip-flop

4.What is the operation of D flip-flop?In D flip-flop during the occurrence of clock pulse if D=1, the output Qis set and ifD=0, the output is reset.

5. What is the operation of JK flip-flop?1. When K input is low and J input is high the Q output of flip-flop is set.2. When K input is high and J input is low the Q output of flip-flop isreset.

3. When both the inputs K and J are low the output does not change4. When both the inputs K and J are high it is possible to set or resetthe flip-flop (ie) the output toggle on the next positive clock edge.

6. What is the operation of T flip-flop?T flip-flop is also known as Toggle flip-flop.1. When T=0 there is no change in the output.2. When T=1 the output switch to the complement state (ie) the outputtoggles.

7. Define race around condition.In JK flip-flop output is fed back to the input. Therefore change in theoutput results change in the input. Due to this in the positive half ofthe clock pulse if both J and K are high then output togglescontinuously. This condition is called race around condition.


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8. What is edge-triggered flip-flop?The problem of race around condition can solved by edge triggeringflip flop. The term edge triggering means that the flip-flop changesstate either at the positive edge or negative edge of the clock pulseand it is sensitive to its inputs only at this transition of the clock.

9. What is a master-slave flip-flop?A master-slave flip-flop consists of two flip-flops where one circuitserves as a master and the other as a slave.

10.Define rise time.The time required to change the voltage level from 10% to 90% isknown as rise time(tr).11.Define fall time.

The time required to change the voltage level from 90% to 10% is

known as fall time(tf).

12.Define skew and clock skew.The phase shift between the rectangular clock waveforms is referred toas skew and the time delay between the two clock pulses is calledclock skew.

13.Define setup time.The setup time is the minimum time required to maintain a constantvoltage levels at the excitation inputs of the flip-flop device prior to the

triggering edge of the clock pulse in order for the levels to be reliablyclocked into the flip flop. It is denoted as tsetup.

14. Define hold time.The hold time is the minimum time for which the voltage levels at theexcitation inputs must remain constant after the triggering edge of theclock pulse in order for the levels to be reliably clocked into the flipflop. It is denoted as thold .

15. Define propagation delay.

A propagation delay is the time required to change the output after theapplication of the input.

16.Define registers.A register is a group of flip-flops flip-flop can store one bit information.So an n-bit register has a group of n flip-flops and is capable of storingany binary information/number containing n-bits.


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17.Define shift registers.The binary information in a register can be moved from stage to stagewithin the register or into or out of the register upon application ofclock pulses. This type of bit movement or shifting is essential forcertain arithmetic and logic operations used in microprocessors. Thisgives rise to group of registers called shift registers.

18.What are the different types of shift type?There are five types. They are,_Serial In Serial Out Shift Register_Serial In Parallel Out Shift Register_Parallel In Serial Out Shift Register_Parallel In Parallel Out Shift Register_Bi-directional Shift Register

19.Explain the flip-flop excitation tables for RS FF.In RS flip-flop there are four possible transitions from the present state

to thenext state. They are,0 0 transition: This can happen either when R=S=0 or when R=1 andS=0.0 1 transition: This can happen only when S=1 and R=0.1 0 transition: This can happen only when S=0 and R=1.1 1 transition: This can happen either when S=1 and R=0 or S=0 andR=0.

20. Define sequential circuit?

In sequential circuits the output variables dependent not only on thepresent input variables but they also depend up on the past history ofthese input variables.

21.Give the comparison between combinational circuits and sequentialcircuits.Combinational circuits Sequential circuitsMemory unit is not required Memory unity is requiredParallel adder is a combinational circuit Serial adder is a sequentialcircuit

22. What do you mean by present state?The information stored in the memory elements at any given timedefines the present state of the sequential circuit.

23. What do you mean by next state?The present state and the external inputs determine the outputs andthe next state of the sequential circuit.


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24. State the types of sequential circuits?1. Synchronous sequential circuits

2. Asynchronous sequential circuits

25. Define synchronous sequential circuitIn synchronous sequential circuits, signals can affect the memory

elements only at discrete instant of time.

UNIT IV

2 Marks

1.Give the classification of logic familiesBipolar UnipolarSaturated Non Saturated PMOSNMOSCMOSRTL Schottky TTLECL DTLI I L

TTL

2. Which gates are called as the universal gates? What are itsadvantages?

The NAND and NOR gates are called as the universal gates. Thesegates are used to perform any type of logic application.

3.Classify the logic family by operation?The Bipolar logic family is classified intoSaturated logicUnsaturated logic.

The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logicfamily.

The Schottky TTL, and ECL logic comes under the unsaturated logicfamily.

4.State the classifications of FET devices.FET is classified as1. Junction Field Effect Transistor (JFET)


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2. Metal oxide semiconductor family (MOS).

5.Mention the classification of saturated bipolar logic families.The bipolar logic family is classified as follows:

RTL- Resistor Transistor LogicDTL- Diode Transistor logicI2L- Integrated Injection Logic

TTL- Transistor Transistor LogicECL- Emitter Coupled Logic

6. Mention the important characteristics of digital ICs?Fan outPower dissipationPropagation Delay

Noise MarginFan InOperating temperaturePower supply requirements

7. Define Fan-out?Fan out specifies the number of standard loads that the output of thegate can drive with out impairment of its normal operation.

8. Define power dissipation?

Power dissipation is measure of power consumed by the gate whenfully driven by all its inputs.

9. What is propagation delay?Propagation delay is the average transition delay time for the signal topropagate from input to output when the signals change in value. It isexpressed in ns.

10. Define noise margin?It is the maximum noise voltage added to an input signal of a digital

circuit that doesnot cause an undesirable change in the circuit output. It is expressedin volts.

11. Define fan in?

Fan in is the number of inputs connected to the gate without anydegradation in thevoltage level.


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12. What is Operating temperature?All the gates or semiconductor devices are temperature sensitive innature. The temperature in which the performance of the IC is effectiveis called as operating temperature. Operating temperature of the ICvary from 00 C to 700 c.

13.What is High Threshold Logic?Some digital circuits operate in environments, which produce very highnoise signals. For operation in such surroundings there is available atype of DTL gate which possesses a high threshold to noise immunity.

This type of gate is called HTL logic or High Threshold Logic.

14. What are the types of TTL logic?1. Open collector output2. Totem-Pole Output3. Tri-state output.

15. What is depletion mode operation MOS?If the channel is initially doped lightly with p-type impurity aconducting channel exists at zero gate voltage and the device is saidto operate in depletion mode.

16. What is enhancement mode operation of MOS?If the region beneath the gate is left initially uncharged the gate fieldmust induce a channel before current can flow. Thus the gate voltageenhances the channel current and such a device is said to operate inthe enhancement mode.

17. Mention the characteristics of MOS transistor?1. The n- channel MOS conducts when its gate- to- source voltage ispositive.2. The p- channel MOS conducts when its gate- to- source voltage is

negative3. Either type of device is turned of if its gate- to- source voltage iszero.

18. How schottky transistors are formed and state its use?A schottky diode is formed by the combination of metal andsemiconductor. The presence of schottky diode between the base andthe collector prevents the transistor from going into saturation. Theresulting transistor is called as schottky transistor. The use of schottky


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transistor in TTL decreases the propagation delay without a sacrifice ofpower dissipation.

19. List the different versions of TTL1.TTL (Std.TTL) 2.LTTL (Low Power TTL)3.HTTL (High Speed TTL) 4.STTL (Schottky TTL)5.LSTTL (Low power Schottky TTL)

20. Why totem pole outputs cannot be connected together.Totem pole outputs cannot be connected together because such aconnection might produce excessive current and may result in damageto the devices.

21. State advantages and disadvantages of TTLAdv:Easily compatible with other ICs

Low output impedanceDisadv:Wired output capability is possible only with tristate and open collectortypesSpecial circuits in Circuit layout and system design are required.

22. When does the noise margin allow digital circuits to functionproperly.When noise voltages are within the limits of VNA(High State NoiseMargin) and VNK for a particular logic family.

23. What happens to output when a tristate circuit is selected for highimpedance. Output is disconnected from rest of the circuits by internalcircuitry.

24. What is 14000 series.It is the oldest and standard CMOS family. The devices are not pincompatible or electrically compatible with any TTL Series.

25. Explain PROM.

_ PROM (Programmable Read Only Memory)It allows user to store data or program. PROMs use the fuses withmaterial like nichrome and polycrystalline. The user can blow thesefuses by passing around 20 to 50 mA of current for the period 5 to20s.The blowing of fuses is called programming of ROM. The PROMsare one time programmable. Once programmed, the information isstored permanent.

26. Explain EPROM.


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EPROM(Erasable Programmable Read Only Memory)EPROM use MOS circuitry. They store 1s and 0s as a packet of chargein a buried layer of the IC chip. We can erase the stored data in theEPROMs by exposing the chip to ultraviolet light via its quartz windowfor 15 to 20 minutes. It is not possible to erase selective information.

The chip can be reprogrammed.

27. Explain EEPROM.EEPROM(Electrically Erasable Programmable Read Only Memory)EEPROM also use MOS circuitry. Data is stored as charge or no chargeon an insulated layer or an insulated floating gate in the device.EEPROM allows selective erasing at the register level rather thanerasing all the information since the information can be changed byusing electrical signals.

28. What is RAM?Random Access Memory. Read and write operations can be carried out.

29. What is programmable logic array? How it differs from ROM?In some cases the number of dont care conditions is excessive, it ismore economical to use a second type of LSI component called a PLA.A PLA is similar to a ROM in concept; however it does not provide fulldecoding of the variables and does not generates all the minterms asin the ROM.

30.What is mask - programmable?With a mask programmable PLA, the user must submit a PLA programtable to themanufacturer.31. What is field programmable logic array?

The second type of PLA is called a field programmable logic array. Theuser by means of certain recommended procedures can program theEPLA.

32. List the major differences between PLA and PALPLA: PALBoth AND and OR arrays AND arrays areprogrammable OR are programmable and Complexarrays are fixedCostlier than PAL Cheaper andSimpler

33. Define PLD.


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Programmable Logic Devices consist of a large array of AND gates andOR gates that can be programmed to achieve specific logic functions.

34. Give the classification of PLDs.PLDs are classified as PROM(Programmable Read Only Memory),ProgrammableLogic Array(PLA), Programmable Array Logic (PAL), and Generic Array

Logic(GAL)

35. Define PROM.PROM is Programmable Read Only Memory. It consists of a set of fixedAND gatesconnected to a decoder and a programmable OR array.

36. Define PLAPLA is Programmable Logic Array(PLA). The PLA is a PLD that consistsof a programmable AND array and a programmable OR array.

37. Define PALPAL is Programmable Array Logic. PAL consists of a programmable ANDarray and a fixed OR array with output logic.

38. Why was PAL developed ?It is a PLD that was developed to overcome certain disadvantages ofPLA, such as longer delays due to additional fusible links that result

from using two programmable arrays and more circuit complexity.

39. Why the input variables to a PAL are bufferedThe input variables to a PAL are buffered to prevent loading by thelarge number ofAND gate inputs to which available or its complement can beconnected.

40. What does PAL 10L8 specify ?PAL - Programmable Logic Array

10 - Ten inputsL - Active LOW Ouput8 - Eight Outputs

41.Give the comparison between PROM and PLA.PROM PLA1. And array is fixed and OR Both AND and OR arraysarearray is programmable. Programmable.


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2. Cheaper and simple to use. Costliest andcomplex thanPROMS.

The sequential circuits are classified on the basis of timing of theirsignals into twotypes. They are,1)Synchronous sequential circuit.

2)Asynchronous sequential circuit.

2. Define Flip flop.The basic unit for storage is flip flop. A flip-flop maintains its outputstate either at 1or 0 until directed by an input signal to change its state.

3.What are the different types of flip-flop?There are various types of flip flops. Some of them are mentionedbelow they are,

RS flip-flopSR flip-flopD flip-flopJK flip-flopT flip-flop

4.What is the operation of D flip-flop?In D flip-flop during the occurrence of clock pulse if D=1, the output Qis set and ifD=0, the output is reset.

5. What is the operation of JK flip-flop?When K input is low and J input is high the Q output of flip-flop is set.When K input is high and J input is low the Q output of flip-flop is reset.When both the inputs K and J are low the output does not changeWhen both the inputs K and J are high it is possible to set or reset the

flip-flop (ie) the output toggle on the next positive clock edge.

6. What is the operation of T flip-flop?T flip-flop is also known as Toggle flip-flop.When T=0 there is no change in the output.When T=1 the output switch to the complement state (ie) the output

toggles.

7. Define race around condition.


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In JK flip-flop output is fed back to the input. Therefore change in theoutput results change in the input. Due to this in the positive half ofthe clock pulse if both J and K are high then output togglescontinuously. This condition is called race around condition.

8. What is edge-triggered flip-flop?The problem of race around condition can solved by edge triggering

flip flop. The term edge triggering means that the flip-flop changesstate either at the positive edge or negative edge of the clock pulseand it is sensitive to its inputs only at this transition of the clock.

9. What is a master-slave flip-flop?A master-slave flip-flop consists of two flip-flops where one circuitserves as a master and the other as a slave.

10.Define rise time.The time required to change the voltage level from 10% to 90% is

known as rise time(tr).

11.Define fall time.The time required to change the voltage level from 90% to 10% isknown as falltime(tf).

12.Define skew and clock skew.The phase shift between the rectangular clock waveforms is referred toas skew and the time delay between the two clock pulses is called

clock skew.

13.Define setup time.The setup time is the minimum time required to maintain a constantvoltage levels at the excitation inputs of the flip-flop device prior to thetriggering edge of the clock pulse in order for the levels to be reliably

clocked into the flip flop. It is denoted as tsetup.

14. Define hold time.The hold time is the minimum time for which the voltage levels at theexcitation inputs must remain constant after the triggering edge of theclock pulse in order for the levels to be reliably clocked into the flipflop. It is denoted as thold .

15. Define propagation delay.


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A propagation delay is the time required to change the output after theapplic ation of the input.

16.Define registers.A register is a group of flip-flops flip-flop can store one bit information.So an n-bit register has a group of n flip-flops and is capable of storingany binary information/number containing n-bits.

17.Define shift registers.The binary information in a register can be moved from stage to stagewithin the register or into or out of the register upon application ofclock pulses. This type of bit movement or shifting is essential forcertain arithmetic and logic operations used in microprocessors. Thisgives rise to group of registers called shift registers.

16 Marks

1. Draw a dynamic ram cell and explain its operation. Compare itssimplicity that of NMOS static RAM cell, by way of diagram andoperation. (16)

2. Discuss on the concept of working and applications of followingmemories.i) ROMii) EPROM

iii) PLA. (16)

3. Explain the basic structure of 256 x 4 static RAM with neat sketch.(16)4. i) A combinational circuit is defined by the functions. (8)F1 (a, b, c) = _ (3, 5, 6, 7)F2 (a, b, c) = _ (0, 2, 4, 7) implement the circuit with a PLA.ii). Implement the given function using PAL and PLA.F1 = _ (0, 1, 2, 4, 6, 7)F2 = _ (1, 3, 5, 7)

F3= _ (0, 2, 3, 6) (8)

5. Write short notes on semiconductor memories. (16)

6. Explain the characteristics and implementation of the followingdigital logic families.(i) TTL(ii) CMOS (16)


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UNIT-V

2 Marks

1. Write some of the Low Level Language and High Level Language?Low Level Languages-ABEL, CUPL,PALASM

High Level Languages-VHDL, VERILOG

2. Define Schematic Entry?The schematic shows how all the components are connected together ,the connectivity of an ASIC. This type of design entry process is calledSchematic entry.

3. Define Hierarchical design?Hierarchical design reduces the size and complexity of a schematic. Toclarify the relationship between different levels of Hierarcy, we say that

a sub schematic is child of the parent schematic.4. Write one example for combinational logic in verilog

Two input AND gateModule And-Always(X, Y, Z);Input X, Y;Output Z;Reg Z;Always @(X or Y)Z


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3b110:out=i[6];3b111:out=i[7];Default : $ display (invalid control signal);End caseEndEnd

6. Write the program for adder inVHDLLibrary IEEE;Use IEEE.NUMARIC-STD.all;Use IEEE.STD-LOGIC-1164.all;Entity adder-1 isPort(A,B:in UNSIGNED(3 down to 0);C:out UNSIGNED(4 down to 0);End adder-1;Architecture synthesis -1 for adder-1 isBegin c


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It can be also used to check the timing performance of an ASIC. In agate level simulation a logic gate or logic cell is treated as a black boxmodeled by a function whose variable are single inputs. The functionalso mode the delay through the logic cell setting all the delay value tounit value is the equalent of functional simulation.

10. Define transistor-level simulation

The most accurate but also the most complex & time consuming formof simulation is transistor level simulation.

16 Marks

1. Write an VHDL program to implement full adder and full subs tractorusing data flow model.2. Write an VHDL program to implement decoder and encoder using

structural model.3. Write an Verilog program to implement clocked J-K flip flop usingbehavioral model.4. Write an VHDL program to implement D-flip flop using structuralmodel.5. Write an Verilog program for synchronous counter using behavioralmodel.

eee digital question bank

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