eee 1106 014 low voltage highly linear cmos up conversion mixer

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Canadian Journal on Electrical and Electronics Engineering Vol. 2, No. 6, June 2011

176

AbstractA low voltage highly linear CMOS single IF based upconversion mixer is presented which converts the input baseband

signal to an output of 1.7-1.8 GHz RF signal. Low voltage

architectures based on the switched mode transconductors and

folded cascode structures are used in the IF and RF mixers that help

to achieve low voltage and low power operation. A harmonic

suppression technique is used in the IF mixer and a current steering

approach is utilized to transfer the intermediate signal between IF

and RF stages in order to increase the overall linearity. Full

transistor level simulation results for an AMS 0.35 m CMOS

process reveal high linearity of the proposed mixer after a FOM-based comparison at 1 V supply voltage while consumes only 5.35

mW power. The proposed mixer has reached to a maximum

conversion gain of 4.5 dB at the desired output frequency and its

linearity performance indexes consisting of IIP3, P-1dB, and IIP2

are 10.51, -1.05, and 85.6 dBm, respectively.

Keywords Highly linear, up conversion mixer, low power,

low voltage, harmonic suppression.

I.INTRODUCTIONIn recent years, demand for single chip low power and low

voltage transceivers has been increased, tremendously. Many

types of portable communication devices like cellular phones

need high performance and low cost RF circuits and hence,

single chip integrating and low power consuming solutions

draw great attention due to decrease the cost and prolong the

battery life.

A conventional Gilbert mixer is the most popular circuit and

widely used in transceivers due to its good port to port

isolation. However, it is not suitable for low voltage

application, as it requires a stack of three levels of transistors

working in saturation region and a load stage, and hence when

the mixer reduces its power supply voltage, its performance

including conversion gain and especially linearity will be

degraded. On the other hand in such a mixer, the localoscillator (LO) switches are hard driven to improve linearity

and optimize noise figure. As a result, the mixing process

produces several unwanted harmonics that must be filtered,

which degrades the single chip integration.

Alireza Saberkari is with the Department of Electrical Engineering,

University of Guilan, Rasht, Iran. (e-mail: [email protected]).

Shahriar B. Shokouhi is with the Department of Electrical Engineering,

Iran University of Science & Technology, Tehran, Iran.

By using more LO phases and summing them with the right

weighting, it is possible to approximate a sinusoidal switching

that contains less unwanted harmonics [1]-[4]. But the sub-

mixers used in [1] are based on the conventional Gilbert cell

that need high power supply and high LO power to drive the

LO switching gates in order to increase the linearity and

harmonic suppression. Also total capacitive loading at the LO

ports of the sub-mixers are not equal due to the scaling of

switching transistors in one of the sub-mixers that can lead to

phase error. In this paper a low voltage highly linear CMOS

single IF based up conversion mixer exhibiting highperformance after a FOM-based comparison is presented.

II. PROPOSED MIXER STRUCTURE AND DESIGN CRITERIAThe transistor level schematic of the proposed mixer is

shown in Fig. 1. The baseband-to-IF stage is a harmonic

suppression mixer and consists of three switched mode

transconductor sub-mixers [5]. The sources of transconductor

transistors (M1-M12) are switched from on-chip inverters

(M13-M36) which work as LO buffers and provide square-

wave LO signals. Three LO signals with phases of o45 , 0,

and o45+ are used to drive the inverters as shown in Fig. 2.

The transconductance stages of these three sub-mixers are

weighted as 1: 2 :1 and switched according to the LO phases

in order to suppress the 3rd

and 5th

order harmonics. The

current output of each transconductance stage is multiplied and

then added together and finally injected into the active load.

This structure helps to reduce the needed LO power to drive

the switching inverters and compatible with low supply

voltage. Since the switching transistors of inverters have the

same aspect ratio, there is no unbalancing at the LO ports that

leads to phase error reduction. Also, generated noise by the

LO switches is in the form of common mode noise and

therefore it will be rejected at the differential output and the

noise level can be decreased. Two LO buffers for each sub-

mixer with gradual increase in size help to achieve lower

power dissipation and loading effect on the LO generators by

the switches. It also increases the overall linearity by

decreasing the on-resistance of the switches.

Low Voltage Highly Linear CMOS Up

Conversion Mixer

Alireza Saberkari and Shahriar B. Shokouhi


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177

Fig. 1. Schematic of the proposed mixer.

Fig. 2. Three LO signals used to generate the effective LO.

The IF-to-RF stage is performed using the structure of

folded cascode. Transistors M43-M46 form the LO switching

stage and M47 and M48 supply dc biasing current of the

switching pairs. To make M43-M46 as ideal switches, the

transistors are biased in the saturation region close to the

triode one. The inductive loads of the mixer L 1 resonate at the

desired output frequency with the parasitic capacitances at the

output node and hence reject the image signals. They also

improve the noise level of the mixer due to their lower noise

contribution. The inductor L 2 has been used to tune out the

parasitic tail capacitance between the transconductance and

LO switching stages and increase the mixer linearity [6]. The

use of folded cascode helps to split the supply voltage and

provides low voltage operation. Also, it is possible to separate


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the dc biasing current of transconductance and LO switching

stages. As a result, by limiting the dc current of switching

pairs, their noise level can be greatly decreased. In addition, by

injecting more dc current into the transconductance stage, the

conversion gain and dc current mismatch of input differential

transistors and hence the IIP2 can be improved.

If the LO switching stage of a mixer is assumed ideal,

overall linearity performance is dominated by its

transconductance stage. A current steering approach based oncurrent mirror [7] has been used in the proposed mixer instead

of the conventional voltage mode method in order to transfer

the intermediate signal between IF and RF stages to increase

the linearity. The diode connected transistors of baseband-to-

IF stage (M37, M38) which act as active loads, with the input

stage transistors of IF-to-RF stage (M41, M42) form a current

mirror and steer the current mode intermediate signal. By

choosing the appropriate scaling factor for these transistors, it

is possible to set the gain of mixer. One issue about the current

mirror is that its operating frequency is reversely proportional

to its scaling factor and hence it is not possible to increase the

scaling factor at RF frequency. But in this case, as the currentmirror works at IF frequency, it is not a bottleneck. Another

issue is that if the bias current of the first stage of mixer is

amplified by the current mirror, noise level of the switches in

the second stage and also the power consumption will be

increased. So, transistors M39 and M40 are used to bypass the

bias current of the first stage.

The overall conversion gain of the mixer is as follow:

LmCG RNGA 2

4

= (1)

where N is the scaling factor of the current mirror, LR is the

output load resistance, and mG is the total effectivetransconductance of the baseband-to-IF stage which is equal to

sum of the effective transconductance of three sub-mixers.

We assume that the three LO signals with phases of o45 ,

0, and o45+ used in the IF stage have frequency of IFLO,

and transient switching time of sw , like Fig. 3. According to

the Fourier series, the effective transconductance of each sub-

mixer and the total mG can be written as:

=

=

1

,,2

,

00

)cos()]2

sin()2

[sin(1*

8)(

k

IFLOswIFLO

swIFLO

meff

tkkkk

gtg

(2)

)8

(2

1)(

,01

IFLOeffeff

Ttgtg = (3)

)8

(2

1)(

,02

IFLOeffeff

Ttgtg += (4)

Fig. 3. LO signal with rise and fall time of sw .

where IFLOT , is the period of LO signals and 0mg is the

maximum range of each transconductance stage.

The total effective transconductance of the baseband-to-IF

stage, mG , which is equal to sum of the effective

transconductance of three sub-mixers, is as follows;

)()()( 210 tgtgtgG effeffeffm ++= (5)

...]7cos)2

7sin(

49

1cos)

2

1[sin(

16,,,,

,

0+= tt

gIFLOswIFLOIFLOswIFLO

swIFLO

m

As can be seen, the 7th

order harmonic is the main unwanted

one in mG and hence at the output of mixer. Substituting (5) in(1), the conversion gain due to the main harmonic is equal to:

))sin(

(32

,

,

3

0

swIFLO

swIFLOLmCG

f

fRNgA

= (6)

III. CIRCUIT CHARACTERIZATIONTo verify the discussion, the proposed mixer is simulated by

Cadence in AMS 0.35 m CMOS process at 1 V supply

voltage and the results have been compared with the most

recently works. The input baseband signal is up converted to

the 1.7-1.8 GHz RF signal and the chosen IF frequency is 300-

400 MHz according to the DCS1800 standard.

As shown in Fig. 4, the proposed mixer has a maximum

conversion gain of 4.5 dB at the desired output frequency.

Whereas power amplifiers in transmitters are responsible for

increasing the signal gain and power, the measured conversion

gain is suitable for the up conversion mixer in order to have a

trade off between conversion gain and linearity.

For P-1dB and IIP3 measurement, two baseband tones with

frequency spacing of 100 KHz are applied. The IIP3 and P-

1dB are 10.51 and -1.05 dBm, respectively as shown in Fig. 5.

In addition, the mixer has reached to a suitable IIP2 of 85.6

dBm.

Table I provides comparison between performance of the

proposed mixer and the most recently published works [6],[8]-[10]. A figure of merit is adopted here as written in Eq. (7),

to compare the linearity of different mixers by evaluating the

effect of the input third order intercept point IIP3 to the dc

power dissipation.

FOM=10log(IIP 3 (mW)/P dc (mW)) (7)


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Fig. 4. Conversion gain of the mixer versus frequency. Fig. 5. IIP3 and 1-dB compression point of the mixer.

TABLE I

PERFORMANCE COMPARISON OF THE PROPOSED DESIGN AND RECENTLY PUBLISHED WORKS.

Reference [10] [9] [8] [6] This work

Technology (m) 0.18 0.18 0.18 0.18 0.35

Supply Voltage (V) 1 1 1.8 1 1

Frequency (GHz) 5.2 2.4 2.4 3-5 1.7-1.8

Power Dissipation (mW) 3.8 3.2 4.25 4.22 5.35

Conversion Gain (dB) 4.5 11.9 19 5.8 4.5

IIP3 (dBm) -6 -3 -9 -1.31 10.51

P-1dB (dBm) -16 -15 N.A. -12 -1.05

Noise Figure (dB) 13 13.9 11 9.3 10

FOM -11.8 -8.05 -15.28 -7.56 3.23

A higher FOM implies better linearity for mixer. In the

proposed mixer, linearity and power dissipation are improved

by using the harmonic suppression, current steering approach

and also low voltage structures and as shown in Table I, FOM

of the proposed mixer is higher than other reported mixers

while consumes only 5.35 mW power.

IV. CONCLUSIONIn this paper, a low voltage highly linear CMOS single IF

based up conversion mixer has been presented that convertsthe input baseband signal to an output of 1.7-1.8 GHz RF one.

Low voltage structures and harmonic suppression technique

were used in the IF and RF stages, and also a current steering

approach was utilized to transfer the intermediate signal

between IF and RF stages instead of the conventional voltage

mode in order to increase the overall linearity. The proposed

mixer was designed and characterized in AMS 0.35 m

CMOS process at 1 V supply voltage and the results indicated

high linearity of the proposed mixer after a FOM-based

comparison and the overall cell consumes 5.35 mW power.

The proposed mixer has reached to a maximum conversion

gain of 4.5 dB at the desired output frequency and its linearity

performance indexes including IIP3, P-1dB, and IIP2 are

10.51, -1.05, and 85.6 dBm, respectively.

ACKNOWLEDGMENT

The authors would like to thank the Universitat Politcnica

de Catalunya and specially thank Associate Professor E.

Alarcn for his technical support.

REFERENCES

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Otsuka, S. Dedieu, L. Tee, K. C. Tsai, C. W. Lee, and P. R.

Gray, A 1.75 GHz Highly Integrated Narrow-Band CMOS

Transmitter with Harmonic-Rejection Mixers, IEEE J. Solid-

State Circuits, vol. 36, no. 12, pp. 2003-2015, Dec. 2001.

[2] N. A. Moseley, E. A. M. Klumperink, and B. Nauta,Experimental Verification of a Harmonic-RejectionMixing Concept Using Blind Interference Canceling,


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Proc. European Conf. Wireless Technology, Oct. 2008,pp. 210-213.

[3] N. A. Moseley, E. A. M. Klumperink, and B. Nauta, ATwo-Stage Approach to Harmonic Rejection MixingUsing Blind Interference Cancellation, IEEE Trans.Circuits Syst. II, vol. 55, no. 10, pp. 966-970, Oct. 2008.

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[5] E. A. M. Klumperink, S. M. Louwsma, G. J. M. Wienk, and B.

Nauta, A CMOS Switched Transconductor Mixer, IEEE J.

Solid-State Circuits, vol. 39, no. 8, pp. 1231-1240, Aug. 2004.

[6] P. Renjing, Y. K. Seng, and Z. Yuanjin, A Low-Voltage Low-

Power High Linear and Wide-Band Mixer, Proc. IEEE Int.

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[7] K. B. Ashby and R. Pa, Mixer with Current Mirror Load, U.S.

Patent 6029060, Feb. 2000.

[8] Kwon and K. Lee, An Integrated Low Power Highly Linear 2.4

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BIOGRAPHIES

Alireza Saberkari received the B.Sc. degree in Electrical

Engineering from the University of Guilan, Rasht, Iran, in

2002 and the M.Sc. and Ph.D. degrees both in Electrical

Engineering from the Iran University of Science and

Technology (IUST), Tehran, Iran, in 2004 and 2010,

respectively. Since 2010, he has been with the Department

of Electrical Engineering at the University of Guilan as an

Assistant Professor. From September 2008 to August 2009,

he was with the group of Energy Processing Integrated Circuits, Department

of Electronic Engineering, Technical University of Catalunya (UPC),

Barcelona, Spain, as a Visiting Scholar. His fields of interest include the areas

of Analog and Mixed-Signal Microelectronics with particular interest in

CMOS Mixers, RF Power Amplifiers, Linear Regulators, Current-Mode

Circuit Design, Low-Power and Low-Voltage Integrated Circuits, and Vision

Chips.

Shahriar B. Shokouhi is currently an Assistant Professor in

Electrical Engineering at the Iran University of Science and

Technology, Tehran, Iran. He earned his Ph.D. degree in

Electrical Engineering in 1999 from the University of Bath inEngland. His fields of interest are Machine Vision and Image

Processing Algorithms, Design and Implementing Processors

and Vision Chips, Integrated Mixed Mode Circuits, 3-D

Vision and Range Finding Techniques, Optoelectronic Integrated Circuits,

Navigation and Tracking, IT, Security and Networking.

eee 1106 014 low voltage highly linear cmos up conversion mixer

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