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EECS 244:Introduction to CAD
and the Course
Prof. Kurt KeutzerEECS
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Lecture Overview
Introduction to Kurt … and othersWhere does CAD fit in?Brief overview of CADGoals of CourseProject
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Introduction to Kurt
Professor in EECSB. S. in mathematics from Maharishi International University 1978 (yes, I’m serious)M. S. in Ph.D. in CS from Indiana University 1984AT&T Bell Labs, Area 11 1984-1991
Developed a number of successful (internally) tools for hardware developers
Plaid – Programmable Logic AID – used to create racks of switching system hardwareDAGON – worked with Chuck Stroud and Mark Vancura to create a logic synthesis system for Bell Labs – dozens of IC’s developed with the system
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Introduction to KurtSynopsys, Inc. 1991-1998 (now 14th largest software company)
From Member of Research Staff of $30M 200 person company to SVP/CTO of $600M 3000 person company in 7 yearsAs CTO
oversaw and reviewed technology of over 25 software products accounting for $600M in revenueIdentified new technology and market opportunitiesInitiated and participated in a dozen corporate acquisitionsAs Manager=>Director=>VP=>SVP or research
Initiated a number of product ideas and two complete products:FPGA Express – FPGA synthesis software – brought to ``product roll-out’’Formality – market leader in formal verification of circuits –
UC Berkeley 1998-presentProfessor of EECS
As teacher – EECS 244 (Intro to CAD), CS169 (Software Engineering)Associate Director – Gigascale Systems Research Center 1998-2001As a research advisor
MESCAL: modern embedded systems, compilers, architectures, and languages – 8 students
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Introduction to KurtAs an entrepreneur:
Cadabra (acquired by Numerical Technology 2000, acquired by Synopsys 2003) – investor/Corporate BoardEverest Design (acquired SNPS, 1999) – investor/TABRight Track CAD (acquired by Altera, 2000) – angel investor/TAB0-in Design Automation – Series A investor 1998/TAB -acquired by Mentor Graphics 8/2004Tensilica, Inc (upside top 100), Series A investor 1998/TABCatalytic Compilers – angel investor/TAB – founded Fall 2002, $6M in funding from NEA July 2003Stretch Inc. - Series A investor/TAB – founded 2002, $15M in funding from Worldview, July 2003
As a consultant: Cadence (2001-present) Synopsys (1998 – 2000) Ammocore, C-Cube Microsystems (IPO), CoWare, Hier Design (acquired by Xilinx) Reshape, a number of venture capital firms
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Please introduce yourselves …!
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Lecture Overview
Introduction to KurtWhere does CAD fit in?Brief overview of CADGoals of CourseProject
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The World and Electronic Systems
The world is increasingly dependent on electronic systemsThe “first world” is entirely dependent on electronic systems
World economy $33.4 trillion http://www.imf.org/Electronic systems $1 trillion Sources: Gartner Group/Dataquest, Rose Associates; January, 2000 http://www.facsnet.org/tools/sci_tech/tech/biz/
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Electronic Systems and Semiconductors
Electronic systems are entirely dependent on semiconductor componentsElectronic systems $1 trillion Semiconductor industry $160 billion Sources: Gartner Group/Dataquest, Rose Associates; January, 2000http://www.facsnet.org/tools/sci_tech/tech/biz/
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Where does CAD fit in?
Silicon FoundriesIntegrated CircuitComputer-aided
Design
Real WorldElectronic Systems
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Where does CAD fit in? Everywhere?
Silicon Foundries
Semiconductor Industry
Designer usingCAD
Real World
Speech processingSignal processingPerformance analysis
System modelingand synthesis
Formal verificationLogic synthesisPlace and routeCircuit simulation
Device simulationProcess modeling
Electronic Systems
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Where does CAD fit in? The tools
Silicon Foundries
Semiconductor Industry
Designer usingCAD
Real World
MatlabLabview
SystemCMetropolisPtolemy
Design compilerPhysical compilerApollo
BSIMSpicePisces
Electronic Systems
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Electronic Systems, Semiconductors and CAD
Electronic systems and semiconductor components are entirely dependent on computer-aided design/electronic design automation tools
Electronic systems $1 trillion Semiconductor industry $160BEDA industry $3BSources: Gartner Group/Dataquest, Rose Associates; January, 2000http://www.facsnet.org/tools/sci_tech/tech/biz/
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Another look- Industry Sector – bottom up %
By Revenue (TTM)
Capital Goods
4%
Healthcare 5%
Services 22%
Technology 9%
Conglomerates 4%
Consumer Cyclical
11%
Consumer/Non-
Cyclical 6%
Energy 11%Financial
15%
Basic Materials
5%Utilities
6%
Transportation 2%
Entire Technology Sector
$1290B
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Another look - Technology Sector – bottom up
TTM Revenue Breakdown
Software & Programming,
127,737
Semis, 147,624
Sci & Tech Instr, 31,610
Office Eqpt, 49,305
Electronic Instr. &
Controls, 144,429 Computer
Storage Devices, 27,023
Computer Services, 192,348
Computer Peripherals,
126,283
Computer Networks,
15,805
Computer Hardware, 201,226
Comm Eqpt, 226,929
Multex Investor – bottom up TTM
Entire Technology Sector
$1290B
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Software Market Segmentation
Software Market (not incl services)
$100.9B
Applica tio n So ftware , $ 74.11B
Healthcare Info rmatio n
Services , $ 3.41B
Info rmatio n & Delive ry
Services , $ 59.72B
Bus ines s So ftware & Services , $ 55.75B
Multimedia & Graphics So ftware ,
$ 8.18B
Technical & Sys tem
So ftware , $ 10.44B
Security So ftware & Services , $ 2.83B
Software & Services Market
$229.8B
Application Software, $74.11B
Multimedia & Graphics Software, $8.18B
Security Software,
$2.83B
Technical & System
Software, $10.44B
Business Software,
$5.33B
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Largest Software Companies - 8/2003
$3.92$16.1$13.9NM(28.4)$1112$3307VRSN20. Verisign
$15.2$45.6$39.852.715.1$444$3398MERQ19. MercuryInteractive
$8.65$15.6$13.050.86.2$1136$3543CDN18. Cadence Design
$12.6$22.2$16.216.658.2$425$3974CHKP17. Check Point
Software
$5.33$12.2$9.30NM(8.2)$1418$4595SEBL16. Siebel
$5.85$27.3$21.340.38.1$1427$4598DOX15. AmdocsLtd
$31.8$65.5$65.0NM(16.2)$1106$5051SNPS14. Synopsys, Inc
LowHighPriceP/EMargRevMarket TickerCorporation
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The Inverted Pyramid
Electronic systems > $1Trillion
Semiconductor > $160B
CAD $3B
World economy > $33 Trillion
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What does it all mean?
Computer-aided design (CAD)/Electronic design automation (EDA) enables electronic systems, and electronic systems enable the world economyCAD/EDA software companies are big players in the world software market, but modestly sized relative to the industries they serve
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Lecture Overview
Introduction to KurtWhere does CAD fit in?Brief overview of CADGoals of CourseProject
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Driving CAD: Moore’s Law
1
10
100
1K
10K
100K
1M
10M
1975 1980 1985 1990 1995
Transistors
10x/6 years10x/6 years
808668000
6802080386
80486
68040
PentiumPentium Pro
PPC601
PPC603
80804004
MIPS R4000
Microprocessors
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NRTS: Chip Frequency (Ghz)
0
1.0
3.0
5.0
7.0
9.0
1997 1999 2001 2003 2006 2009 2012
10.0
On-chip, global clock, high performance
On-chip, local clock, high-performance
Clock Speed GHz.
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Role of CAD: Helping humans cope
Transistors
Processor ComplexityAvg. Human IQ
1
10
100
1K
10K
100K
1M
10M
1975 1980 1985 1990 1995
808668000
6802080386
80486
68040
PentiumPentium Pro
PPC601
PPC603
80804004
MIPS R4000
50
80
120
140
160
180
100
IntelligenceQuotient
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How does Moore’s Law drive CAD?
Because the capability of integrated circuit technology scales so rapidly, traditionally we have had:
Exponentially more devices every process generationExponential increases in speed every process generation
Will these trends continue?
After a few process generations we need to do something fundamentally differentCAD is not a field you can relax in!
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Evolution of IC Design
Effort
(EDA tools effort)
Results
(Design Productivity)
a
b
s
q0
1
d
clk
1978
1985
1992
1999
Transistor entry
Schematic Entry
RTL Synthesis
What’s next?
McKinsey S-Curve
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Evolution of the EDA Industry
Effort
(EDA tools effort)
Results
(Design Productivity)
a
b
s
q0
1
d
clk
1978
1985
1992
1999
Transistor entry - Calma, Computervision
Schematic Entry - Daisy, Mentor, Valid
Synthesis - Cadence, Synopsys
What’s next?
McKinsey S-Curve
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Transistor Era
Key tools:Transistor-level layout – e.g. Calma workstationTransistor-level simulation – e.g. SpiceBonus: transistor-level compaction – e.g. Cabbage
Size of circuits: 10’s of transistors to few thousandKey abstractions and technologies:
Transistor-level modelingLogical gates- NAND, NOR, FF and cell librariesCompaction
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Gate-level Schematic Era
Key tools:gate-level layout editor –Daisy, Mentor, valid workstationGate-level simulator Automated place and route
Size of circuits: 3,000 – 35,000 gates (12,000 to 140,000 transistors)Key abstractions and technologies:
Logic-level simulationCell-based place and routeStatic-timing analysis
a
b c_out
sumAdd_half_0_delay
a
b c_out
sumAdd_half_0_delay
(a⊕ b)⊕ c_in
(a + b) c_in + ab
(a⊕ b) c_ina
b
c_in sum
c_out
ab
(a⊕b)
Add_full_0_delay
w1
w2
w3
FAab
c_in
sumc_out
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Gate level modelsBorder between transistor domain (analog) and digital domainDigital gate level models introduced to speed up digital simulation.Gate level model contains:
Logic behaviorDelays depending on: operating conditions, process, loading, signal slew ratesSetup and hold timing violation checks
Gate level model parameters extracted from transistor level simulations and characterization of real gates.
J. Christiansen,CERN - EP/MIC
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Building a 4-Bit Ripple Adder
4-bit Ripple Adder
FA
Hall AdderHalf Adder
FAFAFA
XOR AND
OR
Ciletti, M. D.
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RTL Synthesis Era
Key tools:Hardware-description language simulator – Verilog, VHDLLogic synthesis tool - SynopsysAutomated place and route –Cadence, Avant!, Magma
Size of circuits: 35,000 gates to …? Key abstractions and technologies:
HDL simulationLogic synthesisCell-based place and routeStatic-timing analysisAutomatic-test pattern generation
module Half_adder (Sum, C_out, A, B);output Sum, C_out;input A, B;
xor M1 (Sum, A, B); and M2 (C_out, A, B);
endmodule
module Full_Adder (sum, c_out, a, b, c_in);output sum, c_out;input a, b, c_in;wire w1, w2, w3;Half_adder M1 (w1, w2, a, b);Half_adder M2 (sum, w3, w2, c_in);or M3 (c_out, w2, w3);
endmodule
module Full_Adder_4 (sum, c_out, a, b, c_in);output [3:0]sum;output c_out;input [3:0] a, b;input c_in;wire c_in2, c_in3, c_in4;Full_adder M1 (sum[0], c_in2, a[0], b[0], c_in);Full_adder M2 (sum[1], c_in3, a[1], b[1], c_in2);Full_adder M3 (sum[2], c_in4, a[2], b[2], c_in3);Full_adder M4 (sum[3], c_out, a[3], b[3], c_in4);
endmodule
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RTL Synthesis Era
a
b c_out
sumAdd_half_0_delay
a
b c_out
sumAdd_half_0_delay
(a⊕ b)⊕ c_in
(a + b) c_in + ab
(a⊕ b) c_ina
b
c_in sum
c_out
ab
(a⊕b)
Add_full_0_delay
w1
w2
w3
FAab
c_in
sumc_out
module Half_adder (Sum, C_out, A, B);output Sum, C_out;input A, B;
xor M1 (Sum, A, B); and M2 (C_out, A, B);
endmodule
module Full_Adder (sum, c_out, a, b, c_in);output sum, c_out;input a, b, c_in;wire w1, w2, w3;Half_adder M1 (w1, w2, a, b);Half_adder M2 (sum, w3, w2, c_in);or M3 (c_out, w2, w3);
endmodule
module Full_Adder_4 (sum, c_out, a, b, c_in);output [3:0]sum;output c_out;input [3:0] a, b;input c_in;wire c_in2, c_in3, c_in4;Full_adder M1 (sum[0], c_in2, a[0], b[0], c_in);Full_adder M2 (sum[1], c_in3, a[1], b[1], c_in2);Full_adder M3 (sum[2], c_in4, a[2], b[2], c_in3);Full_adder M4 (sum[3], c_out, a[3], b[3], c_in4);
endmodule
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What’s after RTL synthesis?
Effort
(EDA tools effort)
Results
(Design Productivity)
a
b
s
q0
1
d
clk
1978
1985
1992
1999
Transistor entry
Schematic Entry
RTL Synthesis
What’s next?
McKinsey S-Curve
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DOMAIN SPECIFIC
RTL
GATE
TRANSISTOR
BEHAVIORAL
Design Productivity by Approach
a
b
s
q0
1
d
clk
GATES/WEEK(Dataquest)
100 - 200
1K - 2K
2K - 10K
8K - 12K
10 - 20
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To Design, Implement, Verify 10M transistors
a
b
s
q0
1
d
clk
62.5
125
625
6250
62,500
Power
Delay
Area
Beh
RTL
Implementations here are often not good enough
Because implementationshere are inferior/ unpredictable
Staff Months
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Level of Acceptance of SynthesisTechniques
Source: A. DeGeus
Speed ofDesigner
Expert designer
Behavioral Synthesis
Acceptance curve
Quality of Design
Sequential Synthesis
Combinational Synthesis
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Current Practice: HDL at RTL Level
module foobar (q,clk,s,a,b);
input clk, s, a, b;
output q; reg q; reg d;
always @(a or b or s) // mux
begin
if( !s )
d = a;
else if( s )
d = b;
else
d = 'bx;
end // always @ (a or b or s)
always @(clk) // latch
begin
if( clk == 1 )
q = d;
else if( clk !== 0 )
q = 'bx;
end // always @ (clk)
endmodule
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RTL Synthesis Flow
RTLSynthesis
HDL
netlist
logicoptimization
netlist
Library/modulegenerators
physicaldesign
layout
HDLsimulation
module Full_Adder_4 (sum, c_out, a, b, c_in);output [3:0]sum;output c_out;input [3:0] a, b;input c_in;wire c_in2, c_in3, c_in4;Full_adder M1 (sum[0], c_in2, a[0], b[0], c_in);Full_adder M2 (sum[1], c_in3, a[1], b[1], c_in2);Full_adder M3 (sum[2], c_in4, a[2], b[2], c_in3);Full_adder M4 (sum[3], c_out, a[3], b[3], c_in4);
endmodule
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Cover All Aspects of the Design Process
Design : specify and enter the design intent
Implement:refine the design through all phases
Verify:verify the correctness of design and implementation
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Lecture Overview
Introduction to KurtWhere does CAD fit in?Brief overview of CADGoals of CourseProject
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Goals of CourseHelp to develop the core competences of a CAD engineer
Software expertiseAlgorithmic facilityDomain expertise in ic design
Communicate the essence of the current IC design flow in a semesterGoal: ``If Avanti, Cadence, and Synopsys employees were all abducted by aliens, their software could be recreated by this class.’’
Prepare you for performing publishable research – aim high, a real publication!
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Something for EveryoneProcessing, Devices students – understand the tool flow, examine ways of bridging the gap between processing, design, and CADCircuits students – understand how the tools that you will be using for the rest of your life workCAD students – give you foundation material for the field, prepare you for preliminary examinationsTheory types – understand how algorithms are applied in this algorithm-rich area
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Approach of the CourseEach week
Examine a portion of the IC design flowIdentify one or more key problemsFormulate the problem mathematicallySolve the problem, examining trade-offs between
The computational efficiency of the algorithmsThe quality/optimality of the result
Look at contemporary practiceSee how close the classroom work approaches industrial practice
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Course logistics
EECS 244
Cory 521, Monday, Wednesday 1:00 – 2:30 PM
Prof. Kurt Keutzer, Cory 566, Office hour: Wednesday 2:30 – 3:30, or by appointment
Exam 1: 30%
Exam 2: 30%
Final project: 40% (20% general content, 10% content in presentation, 10% content in written report)
No TA for course – still working out web pages, pdf etc.
Syllabus, Web page: up soon
The course material will not be hard for you – but the project may be …
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Lecture Overview
Introduction to KurtWhere does CAD fit in?Brief overview of CADGoals of CourseProject
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The Purpose of the Project
Your first couple years of graduate school are about making the transition from
Excellent course/test taker creative researcherSolitary student Active team memberAssimilating well defined information pursuing open questions
The project portion of the course is to help you make this transition
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Project Outline
MotivationProblem statementPrior workInvestigative approachResultsSummaryConclusionsFuture Work
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How Conducted
Research will be conducted in groups of 2-3Individual projects highly discouragedResearch may be coordinated with other class projects: EECS249, EECS290N etc.Research will culminate in a:
Powerpoint presentation/demoWritten report
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Tips for a Great Project
Use your skill set
Circuits, devices, processing, software development, system-level applications
Great idea:
Topical – e.g. system level, deep submicron effects, power
Tractable – can make an impact in a semester, have all the software, examples, data files that you need
Get started early
Get mentorship (senior grad students, post-docs, prof of course)
Follow deadlines
Formulate the problem clearly
Formulate your results clearly
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Some Successful 244 Projects``Getting to the Bottom of Deep Submicron’’, D. Sylvester, K. Keutzer, In Proceedings of the International Conference on Computer-Aided Design, November, 1998, pp. 203-211.``Towards True Crosstalk Noise Analysis’’, P. Chen, K. Keutzer, In Proceedings of the International Conference on Computer-Aided Design, November, 1999, pp. 132-137.``Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-speed Digital Circuits’’ M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, In Proceedings of the International Conference on Computer-Aided Design, November, 2000, pp. 62-67.`` Bus Encoding to Prevent Crosstalk Delay ‘’, B. Victor, K. Keutzer, Proceedings of the International Conference on Computer-Aided Design, November, 2001.“Constraint Driven Communication Synthesis”, A. Pinto, L. Carloni, A. Sangiovanni-Vincentelli, DAC 2002“Multi-Domain Clock Skew Scheduling”, Kaushik Ravindran, Andreas Kuehlmann, Ellen Sentovich, ICCAD 2003.
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A System Level Project“Constraint Driven Communication Synthesis”, A. Pinto, L. Carloni, A. Sangiovanni-Vincentelli, DAC 2002
Problem: Addresses the design of the communication architecture of a complex system from a library of pre-defined Intellectual Property (IP) components. The key communication parameters that govern all thepoint-to-point interactions among system modules are captured as a set of arc constraints in the communication constraint graph. Similarly, the communication features offered by each of the components available in the IP communication library are captured as a set of feature resources together with its cost figures.
Solution:Each communication architecture that can be built using the available components while satisfying all constraints is implicitly considered (as an implementation graph matching the constraint graph) to derive the optimum design solution with respect to the desired cost figure. The corresponding constrained optimization problem is efficiently solved.
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A Chip-Level Project
“Bus Encoding to Prevent Crosstalk Delay”, B. Victor, K. Keutzer.
Problem: Delay in global wires is a large factor in overall circuit performanceCapacitive coupling (cross-talk) between wires may greatly increase this delay
Solution:Old solutions: place shielding wires between signal wires
Large (2X) area penaltyProposed solution: use data encoding to eliminate coupling between neighboring bus lines
Smaller (1.25X) area penalty
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A Circuit Level Project “Getting to the Bottom of Deep Submicron’’, D. Sylvester, K. Keutzer
Problem:Total chip wiring length increase dramaticallyIt is claimed that wire delay contribution becomes dominant Traditional design flows (as will see) treat wire contribution as something secondaryIt is claimed that traditional design flows thus will fail in deep sub-micron
Solution:Need to perform careful analysis of local and global interconnectIf design is done on blocks of 50K-100K gates, traditional flows will work
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A Transistor and Process Level Project“Impact of […] Variability on Performance of High-speed Digital Circuits’’ M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, ICCAD 2000
Problem:Chip performance depends on path delay distribution and on critical path valuesManufacturing of advanced technologies inevitably creates large variations in properties of transistorsNeglecting this variability and uncertainty leads to under-performing and malfunctioning circuits
SolutionA probabilistic model is derived to predict critical path degradation due to uncertaintyCircuit and process-level fixes proposed for most critical factors
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Summary
Computer-aided design (CAD)/Electronic design automation (EDA) enables electronic systems, and electronic systems enable the world economyCAD/EDA software companies are big players in the world software market, but modestly sized relative to the industries they serveAlthough many “higher productivity” design flows have been developed the industry continues to rely on the RTL synthesis flowEssence of being a CAD engineer is the ability to:
Build large, robust, software systems that Embody sophisticated CAD algorithms, targeted towardSolving real IC design problems
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On Wednesday
More on projectsOverview of the RTL design flow