ee452 finalreport liou mindy martinez tomas · 2013-11-20 · flyback converter mindy liou tomas...

Flyback Converter

Mindy Liou Tomas Martinez

Autumn 2012 EE 452 AB

Final Design Project

Autumn 2012 EE 452 AB Final Design Project 2

Table of Contents Introduction ................................................................................................................................. 3

Design Specifications ............................................................................................................... 3

Design Process ............................................................................................................................ 4

Bode Plots ..................................................................................................................................... 5

Power Stage .......................................................................................................................................... 5

Power Stage and Controller ........................................................................................................... 5

Preliminary Design Schematic ............................................................................................. 7

Preliminary Design Results .................................................................................................... 8

Open .......................................................................................................................................................... 8

Closed ....................................................................................................................................................... 12

Circuit Design Results ............................................................................................................... 15

Open .......................................................................................................................................................... 15

Closed ....................................................................................................................................................... 17

Design Problems, Decisions, and Solutions ...................................................................... 25

Cost Analysis ................................................................................................................................ 27

Appendix ....................................................................................................................................... 28

Table of Figures .......................................................................................................................... 32

References .................................................................................................................................... 33


Introduction This quarter, our lab group will be building a flyback converter, which is an isolated buck-‐boost switching power supply that uses a transformer. This lab report will go through the process of building the device, including design specifications for a closed loop feedback case, our preliminary design for both the open and closed design, our results from implementing the hardware, as well as follow up details. The end portion will include problems we ran into, how we troubleshooted the issues and came up with solutions, how we could have proceeded to build a better flyback converter, as well as a cost analysis. Design Specifications

• Input voltage magnitude: 10 V • Output voltage magnitude: 5 V to 15 V (adjustable at Vref) • Power rating: (maximum output wattage) 10 W • Efficiency: 70% • Maximum output voltage ripple: +/-‐ 2.5% of Vout

• +/-‐ 0.125 V for a 5 V output • +/-‐ 0.375 V for a 15 V output

• Dynamic regulation: +/-‐ 25% of Vout • +/-‐ 1.25 V for a 5 V output • +/-‐ 3.75 V for a 15 V output

• Overshoot: <10% of Vout • < 0.5 V for a 5 V output • < 1.5 V for a 15 V output

• Start up transient magnitude: < 25% of Vout • < 1.25 V for a 5 V output • < 3.75 V for a 15 V output

• Start up duration: < 500 ms We altered several of the design specifications after realizing it would either be too difficult or unrealistic to reach specifications after simulating the circuit as well as trying to implement the hardware design. The original design specifications and explanation to the new specifications are included in the appendix.


Design Process While researching the way a flyback converter functions, we found a forum with this basic open loop flyback converter design simulation provided by an employee of National Instruments EWB Group. This gave us guidance on the way a flyback converter functions, and afterward we were able to assess each individual component to create the power stage model and the controller.

Figure 1: Isolated Flyback Simulation designed by an employee of National Instruments

After exploring the simulation provided by NI, we broke down the components to include the power stage model and controller in Multisim, though the simulation results were not what we ideally wanted. To gather the values, we built the transfer functions for a Type 3 Controller Flyback Converter in MATLAB, determining the component values. Using the generated bode plots, we selected a crossover frequency of 1.26 kHz and calculated the design of the converter through controller design equations based on the SG3524 controller IC. The transformer we are using also has an internal inductance of 85 µH, and that was factored into the final component values.


Matlab Generated Bode Plot of Power Stage

Figure 2: Power Stage Bode Plot

Matlab Generated Bode Plot of Power Stage and Controller

Figure 3: Power Stage and Controller Bode Plot


Design components to be used based on MATLAB code: Flyback Transformer = Coilcraft Q4343BL, Lm = 85 µH R1 = 361.55kΩ R2 = 1.144kΩ R3 = 973Ω C1 = 2.53µF C2 = 76.97nF C3 = 7.98nF Rb = 10kΩ Vref(5V) = 0.1346 V Vref(15V) = 0.405 After designing the hardware circuit and testing the controller, we changed the components and used: R1 = 20kΩ R2 = 340Ω R3 = 976Ω C1 = 2.3 µF C2 = 51nF C3 = 1.9nF Rb = 10kΩ Vref(5V) = 1 V Vref(15V) = 3 V (Component calculations included in the appendix)


Preliminary Design Schematic

Figure 4: Open flyback converter average model design

Figure 5: Closed flyback converter design

While designing the circuit, some of the decisions we had to make were: the type of controller, the frequency, and which transformer, MOSFET, and driver we wanted to use. We chose a Type-‐3 K Factor controller based on the MATLAB script that determined a crossover frequency of 1.26 kHz and a gain of 29.3. We chose the Coilcraft Q-‐4343-‐BL transformer since it could handle up to 36 W, thus preventing more potential issues. We also selected the MTP3055 MOSFET and SG3524 Driver due to familiarity from previous lab projects. The final wiring of the project in Multisim as well as the circuit built on the proto-‐board are included in the appendix.


Design Specification Results: Open Circuit The main concern while designing the open circuit simulation was ensuring that the output voltage ripple remained as little as possible. This would be the foundation for the final output voltage ripple. Maximum output voltage ripple: +/-‐ 2.5% of Vout This is a graph of the 5 V output, showing the output voltage ripple for the simulated design. The output voltage ripple simulated achieved approximately +/-‐0.0295 V. The output voltage ripple is well within the specifications of +/-‐ 0.125 V.

Figure 6: Voltage Ripple of 4.9276V to 4.9705V


This is a graph of the 15 V output, showing the output voltage ripple for the simulated design. The output voltage ripple simulated achieved approximately +/-‐0.0705 V. The output voltage ripple is well within the specifications of +/-‐ 0.375 V.

Figure 7: Voltage Ripple of 14.9295V to 14.9497V

Dynamic Regulation: +/-‐ 25% of Vout

This is a graph of the dynamic regulation from 15 V to 5 V for the simulated design. As shown from this graph there is undershoot of approximately 2.5284 V from the steady state value. This was not within the specification of 1.25 V.

Figure 8: Dynamic Regulation for maximum to minimum output voltage

2.4389V to 4.9673V steady state


This is a graph of the dynamic regulation from 5 V to 15 V for the simulated design. As shown from this graph there is overshoot of approximately 9.3556 V from the steady state value. This was not within the specification of 3.75 V.

Figure 9: Dynamic Regulation for minimum to maximum output voltage

24.3036V to 14.9480V steady state Dynamic Regulation: Although we did not achieve the dynamic regulation specifications in the simulation the actual values for dynamic regulation were much smaller. The simulation was used as a base for circuit implementation and therefore reducing the dynamic regulation in the simulation was bypassed. If necessary a slow start circuit could be implemented to reduce the dynamic regulation in the actual final circuit.


Transient Magnitude: < 25% of Vout This is a graph of the start up duration and transient magnitude for the simulated 15 V output. The start up duration is approximately 482.6797 ms which is just within the specification of 500 ms. The transient magnitude is approximately 2.8832 V which is within the specification of 3.75 V.

Figure 10: Transient magnitude and start up duration for maximum output voltage

17.9664V to 15.0832V steady state This is a graph of the start up duration and transient magnitude for the simulated 15 V output. The start up duration is approximately 955.7662 ms which is not within the specification of 500 ms. Again this specification was bypassed and would be checked in the actual final circuit. The transient magnitude is approximately 0 V which is within the specification of 1.25 V.

Figure 11: Transient magnitude and start up duration for minimum output voltage

Smooth 0 to 4.9607V steady state


Design Specifications Results: Closed Circuit Efficiency: 70% This is a graph of efficiency for the simulated closed loop 15 V output. The efficiency is approximately 73.2% which is within the specification of 70%. This was actually one of the more difficult specifications to achieve in simulation and proved to be the most difficult as well in the actual circuit.

Figure 12: Efficiency

Actual: 73.2%


Maximum output voltage ripple: +/-‐ 2.5% of Vout This is a graph of the 5 V output, showing the output voltage ripple for the simulated closed loop design. The output voltage ripple simulated achieved approximately 0 V. The output voltage ripple is well within the specifications of +/-‐ 0.125 V.

Figure 13: Voltage Ripple of 5 V to 5 V ripple (no ripple)

This is a graph of the 15 V output, showing the output voltage ripple for the simulated closed loop design. The output voltage ripple simulated achieved approximately 0 V. The output voltage ripple is well within the specifications of +/-‐ 0.375 V.

Figure 14: Voltage ripple of 14.8600 V to 14.8600 V ripple (no ripple)


Dynamic Regulation: +/-‐ 25% of Vout Under the recommendation of Professor Christie, these simulations were under automatically determined initial conditions by Multisim, instead of having the initial conditions set to zero. This is a graph of the dynamic regulation from 15 V to 5 V for the simulated closed loop design. As shown from this graph there is no undershoot from the steady state value.

Figure 15: Dynamic regulation for minimum to maximum output

Dynamic regulation from 5.0000 V to 15.0438 V (meets our specifications of 18.75 V) This is a graph of the dynamic regulation from 5 V to 15 V for the simulated closed loop design. As shown from this graph there is no overshoot from the steady state value.

Figure 16: Dynamic regulation for maximum to minimum output

Dynamic regulation from 15.0457 V to 5.0003 V (meets our specifications of 3.75 V)


Circuit Design Implementation: Open Circuit This is a graph of the 5 V output, showing the output voltage ripple for the actual circuit. The output voltage ripple achieved approximately +/-‐0.072 V. The output voltage ripple is within the specifications of +/-‐ 0.125 V.

Figure 17: 5 V output

(Purple = Vout, Teal = VG) 0.144V Ripple for Vout = 5 V (CH3 window: 200 mV) This waveform shows the voltage drop across the drain of the MOSFET. As displayed by the cursors below there is a spike of 3.2 V that occurs at the beginning of each pulse. This was not a significant problem for the 5 V case.

Figure 18: Voltage drop across the MOSFET drain for 5 V output

(Purple = Vout, Teal = VD) VDrain = 20.8 V with a 3.2 V initial spike for Vout = 5 V


This is a graph of the 15 V output, showing the output voltage ripple for the actual circuit. The output voltage ripple achieved approximately +/-‐0.36 V. The output voltage ripple is just within the specifications of +/-‐ 0.375 V.

Figure 19: 15 V output

(Purple = Vout) 0.720V ripple for Vout = 15 V (CH3 window: 200 mV) This waveform shows the voltage drop across the drain of the MOSFET. As displayed by the cursors below there is a spike of 16.8 V that occurs at the beginning of each pulse. This became more of a significant problem for the 15 V case than the 5 V case. This spike is most likely the major cause for the larger output voltage ripple in the 15 V case.

Figure 20: Voltage drop across the MOSFET drain for 15 V output (Teal = VD) VDrain = 44.4 V with a 16.8 V initial spike for Vout = 15 V


Circuit Design Implementation: Closed Circuit This is a graph of the closed loop 5 V output, showing the output voltage ripple for the actual circuit.

Figure 21: Vout = 5.11 V

This is a graph of the closed loop 5.11 V output, showing the output voltage ripple for the actual circuit. The output voltage ripple achieved approximately +/-‐0.14 V. The output voltage ripple is just shy of the specifications +/-‐ 0.125 V.

Figure 22: Voltage Ripple for minimum output voltage

Did not achieve specifications


This is a graph of the transient magnitude for the closed loop 5 V output. The transient magnitude is approximately 3.8 V which is not within the specification of 1.25 V.

Figure 23: Start up transient magnitude for minimum output voltage

Did not achieve specifications This is a graph of the start up duration for the closed loop 5 V output. The start up duration is approximately 45 ms which is well within the specification of 500 ms.

Figure 24: Start up duration for minimum output voltage

Achieved specifications


This is a graph of the closed loop overshoot caused by increasing the input voltage from 10 V to 11 V for a 5 V output. As shown from this graph there is overshoot of approximately 0.216 V from the steady state value. This is within the specification of 0.5 V.

Figure 25: Overshoot for minimum output voltage

Achieved specifications This is a graph of the closed loop dynamic regulation from 15 V to 5 V for the simulated design. As shown from this graph there is undershoot of approximately 0.6 V from the steady state value. This is well within the specification of 1.25 V.

Figure 26: Dynamic regulation for15 V to 5 V output



This is a graph of the closed loop 15 V output, showing the output voltage ripple for the actual circuit.

Figure 27: Vout = 14.8 V

This is a graph of the closed loop 14.8 V output, showing the output voltage ripple for the actual circuit. The output voltage ripple achieved approximately +/-‐0.59 V. The output voltage ripple is not within the specifications of +/-‐ 0.375 V.

Figure 28: Voltage Ripple for maximum output voltage

Did not achieve specifications


This is a graph of the transient magnitude for the closed loop 15 V output. As shown below there is no overshoot from the steady state value which is within the specification of 3.75 V.

Figure 29: Start up transient magnitude for maximum output voltage

Achieved specifications This is a graph of the start up duration for the closed loop 15 V output. The start up duration is approximately 42 ms which is well within the specification of 500 ms.

Figure 30: Start up duration for maximum output voltage



This is a graph of the closed loop overshoot caused by increasing the input voltage from 10 V to 11 V for a 15 V output. As shown from this graph there is overshoot of approximately 2.16 V from the steady state value. This is not within the specification of 1.5 V.

Figure 31: Overshoot for maximum output voltage

Did not achieve specifications This is a graph of the dynamic regulation from 5 V to 15 V for the simulated design. As shown from this graph there is no overshoot from the steady state value. This is within the specification of 3.75 V.

Figure 32: Dynamic regulation from 5 V to 15 V output



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Specification 5 V expected

5 V actual

15 V expected

15 V actual

Output voltage ripple +/-‐ 0.125 V +/-‐ 0.14 V +/-‐ 0.375 V +/-‐ 0.59 V

Dynamic regulation +/-‐ 1.25 V 0.6 V +/-‐ 3.75 V 0 V

Overshoot < 0.5 V 0.216 V < 1.5 V 2.16 V

Start up transient magnitude < 1.25 V 3.8 V < 3.75 V 0 V

Start up duration < 500 ms 45 ms < 500 ms 42 ms

Efficiency > 70 % 55.1% > 70% 52.7%

Power rating 10 W 1.25 W 10 W 11.25 W

Table 1: Specifications and results How to achieve better efficiency? We could have improved the efficiency with several additional steps. We first could have checked the transformer to make sure it did not saturate since it was operating at a lower frequency (50 kHz instead of our original 100 kHz). Not only that, but the zener diode that was included at the MOSFET gate should have been in parallel with the resistance as opposed to in series. The way the diode was set up enabled the current to go into the MOSFET, but prevented the current from leaving. A third option was to forgo the breadboard and build a smaller, soldered, circuit. How to decrease startup transient magnitude and overshoot? The best process to lower the overshoot was to include a slow start circuit. Based on Lab 3, “When the converter is first energized, the startup transient can cause output voltage far in excess of the voltage specification…therefore, it is useful to bring the converter up to operating voltage relatively slowly, minimizing any overshoot during startup…minimize[ing] the error between a reference voltage and output voltage.” (Christie) How to improve power rating? Based on our specifications, we were not able to reach a power rating of 10 W. We realized that since the output voltage was adjustable, it was necessary to be able to adjust the required power rating or adjust the load resistance. We ultimately decided not to change the load resistance in order to maintain consistent and comparable results.


Design Problems, Decisions, and Solutions

We ran into several problems throughout the entire process, from simulation, to open loop hardware implementation, to closed loop hardware implementation. Some of the issues include the inductance of the transformer, the floor limiter, the inverted error amplifier inputs, difficulty with lab benches, and overheated MOSFETs and BJTs.

One of the issues that came up with the software while simulating the circuit was trying to meet the dynamic regulation specifications of +/-‐ 25% of the output voltage. We discovered that Multisim had a tendency to crash during simulation at odd points especially while the output was in the process of reaching steady state. One of the solutions that helped to observe dynamic regulation was to change the initial conditions to be automatically set by Multisim, as opposed to having it initially set to zero. Once the simulations simulated properly and we ordered the transformer, we realized that the original design of having an inductance of 216 µH would not be possible because the Coilcraft transformer had an internal inductance of 85 µH and we would not be able to increase that since it was an internal component. This wasn’t as large of a problem as we anticipated since we were able to go back to the simulated design and recalculate some of the components from the base circuit that was already designed.

When we were implementing the circuit design, each stage of the design process had issues that had to be addressed. First, while testing the transformer with the function generator, the turns ratio wasn’t exactly 1:0.8 like the circuit design was based on. In addition, it was difficult to get an accurate understanding of the piece using the function generator due to internal resistance of the generator, however we recognized that the turns ratio did not have to be exact while implementing the actual circuit because the rest of the circuit design left room to be flexible turns ratio. Not only that, but once the open loop circuit was set up, we realized that components and physical pieces would not always function as if it were ideal conditions. One of the best processes we discovered was to go through the circuit through the individual stages to consider the expected results, then test and observe the circuit to see if the actual results met what we were expecting, and if not we could analyze where the issues stemmed from.

Once the open circuit was built, we tested the output voltage ripple to determine if it was within the specifications. We realized that the best achievable voltage ripple was around 3.3%, as opposed to the goal of 2.5%. Since the controller would not regulate the output voltage, we chose to proceed with 3.3%. Some of the alterations we made to the circuit included adding snubbers across the MOSFET and diode, changing the MUR420 power diode to a Schottkey diode, increasing various capacitances across the input and output voltage to reduce spiking, and changing the frequency from 100 kHz to 50 kHz. We


noticed that this gave us a larger range of output voltage, however this also meant there was the potential risk of running into the problem of saturating the transformer.

Some of the biggest issues were built around the controller; due to the way that the SG3524 PWM was designed, we had to include a floor limiter in the Type 3 feedback controller to ensure that the PWM did not exceed its ramp voltage of 0.8 V to 3.5 V while also inverting the error amplifier inputs. We finally set the floor limiter to 1 V, and this was enough to properly regulate the output voltages.

The final step that we anticipated was isolating the circuit. Throughout the entire testing process, we used two power supplies: one to power the PWM Controller, and another to supply voltage to the transformer. Changing to one source proved to have no problems for the circuit. The next step for the circuit would be to add an optocoupler to completely isolate the output from the input to create an isolated flyback converter. Another design decision that we had to make was to capture dynamic regulation. We were controlling the output voltage through a potentiometer that fed into Pin 1 that was powered through Pin 16 of the PWM Controller that supplied 5 V. To get an output voltage of 5 V, we set the potentiometer to feed 1 V into Pin 1, and to get an output voltage of 15 V, we set the potentiometer to feed 3 V into Pin 1. However that required adjusting the potentiometer, which would not be effective to measure dynamic regulation, so we decided to use a switch and have two potentiometers regulating Vref.

Outside of the circuit design, one of our problems was difficulty with lab benches that provided inconsistent results. Several of the stations did not have power supplies that would be useful enough for testing the circuit, mostly due to limited output current. However once we found a station that was in line with what we wanted for the circuit, we ran into problems of overheating many MOSFETs and BJTs. This was mostly caused by not realizing the components were overloading and putting more current into the circuit than the circuit could handle. One of the ways we could have prevented this from happening was actually putting a maximum amount of current that could go through the circuit while we were testing it instead of setting the maximum current to be the maximum amount that the power supply could provide.


Cost Analysis Controller Part Number Cost per

unit QTY Total

Cost C1 (uF) CE4.7-‐50 Capacitor, electrolytic 4.7uF 50V $0.30 2 $0.60 C2 (nF) CC-‐.001U Capacitor, ceramic disc 0.001uF $0.20 1 $0.20 CC-‐.05U Capacitor, ceramic disc 0.050uF $0.20 1 $0.20 C3 (nF) CC-‐.0018U Capacitor, ceramic disc 0.0018uF $0.20 1 $0.20 R1 (kohm) R1-‐20.0k Resistor, 1%, ¼W, 20.0k $0.10 2 $0.20 R2 (kohm) R1-‐340 Resistor, 1%, ¼W, 340ohm $0.10 1 $0.10 R3 (ohm) R1-‐976 Resistor, 1%, ¼W, 976ohm $0.10 1 $0.10 Rb (kohm) R1-‐10.0k Resistor, 1%, ¼W, 10.0k $0.10 1 $0.10 NPN Transistor 2N3904 Transistor, NPN, GP Amplifier $0.20 1 $0.20 Potentiometer T34-‐10k Trimmer, ¾ turn, 10kohm $1.00 1 $1.00 Open Circuit Part Number Cost per

unit QTY Total

Cost Resistors R4-‐10 Resistor, 5%, 5W, 10ohm $0.50 2 $1.00 R1-‐2.00k Resistor, 1%, ¼W, 2.00k $0.10 2 $0.20 R1-‐25.5k Resistor, 1%, ¼W, 25.5k $0.10 1 $0.10 R5-‐2.0k Resistor, 5%, ¼W, 2.0k $0.10 2 $0.20 R5-‐300 Resistor, 5%, ¼W, 300ohm $0.10 2 $0.20 R6-‐1.0k Resistor, 5%, ½W, 1.0k $0.10 1 $0.10 R5-‐100 Resistor, 5%, ¼W, 100ohm $0.10 1 $0.10 Capacitors CC-‐.01U Capacitor, ceramic disc 0.01uF $0.20 1 $0.20 CC-‐.1U Capacitor, ceramic disc 0.1uF $0.20 6 $1.20 CC-‐.001U Capacitor, ceramic disc 0.001uF $0.20 1 $0.20 CE470-‐50 Capacitor, electrolytic 470uF 50V $0.30 2 $0.60 Schottky Diode 1N5819 Diode, Schottky Rectifier $0.30 1 $0.30 Diode 1N4732 Zener Diode, 4.7v $0.30 2 $0.60 Transformer Coilcraft Flyback Regulator Transformer Q4343-‐

BL $4.71 1 $4.71

Potentiometer T34-‐10k Trimmer, ¾ turn, 10kohm $1.00 2 $2.00 Switch SWDIP2 DIP switch, 2 position rocker $1.00 1 $1.00 MOSFET MTP3055 MOSFET, N-‐Channel, Power $1.00 1 $1.00 PWM Controller

SG3524 Regulating Pulse Width Modulator $1.60 1 $1.60

Heat Sync $0.40 1 $0.40 Total $18.61

Table 2: Cost Analysis


Appendix Original intended specifications (underlined specifications altered):

• Input voltage magnitude: 10 V • Output voltage magnitude: 5 V to 20 V (adjustable at controller) • Power rating: (maximum wattage) 1 W • Efficiency: 70% • Maximum output voltage ripple: +/-‐ 2.5% of Vout

• +/-‐ 0.125 V for a 5 V output • +/-‐ 0.375 V for a 15 V output

• Dynamic regulation: +/-‐ 25% of Vout • +/-‐ 1.25 V for a 5 V output • +/-‐ 3.75 V for a 15 V output

• Overshoot: <10% of Vout • < 0.5 V for a 5 V output • < 1.5 V for a 15 V output

• Start up transient magnitude: < 25% of Vout • < 1.25 V for a 5 V output • < 3.75 V for a 15 V output

• Start up duration: < 500 µs Since the transformer had an internal inductance of 85 µH, we had to change the power rating in order to best accommodate that component as well as the additional capacitance. We also changed the start up duration from 500 µs to 500 ms because after simulating the circuit, we realized that it was not realistic to get the circuit to reach steady state that quickly. The simulation reached steady state at approximately 200ms when Multisim was not set to automatically determine the initial conditions. One problem we ran into was that the simulation would not even properly function when it was set to zero. Power Stage MATLAB Script Vin = 10; D = 0.652; L = 85e-6; Le = L/(1-D)^2; R = 20; r = 10e-3; C = 47e-6; Vr = 3.5 - 0.8; Gpwm = 1/Vr; s = tf('s');


a = (Vin/(1-D)^2); b = (1-(s * D * (Le/R))); n = (1+(s * r * C)); d = (Le * C) * (s^2 + (s * ((1/(R*C))+(r/Le))) + (1/(Le * C))); Gps = a * b * (n/d); G = Gps * Gpwm; bode(G); grid on;

Power Stage + Controller MATLAB Script Vin = 10; Vo = 15; D = 0.652; L = 85e-6; Le = L/(1-D)^2; R = 20; r = 10e-3; C = 47e-6; Vr = 3.5 - 0.8; Gpwm = 1/Vr; fcr = 1.26e3; %input Gps_fcr_gain = 29.3; %input Gps_fcr_angle = (185-360); %input boost = 60 - Gps_fcr_angle - 90; K = tand(boost/4 + 45); fz = fcr/K; fp = fcr*K; wz = 2*pi*fz; wp = 2*pi*fp; Gps_fcr = 10^(Gps_fcr_gain/20); kfb = 1; Gc_fcr = 1/(kfb*Gpwm*Gps_fcr); kc = Gc_fcr*wz/K; s = tf('s'); a = (Vin/(1-D)^2); b = (1-(s * D * (Le/R))); n = (1+(s * r * C)); d = (Le * C) * (s^2 + (s * ((1/(R*C))+(r/Le))) + (1/(Le * C))); e = kc/s; f = (1+s/wz)^2/(1+s/wp)^2; Gl = a*b*(n/d)*kfb*e*f*Gpwm; bode(Gl); grid on; gm = 0.002; Rb = 10000; R1 = 1.1*(wp/wz - 1)*Rb C2 = (gm/kc)*(wz/wp)*(Rb/(Rb + R1)) C1 = ((gm/kc)*(Rb/(Rb + R1)) - C2)


R2 = 1/(wz*C1) R3 = (R1/(wp - wz))*(wz - wp*(Rb/(Rb + R1))) C3 = 1/(wz*(R1 + R3)) Vref = Vo*(Rb/(Rb + R1))

Circuit built on the proto-‐board

Figure 33: Proto-‐board circuit

The controller is on the right breadboard, though it was not connected to the rest of the circuit when the picture was taken.


Final Closed Loop Design Schematic

Figure 34: Final Closed Loop Design Schematic


Table of Figures Figure 1: Isolated Flyback Simulation designed by an employee of National Instruments Figure 2: Power Stage Bode Plot Figure 3: Power Stage and Controller Bode Plot Figure 4: Open flyback converter average model design Figure 5: Closed flyback converter design Design Specification Results: Open Circuit Figure 6: Voltage Ripple of 4.9276V to 4.9705V Figure 7: Voltage Ripple of 14.9295V to 14.9497V Figure 8: Dynamic Regulation for maximum to minimum output voltage Figure 9: Dynamic Regulation for minimum to maximum output voltage Figure 10: Transient magnitude and start up duration for maximum output voltage Figure 11: Transient magnitude and start up duration for minimum output voltage Design Specification Results: Closed Circuit Figure 12: Efficiency Figure 13: Voltage Ripple of 5 V to 5 V ripple (no ripple) Figure 14: Voltage ripple of 14.8600 V to 14.8600 V ripple (no ripple) Figure 15: Dynamic regulation for minimum to maximum output Figure 16: Dynamic regulation for maximum to minimum output Circuit Design Implementation: Open Circuit Figure 17: 5 V output Figure 18: Voltage drop across the MOSFET drain for 5 V output Figure 19: 15 V output Figure 20: Voltage drop across the MOSFET drain for 15 V output Circuit Design Implementation: Closed Circuit Figure 21: Vout = 5.11 V Figure 22: Voltage Ripple for minimum output voltage Figure 23: Start up transient magnitude for minimum output voltage Figure 24: Start up duration for minimum output voltage Figure 25: Overshoot for minimum output voltage Figure 26: Dynamic regulation for15 V to 5 V output Figure 27: Vout = 14.8 V Figure 28: Voltage Ripple for maximum output voltage Figure 29: Start up transient magnitude for maximum output voltage Figure 30: Start up duration for maximum output voltage Figure 31: Overshoot for maximum output voltage Figure 32: Dynamic regulation from 5 V to 15 V output Figure 33: Proto-‐board circuit Figure 34: Final Closed Loop Design Schematic Table 1: Specifications and results Table 2: Cost analysis


References Christie, Rich. Closed Loop Flyback Converter. EE 452 Power Electronics Design. N.p., 19

Oct. 2012. Web. National Instruments EWB Group, Max. "Isolated Flyback Simulation?" NI Discussion

Forums. National Instruments, 01 Mar. 2011. Web. 20 Nov. 2012 <http://forums.ni.com/t5/Circuit-‐Design-‐Suite-‐Multisim/Isolated-‐flyback-‐simulation/td-‐p/1463858>.

"Q4343-‐BLFlyback Regulator Transformer." Coilcraft Q4343-‐BL Flyback Regulator

Transformer. Coilcraft, 13 Nov. 2012. Web. 12 Dec. 2012.

ee452 finalreport liou mindy martinez tomas · 2013-11-20 · flyback converter mindy liou tomas...

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