ee382v: embedded system design and...

EE382V: Embedded Sys Dsgn and Modeling

Lecture 1

(c) 2010 A. Gerstlauer 1

EE382V:Embedded System Design and Modeling

Andreas GerstlauerElectrical and Computer Engineering

University of Texas at [email protected]

Lecture 1 - Introduction

EE382V: Embedded Sys Dsgn and Modeling, Lecture 1 © 2010 A. Gerstlauer 2

Lecture 1: Outline

• Introduction• Embedded systems

• System-level design

• Modeling

• Course information• Administration

• Topics

• Materials

• Policies

• Projects


Lecture 1



Embedded Systems

• Systems that are part of a larger system

• Application-specific– Diverse application areas

• Tight constraints– Real-time, performance, power, size

– Cost, time-to-market, reliability

• Ubiquitous

• Far bigger market than general-purpose computing (PCs, servers)

– $46 billion in ‘04, >$90 billion by 2010, 14% annual growth

– 4 billion devices in ‘04

– 98% of processors sold[Turley02, embedded.com]


System Design is hard…


Lecture 1



… and getting harder

• Growing system complexities

• Increasing application demands– Networked and distributed

– Cyber-physical integration

– Increasingly programmable & customizable

• Technological advances– Multi-Processor System-On-Chip (MPSoC)

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1 99 3

1 99 5

1 99 7

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2 00 1

2 00 3

2 00 5

2 00 7

2 00 9

IC capacity

Productivity

Gap

Source: SEMATECH; Courtesy of: T. Givargis, F. Vahid. “Embedded System Design”, Wiley 2002.


General-Purpose Computing

• Reaching physical limits of technology scaling

• Power/utilization/… walls and dark silicon

• Efficiency/optimality vs. flexibility/generality

Opportunity and need for specialization

Heterogeneous multi-core /Asynchronous CMP

GP-GPUs


Lecture 1



Source: T. Noll, RWTH Aachen, via R. Leupers, “From ASIP to MPSoC”, Computer Engineering Colloquium, TU Delft, 2006

Processor Implementation Options


Multi-Processor System-on-Chip (MPSoC)

Frontside Bus

SystemMemory

Local Bus

Local RAM

Bridge

SharedRAM

DSP Bus

DSP RAM

MemoryController GPU

DSP

HardwareAccelerator

CPU

HardwareAccelerator

VideoFront End


Lecture 1



MPSoC Challenges

Applications

ProgrammingModel?

• Complexity

• High degree of parallelism atvarious levels

• High degree of design freedom

• Multiple optimization objectivesdesign constraints

• Heterogeneity

• Of components– Processors, memories, busses

• Of design tasks– Architecture, mapping, scheduling


System levelSystem levelSystem levelSystem level

Abstraction Levels

• Move to higher levels of abstraction [ITRS07, itrs.net]

Electronic system-level (ESL) design

1E0

1E1

1E2

1E3

1E4

1E5

1E6

1E7

Number of componentsLevel

Gate

RTL

Algorithm

Transistor

Ab

stra

ctio

n

Ac

cura

cy

Source: R. Doemer, UC Irvine


Lecture 1



System-Level Design

• From specification• Functionality, behavior

– Application algorithms– Constraints

• To implementation• Architecture

– Spatial and temporal order– Components and

connectivity– Across hardware and

software

Design automation at the system level• Modeling and simulation• Synthesis• Verification

Proc

Proc

Proc

Proc

Proc

Requirements, constraints

Implementation (HW/SW synthesis)

SystemDesign

DCT

TX

ARM

M1Ctrl

I/O4

HW

DSP

MBUS

BUS1 (AHB) BUS2 (DSP)

Arb

iter

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IP Bridge

DCTBus

I/O3I/O2I/O1

DMA

M1

Enc DecJpeg

Codebk

stripe

SI BO BI SO

DCT

MP3


Modeling

• A model:

• Abstraction of physical reality

Mathematical formula, drawing/blueprint, data

• Core of any design process

• Specification– Define (formally!) desired characteristics, “golden” reference

• Exploration– Validate design choices

• Analysis and evaluation– Static analysis

– Simulation/experiments

Predict before the system is built Contract of what to build

Detect problems early (and cheaply)

Simulator

Model

Stimuli Results

Correctness of model? Accuracy vs. simplicity


Lecture 1



System Specification• Capture requirements (what)

• Functional– Free of any implementation

details (not how)

• Non-functional– Quality metrics– Performance constraints

• Formal representation• Models of computation

– Objects and compositions– Concurrency and time

• Executable– Analysis or simulation

Application development Precise description of desired system behavior

Complete and umabgious

Natural language Ambiguous Incomplete


System Architecture

Application mapping

Allocation

Partitioning

Scheduling

Bri

dg

e

P1 P3

CPU Mem

HW IP

P5

C1, C2

Arb

iter

P4P2

C1, C2CPU Bus IP Bus

• Processing elements (PEs)• Processors

– General-purpose, programmable– Digital signal processors (DSPs)– Application-specific instruction

set processor (ASIP)– Custom hardware processors– Intellectual property (IP)

• Memories

• Communication elements (CEs)• Transducers, bus bridges• I/O peripherals

• Busses• Communication media

– Parallel, master/slave protocols– Serial and network media


Lecture 1



System Implementation

• Hardware• Microarchitecture• Register-transfer level (RTL)

• Software binaries• Application object code• Real-time operating

system (RTOS)• Hardware abstraction layer (HAL)

• Interfaces• Pins and wires• Arbiters, muxes, interrupt

controllers (ICs), etc.• Bus protocol state machines

CP

U

Specification for further manufacturing

Logic synthesis

Layout


Bri

dg

e

CPU Mem

HW IP

Arb

iter

v1

C1

B1 B2

B3 B4

C2

CommunicationComputation &

System SynthesisFront-End


Software / HardwareSynthesisBack-End


TLM

Inst

ruct

ion

-Set

Sim

ula

tor

(IS

S) C

-based

RT

L

Software Object Code

Hardware VHDL/Verilog

Application specification

Transaction-Level ModelsTLMTLMTLMn

Platform library

System-Level Design Flow

System-Level Design Languages (SLDLs)

C/C++ code


Lecture 1



System-On-Chip Environment (SCE)

ArchnArchnTLMn

Impln

Spec

ImplnImpln

Synthesize target HW/SW

Compile onto platform

Commercial derivative for Japanese Aerospace Exploration Agency

Commercial derivative for Japanese Aerospace Exploration Agency

Specification

System Design(Specify-Explore-Refine)

SWDB

Systemmodels

CPUn.bin

Implementation Model

PE/CE/BusDatabase

TLMnTLMnTLMi

Hardware Synthesis

Software Synthesis

RTLDB

RTLnRTLnRTLnISSnISSnISSn CPUn.bin

CPUn.binHWn.vHWn.vHWn.v

Design Decisions


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Software Object Code

Hardware VHDL/Verilog

Application specification

Transaction-Level ModelsTLMTLMTLMn

Platform library

UT ECE Courses

System-Level Design Languages (SLDLs)

C/C++ code

EE382V: Embedded System Design & Modeling

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Lecture 1



Lecture 1: Outline

Introduction Embedded systems

Abstraction levels, design flow

System-level design

Design tasks, challenges and tools

• Course information• Administration

• Topics

• Materials

• Policies

• Projects


Class Administration

• Schedule

• Lectures: TTh 3:30-5pm, ENS109

• Instructor

• Prof. Andreas Gerstlauer– E-mail: [email protected]

– Office: ACE 6.118

– Office hours: W 2:00-4:00pm or after class

• Information

• Web page: http://www.ece.utexas.edu/~gerstl/ee382v_f10

• Announcements, assignments, grades: Blackboard

• Questions, discussions: Blackboard


Lecture 1



Course Topics

• System-level design• Methodologies, design flow, models• System-level design languages (SLDL): SpecC, SystemC

• Functional modeling• System specification and validation concepts• Formal Models of Computation (MoC)

• Architecture modeling• Computation and communication refinement• Virtual platform prototyping, transaction-level modeling

• System synthesis• Profiling, analysis and estimation tools• Design space exploration algorithms

Prerequisites Software: C/C++ (algorithms and data structures) Hardware: VHDL/Verilog (digital design) Embedded systems and embedded software


Textbooks (1)

• Main textbook

• D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, 2009 (“orange book”)

• Optional books

• A. Gerstlauer, R. Doemer, J. Peng, D. Gajski, System Design: A Practical Guide with SpecC, Kluwer, 2001 (“yellow book”)

– Practical, example-driven introduction using SpecC


Lecture 1



Textbooks (2)

• Optional books (cont’d)

• T. Groetker, S. Liao, G. Martin, S. Swan,System Design with SystemC, Kluwer, 2002 (“black book")

– Reference for SystemC language and methodology

• F. Vahid, T. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Wiley, John & Sons, 2001

– Background about embedded systems in general

Additional reading material posted on class webpage


Policies

• Grading• Homeworks: 15%• Labs: 20% • Midterm: 25% • Project: 40% No late submissions!

• Academic dishonesty• Homeworks

– Discuss questions and problems with others– Turn in own, independent solution

• Labs and project– Teams of up to 3 students– One report and presentation


Lecture 1



Project

• Project goals

• Independent research or development project– System design example/case study

– System design research problem

– Literature survey on system design research area

• Literature review, proposal, implementation

• Final report and presentation in publishable quality

• Project timeline

• Abstract: October 1

• Proposal, literature survey: October 21 (tentative)

• Presentations: last week of classes (Nov. 30 & Dec 2)

• Report: finals week (Dec. 9)


Some Possible Projects

• Design projects

• (Embedded) system design example

• Specify, model, simulate, explore, synthesize using SCE

• Research projects

• Specification modeling– Model-based design: LabView/Matlab/Powerpoint to chip

» Translation of MoCs into SpecC/SystemC for synthesis

• Platform modeling– Component modeling, e.g. bus TLM or ISS (QEMU) integration

– OS modeling (multi-core schedulers, OS-internal timing)

– Reliability modeling and simulation

– Assertion-based verification

• Synthesis– (Statistical) power, performance, reliability estimation

– Machine learning for mapping (allocation, partitioning, scheduling)

– Hardware or software synthesis and optimization


Lecture 1



Successful Past Projects

• Modeling

• A. Pedram, C. Craven, T. Amimeur, “Modeling Cache Effects at the Transaction Level,”IESS 2009 (best paper runner-up)

• A. Banerjee, “Transaction Level Modeling of Best Effort Channels for Networked Embedded Devices”, IESS 2009.

• Exploration

• J. Lin, A. Srivatsa, “Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems,” 2010.

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