ee370 chapter1 slides

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1

EE370Digital Electronics

Yogesh S. ChauhanDepartment of Electrical Engineering

IIT KanpurEmail: [email protected]

Office: WL125, Phone: 7244

Computer

An electronic device which is capable of receiving information (data) in a particular form and of performing a sequence of operations in accordance with a predetermined but variable set of procedural instructions (program) to produce a result in the form of information or signals.

Minimize human efforts with speed and efficiency.

Y. S. Chauhan, IIT Kanpur 2

Why Digital?

Noise Margin Can be reduced to the limit we want

Fidelity/Regeneration Robustness Scalability Data Storage Ease of data handling


Digital System


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The First Computer


The BabbageDifference Engine(1832)

25,000 partscost: 17,470

ENIAC - The first electronic computer (1946)

17,468 vacuum tubes

7200 crystal diodes

1500 relays 70,000 resistors 10,000 capacitors Weight > 27 Ton 1800 sq. ft. 150 kW of

electricityY. S. Chauhan, IIT Kanpur 6

The Transistor Revolution


First transistorBell Labs, 1948

The First Integrated Circuits


Bipolar logic1960s

ECL 3-input GateMotorola 1966

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Intel 4004 Micro-Processor


19711000transistors1MHzoperation

Intel Pentium (IV) microprocessor


Moores Law In 1965, Gordon Moore noted that the number of

transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology

will double its effectiveness every 18 months


16151413121110

9876543210

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Transistor Counts


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Moores law in Microprocessors


40048008

80808085 8086

286386

486Pentium proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

T

r

a

n

s

i

s

t

o

r

s

(

M

T

)

2Xgrowthin1.96years!

TransistorsonLeadMicroprocessorsdoubleevery2years

Die Size Growth


40048008

80808085

8086286

386486 Pentiumproc

P6

1

10

100

1970 1980 1990 2000 2010Year

D

i

e

s

i

z

e

(

m

m

)

~7%growthperyear~2Xgrowthin10years

Diesizegrowsby14%tosatisfyMooresLaw

Frequency


P6Pentiumproc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

F

r

e

q

u

e

n

c

y

(

M

h

z

)

LeadMicroprocessorsfrequencydoublesevery2years

Doublesevery2years

Power Dissipation


P6Pentiumproc

486386

2868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

P

o

w

e

r

(

W

a

t

t

s

)

LeadMicroprocessorspowercontinuestoincrease

Courtesy,Intel

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Power density


400480088080

8085

8086

286 386 486Pentium proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

P

o

w

e

r

D

e

n

s

i

t

y

(

W

/

c

m

2

)

HotPlate

NuclearReactor

RocketNozzle

Powerdensitytoohightokeepjunctionsatlowtemp

Power is a major problem


5KW18KW

1.5KW500W

40048008

80808085

8086286

386486

Pentium proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

P

o

w

e

r

(

W

a

t

t

s

)

Powerdeliveryanddissipationwillbeprohibitive

Not Only Microprocessors


AnalogBaseband

DigitalBaseband

(DSP+MCU)

PowerManagement

SmallSignalRF

PowerRF

CellPhone

Challenges in Digital Design


Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution.

Everything Looks a Little Different

Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc.

and Theres a Lot of Them!

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Why Scaling?

Technology shrinks by 0.7/generation With every generation can integrate 2X more

functions per chip; chip cost does not increase significantly

Cost of a function decreases by 2x But

How to design chips with more and more functions? Design engineering population does not double every

two years Hence, a need for more efficient design methods

Exploit different levels of abstraction


Design Abstraction Levels


n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

DesignAutomationisthekey.

Design Metrics

How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function


Cost of Integrated Circuits

NRE (non-recurring engineering) costs Design time and effort, mask generation One-time cost factor

Recurring costs Silicon processing, packaging, test proportional to volume proportional to chip area


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Cost of Integrated Circuits

Cost per IC = Variable cost per IC + (fixed cost/volume)

The impact of fixed cost is more pronounced for small volume products.


NRE Cost is Increasing


Die Cost


Single die

Wafer

From http://www.amd.com

Going up to 12 (30cm)

Cost per Transistor


0.0000001

0.000001

0.00001

0.0001

0.001

0.01

0.11

1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

cost: -per-transistor

Fabrication capital cost per transistor (Moores law)

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Yield


%100per wafer chips ofnumber Total

per wafer chips good of No. Y

yield Dieper wafer Dies

costWafer cost Die

area die2

diameterwafer

area die

diameter/2wafer per wafer Dies

2

Yield


%100per wafer chips ofnumber Total

per wafer chips good of No. Y

yield Dieper wafer Dies

costWafer cost Die

Defects


area dieareaunit per defects1yield die is approximately 3

4area) (die cost die f

Some Examples (1994)


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ReliabilityNoise in Digital Integrated Circuits

Noise unwanted variations of voltages and currents at the logic nodes


i(t)

Inductive coupling Capacitive coupling Power and groundnoise

v(t) VDD

Voltagechangeononewirecaninfluencesignalontheneighboringwire

crosstalk

Currentchangeononewirecaninfluencesignalontheneighboringwire

Example of Capacitive Coupling

Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale


Crosstalkvs.Technology

0.16mCMOS0.12mCMOS

0.35mCMOS

0.25mCMOS

PulsedSignal

BlacklinequietRedlinespulsedGlitchesstrengthvstechnology

FromDunlop,Lucent,2000

Lets start Digital Electronics

Digital Electronics uses binary number system Logic 0 == Logic Low Logic 1 == Logic High

Real world is not digital


Analog to Digital conversion


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Binary digital signal


Digital Logic Inverter

The logic inverter is the most basic element in digital circuit design.

It plays a role parallel to that of the amplifier in analog circuits. Inverter inverts the logic value of its input signal. Thus, for a logic-0 input, the output will be a logic 1, and vice

versa.


Input-Output characteristics of an Inverter

Lets draw.


Amplifier vs. Inverter


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DC OperationVoltage Transfer Characteristic (VTC)

VIL Max. value vI can have while being interpreted as logic 0.

VIH Min. value vI can have while being interpreted as logic 1.


IsitInverter?

Exactvalueofinputdoesntmatter.

Noise Margins


Insensitivity of the inverter output to the exact value of vI within allowed regions is a great advantage that digital circuits have over analog circuits.

Consider an inverter driving inverter.

Noise Margins

Four parameters, VOH, VOL, VIH, and VIL, define the VTC of an inverter and determine its noise margins Changes in vI within the noise margins are rejected by the inverter. Noise is not allowed to propagate further through the system, a definite

advantage of digital over analog circuits. You can think of the inverter as restoring the signal levels to

standard values (VOL and VOH) even when it is presented with corrupted input signal levels (within the noise margins).


ImportantParametersoftheVTCoftheLogicInverter

Voltage Transfer Characteristic

Switching Threshold Voltage


Vin

Vout

VOH

VOL

VM

VOHVOL

Vout=Vin

SwitchingThreshold

NominalVoltageLevels

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Voltage Transfer Characteristic

Switching Threshold Voltage (VM) Output is short circuited with input.

Y. S. Chauhan, IIT Kanpur 45V(x)

V(y)

f

V(y)V(x)

VOH = f (VIL)

VIL VIH

V(y)=V(x)

Switching ThresholdVM

VOL = f (VIH)

Vout=f(Vin)

Mapping between analog and digital signals The regions of acceptable high and low voltages are delimited

by VIH and VIL that represent the points on the VTC curve where the gain = -1

Y. S. Chauhan, IIT Kanpur 46V IL V IH V in

Slope = -1

Slope = -1

V OL

V OH

Vout

0 VOL

VIL

VIH

VOH

UndefinedRegion

1

Noise Margins For robust circuits, want the 0 and 1 intervals to be as

large as possible


UndefinedRegion

"1"

"0"

Gate Output Gate Input

VOH

VIL

VOL

VIHNoise Margin High

Noise Margin Low

NMH = VOH - VIH

NML = VIL - VOL

Gnd

VDD VDD

Gnd

Large noise margins are desirable, but not sufficient

The Regenerative Property A gate with regenerative property ensure that a disturbed

signal converges back to a nominal voltage level


v0 v1 v2 v3 v4 v5 v6

-1

1

3

5

0 2 4 6 8 10

t (nsec)

V

(

v

o

l

t

s

) v0

v2

v1

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Conditions for Regeneration

To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smallerthan 1. Such a gate has two stable operating points.


v1 = f(v0) v1 = finv(v2)v0 v1 v2 v3 v4 v5 v6

v0

v1

v2

v3 f(v)

finv(v)

Regenerative Gate

v0

v1

v2

v3

f(v)

finv(v)

Nonregenerative Gate

in

out

in

out

Noise Immunity

Noise margin expresses the ability of a circuit to overpower a noise source noise sources: supply noise, cross talk, interference, offset

Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a

low impedance (in terms of voltage) Noise immunity expresses the ability of the system to

process and transmit information correctly in the presence of noise Transfer function between noise source and signal node is

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VTC of an ideal inverter


VTC of an ideal inverter The ideal gate should have

Infinite gain in the transition region Switching threshold located in the middle of the logic swing High and low noise margins equal to half the swing Input and output impedances of infinity and zero, respectively


Ri = Ro = 0Fanout = NMH = NML = VDD/2

g =

V in

V out

An Old-time Inverter

VOH=3.5V VIH=2.35V VM=1.64V NMH=1.15V

VOL=0.45V VIL=0.66V NML=0.21V


NM H

Vin (V)

V

o

u

t

(

V

)

NM L

VM

0.0

1.0

2.0

3.0

4.0

5.0

1.0 2.0 3.0 4.0 5.0

VOL

VOL

VOH

VOH

VIL VIH

Note Asymmetric NML is low Swing=3.05V

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Delay Definitions


t

Vout

Vin

inputwaveform

outputwaveform

tp =(tpHL +tpLH)/2

Propagationdelay

t

50%

tpHL

50%

tpLH

tf

90%

10%tr

signalslopes

Vin Vout

How fast we can toggle?

tpLH and tpHL can be asymmetric

Time period T> max(tpLH, tpHL)x2 If symmetric, T> max(tp)x2 Duty cycle

time for which it is ON/ (Time period) Usually its 50%: Rise and fall should occur within T/2 time


Vin Vout

How to compare delay in different technologies?


v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 tp N

RingOscillator

N=numberofinverters

Modeling Propagation Delay

Model circuit as first-order RC network


R

C

vin

vout

vout (t) = (1 et/)V

where = RCTime to reach 50% point is

0V

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R

C

vin

vout

vout (t) = (1 et/)V

where = RCTime to reach 90% from 10% point is

0V



Matches the delay of an inverter gateY. S. Chauhan, IIT Kanpur 62

R

C

vin

vout

vout (t) = (1 et/)V

where = RC

Time to reach 50% point ist = ln(2) = 0.69

Time to reach 90% from 10% point ist = ln(9) = 2.2

0V

Power and Energy Dissipation

Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates Supply line sizing (determined by peak power)

Ppeak = Vdd.ipeak=max(p(t)) Battery lifetime (determined by average power dissipation)

.

1

Packaging and cooling requirements


Static and Dynamic power

Two important components: static and dynamic Static power dissipation:

Caused by static conductive paths between the supply rails or by leakage currents.

Always present, even when the circuit is in stand-by. Minimization of this consumption source is a worthwhile goal.

Dynamic power dissipation: Occurs only during transients, when the gate is switching.

Charging of capacitors & temporary current paths between supply rails. Proportional to the switching frequency: the higher the number

of switching events, the higher the dynamic power consumption.


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A First-Order RC Network


vout

vin CL

R

E0 1 P t dt0

T

=

Energydissipatedfromsource

Energytransferredtocapacitor

Ecap Pcap t dt0

T

=

V(t)=VDD

V(t)=Vout

A First-Order RC Network


vout

vin CL

R

E0 1 P t dt0

T

Vdd isupply t dt0

T

Vdd CLdVout0

Vdd

CL Vdd 2= = = =

Energydissipatedfromsource

Energytransferredtocapacitor

Whereisotherhalf?

Ecap Pcap t dt0

T

Vouticap t dt0

T

CLVoutdVout0

Vdd

12---CL Vdd2

= = = =

Energy and Power


E (joules) = CL Vdd2 P01 + tsc Vdd Ipeak P01 + Vdd Ileakage

P (watts) = CL Vdd2 f01 + tscVdd Ipeak f01 + Vdd Ileakage

f01 = P01 * fclock

Energy and Energy-Delay

Propagation delay and power consumption of a gate are related Propagation delay is mostly determined by the speed at which a given

amount of energy can be stored on the gate capacitors. The faster the energy transfer (or the higher the power consumption),

the faster the gate. Product of power consumption and propagation delay is generally a

constant for a given technology and gate topology.

An ideal gate is one that is fast, and consumes little energy. The energy-delay product is a combined metric that brings those two

elements together, and is often used as the ultimate quality metric.


Power-Delay Product (PDP) =

E = Energy per operation = Pav tp

Energy-Delay Product (EDP) =

quality metric of gate = E tp

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Analog vs. DigitalAnalog Digital

1. Computewithcontinuousvaluesofphysicalvariablesinsomerange

Computewithdiscretevaluesofphysicalvariables

2. Primitivesofcomputationarisefromthephysicsofthecomputingdevices:physicalrelationsoftransistors,capacitors,resistors,floatinggatedevices,Kirchoffs currentandvoltagelawsandsoforth.Theuseoftheseprimitivesisanartformanddoesnotlenditselfeasilytoautomation. Theamountofcomputationsqueezedoutofasingletransistorishigh.

PrimitivesofcomputationarisefromthemathematicsofBooleanlogic:logicalrelationslikeAND,OR,NOT,NAND,andXOR.Theuseoftheseprimitivesisascienceandlendsitselfeasilytoautomation.Thetransistorisusedasaswitch,andtheamountofcomputationsqueezedoutofasingletransistorislow.

3. Computationisoffsetpronesinceitissensitivetomismatchesintheparametersofthephysicaldevices.Thedegradationinperformanceisgraceful.

Computationisnotoffsetpronesinceitisinsensitivetomismatchesintheparametersofthephysicaldevices.However,asinglebiterrorcanresultincatastrophicfailure.


Analog vs. Digital


Analog Digital4. Noiseisduetothermalfluctuationsin

physicaldevices.Noiseisduetoroundofferror.

5. Signalisnotrestoredateachstageofthecomputation.

Signalisrestoredto1or0ateachstageofthecomputation.

6. Inacascadeofanalogstages,noisestartstoaccumulate.Thus,complexsystemswithmanystagesaredifficulttobuild.

Roundofferrordoesnotaccumulatesignificantlyformanycomputations.Thus,complexsystemswithmanystagesareeasytobuild.

7. StaticpowerdissipationPA=N.VDD.I

Static powerisduetoleakagecurrentsonly.

8. Littleornodynamicpowerdissipation DynamicpowerconsumptionPD=N.f.C.VDD2

Inside chip


Acknowledgement

Jan M. Rabaey book Irwin & Vijays slides, Penn State University Sedra and Smith book S.S.K. Iyer, IIT Kanpur Course TAs


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